Search NASA⌕ Search

SEARCH · Search NASA

Results for “Floating Gate”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Astronomical Spectroscopy with Skipper CCDs: First Results from a Skipper CCD Focal Plane Prototype at SIFS

We present the first on-sky results from an ultra-low-readout-noise Skipper CCD focal plane prototype for the SOAR Integral Field Spectrograph (SIFS). The Skipper CCD focal plane consists of four 6k x 1k, 15 $\mu$m pixel, fully-depleted, p-channel devices that have been thinned to ~250 $\mu$m, backside processed, and treated with an anti-reflective coating. These Skipper CCDs were configured for astronomical spectroscopy, i.e., single-sample readout noise < 4.3 e- rms/pixel, the ability to achieve multi-sample readout noise $\ll$ 1 e- rms/pixel, full-well capacities ~40,000-65,000 e-, low dark current and charge transfer inefficiency (~2 x 10$^{-4}$ e-/pixel/s and 3.44 x 10$^{-7}$, respectively), and an absolute quantum efficiency of $\gtrsim$ 80% between 450 nm and 980 nm ($\gtrsim$ 90% between 600 nm and 900 nm). We optimized the readout sequence timing to achieve sub-electron noise (~0.5 e- rms/pixel) in a region of 2k x 4k pixels and photon-counting noise (~0.22 e- rms/pixel) in a region of 220 x 4k pixels, each with a readout time of $\lesssim$ 17 min. We observed two quasars (HB89 1159+123 and QSO J1621-0042) at redshift z ~ 3.5, two high-redshift galaxy clusters (CL J1001+0220 and SPT-CL J2040-4451), an emission line galaxy at z = 0.3239, a candidate member star of the Bo\"{o}tes II ultra-faint dwarf galaxy, and five CALSPEC spectrophotometric standard stars (HD074000, HD60753, HD106252, HD101452, HD200654). We present charge-quantized, photon-counting observations of the quasar HB89 1159+123 and show the detector sensitivity increase for faint spectral features. We demonstrate signal-to-noise performance improvements for SIFS observations in the low-background, readout-noise-dominated regime. We outline scientific studies that will leverage the SIFS-Skipper CCD data and new detector architectures that utilize the Skipper floating gate amplifier with faster readout times.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2026

In situ cryogenic characterization of proton damage in thick p-channel skipper CCDs

Skipper charge-coupled devices (CCDs) are an offshoot of standard silicon pixel detectors and are capable of performing repeated non-destructive charge measurements, enabling deeply sub-electron readout noise. This capability has opened the door to single-photon counting from the near-infrared ($\sim$1.1 $μ$m) to the soft X-ray (several keV), making these devices strong candidates for future astronomical instruments operating in the photon-starved limit. Furthermore, the p-channel architecture used to fabricate Skipper CCDs on n-type silicon has been demonstrated to have an increased hardness to the intense radiation environment of space. Building upon previous irradiation campaigns on room-temperature sensors, here we describe the first radiation-hardness tests of p-channel skipper CCDs at their cryogenic operating temperatures. We assess the performance of the floating-gate output stage and global CCD parameters (charge transfer inefficiency, dark current, hot pixels, and charge traps). We find that these devices maintain excellent performance after displacement damage doses equivalent to ${\sim}$10 years at the Earth/Sun L2 Lagrange point, demonstrating for the first time that these sensors remain radiation-hard in realistic deep-space thermal and radiation environments.

Roach, Brandon M. [Chicago U., KICP] (ORCID:000000↗
NASA NTRS1988

MOSFET Electric-Charge Sensor

Charged-particle probe compact and consumes little power. Proposed modification enables metal oxide/semiconductor field-effect transistor (MOSFET) to act as detector of static electric charges or energetic charged particles. Thickened gate insulation acts as control structure. During measurements metal gate allowed to "float" to potential of charge accumulated in insulation. Stack of modified MOSFET'S constitutes detector of energetic charged particles. Each gate "floats" to potential induced by charged-particle beam penetrating its layer.

Robinson, Paul A., Jr.↗
NASA NTRS2012

NAND Flash Qualification Guideline

Better performing Forward Error Correction on the forward link along with adequate power in the data open an uplink operations trade space that enable missions to: Command to greater distances in deep space (increased uplink margin). Increase the size of the payload data (latency may be a factor). Provides space for the security header/trailer of the CCSDS Space Data Link Security Protocol. Note: These higher rates could be used for relief of emergency communication margins/rates and not limited to improving top-end rate performance. A higher performance uplink could also reduce the requirements on flight emergency antenna size and/or the performance required from ground stations. Use of a selective repeat ARQ protocol may increase the uplink design requirements but the resultant development is deemed acceptable, due the factor of 4 to 8 potential increase in uplink data rate.

Floating Gate Memory↗
NASA NTRS2009

Comparison of TID Response and SEE Characterization of Single and Multi Level High Density NAND Flash Memories

Heavy ion single-event measurements and TID response for 8Gb commercial NAND flash memories are reported. Radiation results of multi-level flash technology are compared with results from single-level flash technology. In general, these commercial high density memories appear to be much less susceptible to SEE and have better TID response compared to older generations of flash memories. The charge pump survived up to 600 krads.

nonvolatile memory↗
NASA NTRS1989

Floating-diffusion electrometer with adjustable sensitivity

The effective capacitance of the floating diffusion in a floating-diffusion electrometer is modified to adjust electrometer sensitivity. This is done by changing the direct potential applied to a gate electrode proximate to the floating diffusion.

Tower, John R.↗
NASA NTRS1977

Design, fabrication, and evaluation of charge-coupled devices with aluminum-anodized-aluminum gates

A 4-phase, 49 1/2 bit CCD shift register was designed and fabricated using two levels of aluminum metallization with anodic Al2O3 insulation separating the layers. Test circuitry was also designed and constructed. A numerical analysis of an MOS-RC transmission line was made and results are given to characterize performance for various conductivities. The electrical design of the CCD included a low-noise dual-gate input and a balanced floating diffusion output circuit. Metallization was accomplished both by low voltage DC sputtering and thermal evaporation. The audization was according to published procedures using a buffered tartaric acid bath. Approximately 20 wafers were processed with 50 complete chips per wafer. All devices failed by shorting between the metal levels at some point. Experimental procedures eliminated temperature effects from sintering and drying, anodic oxide thickness, edge effects, photoresist stripping procedures, and metallization techniques as the primary causes of failure. It was believed from a study of SEM images that protuberances (hillocks) grow up from the first level metal through the oxide either causing a direct short or producing a weak, highly stressed insulation point which fails at low voltage. The cause of these hillocks is unknown; however, they have been observed to grow during temperature excursions to 470 C.

Gassaway, J. D.↗
NASA NTRS2011

CMOS Imager Has Better Cross-Talk and Full-Well Performance

A complementary metal oxide/semiconductor (CMOS) image detector now undergoing development is designed to exhibit less cross-talk and greater full-well capacity than do prior CMOS image detectors of the same type. Imagers of the type in question are designed to operate from low-voltage power supplies and are fabricated by processes that yield device features having dimensions in the deep submicron range. Because of the use of low supply potentials, maximum internal electric fields and depletion widths are correspondingly limited. In turn, these limitations are responsible for increases in cross-talk and decreases in charge-handling capacities. Moreover, for small pixels, lateral depletion cannot be extended. These adverse effects are even more accentuated in a back-illuminated CMOS imager, in which photogenerated charge carriers must travel across the entire thickness of the device. The figure shows a partial cross section of the structure in the device layer of the present developmental CMOS imager. (In a practical imager, the device layer would sit atop either a heavily doped silicon substrate or a thin silicon oxide layer on a silicon substrate, not shown here.) The imager chip is divided into two areas: area C, which contains readout circuits and other electronic circuits; and area I, which contains the imaging (photodetector and photogenerated-charge-collecting) pixel structures. Areas C and I are electrically isolated from each other by means of a trench filled with silicon oxide. The electrical isolation between areas C and I makes it possible to apply different supply potentials to these areas, thereby enabling optimization of the supply potential and associated design features for each area. More specifically, metal oxide semiconductor field-effect transistors (MOSFETs) that are typically included in CMOS imagers now reside in area C and can remain unchanged from established designs and operated at supply potentials prescribed for those designs, while the dopings and the lower supply potentials in area I can be tailored to optimize imager performance. In area I, the device layer includes an n+ -doped silicon layer on which is grown an n-doped silicon layer. A p-doped silicon layer is grown on top of the n -doped layer. The total imaging device thickness is the sum of the thickness of the n+, n, and p layers. A pixel photodiode is formed between a surface n+ implant, a p implant underneath it, the aforementioned p layer, and the n and n+ layers. Adjacent to the diode is a gate for transferring photogenerated charges out of the photodiode and into a floating diffusion formed by an implanted p+ layer on an implanted n-doped region. Metal contact pads are added to the back-side for providing back-side bias.

Pain, Bedabrata↗
NASA NTRS2016

Fabrication of a Silicon Nanowire on a Bulk Substrate by Use of a Plasma Etching and Total Ionizing Dose Effects on a Gate-All-Around Field-Effect Transistor

The gate all around transistor is investigated through experiment. The suspended silicon nanowire for the next generation is fabricated on bulk substrate by plasma etching method. The scallop pattern generated by Bosch process is utilized to form a floating silicon nanowire. By combining anisotropic and istropic silicon etch process, the shape of nanowire is accurately controlled. From the suspended nanowire, the gate all around transistor is demonstrated. As the silicon nanowire is fully surrounded by the gate, the device shows excellent electrostatic characteristics.

Transistor↗
NASA NTRS2020

Progress in Interferometric Rayleigh Scattering to Measure Fluctuations Spectra of Velocity and Temperature in High Speed Flows

A new, spectrally-resolved, Rayleigh scattering setup at NASA Ames is further developed to measure fluctuations in velocity and temperature. Using a combination of a continuous-wave laser, a stabilized Fabry-Perot interferometer (FPI), an EMCCD camera, and a photo-multiplier tube, the setup was demonstrated to provide fairly accurate measurements of time-averaged velocity, temperature, density and spectrum of density fluctuations in a high-speed free jet (Panda & White, 2018). This paper describes further progress in fast measurement of the Rayleigh-Brillouin spectrum via a 16-anode linear-array of photo-multiplier tube and a multi-channel, photo-electron counter. Rayleigh scattered light from a 0.4mm long probe volume was directly imaged through the FPI and was imaged on the linear array. Synchronous photo-electron counting over a series of short, contiguous gates provided time-evolution of the fringes at a 10 kHz sampling rate. Sample spectra collected from a Mach 0.98 jet show spectral content floating on high noise-floor. Efforts to collect longer time series of data and different schemes of extracting velocity and temperature information are now in progress.

Panda, J.↗
DOE OSTI2024

On the Origin of Holes During Polarization Reset in Floating Body Ferroelectric FETs Towards Improving Switching Efficiency

In this article, we performed a comprehensive combined experimental and modeling study on the polarization reset mechanisms of floating body (i.e., channel) ferroelectric FETs, an important class of device with growing interests due to added functionalities and improved reliabilities. Using fully-depleted silicon-on-insulator (FDSOI) FeFET as a classical example, we demonstrate that: 1) without hole generation mechanisms, floating body FeFETs during reset is simply a capacitor divider, with negligible ferroelectric voltage drop for switching; ii) Band-to-band-tunneling (BTBT) around gate-to-S/D overlap even with zero drain bias generates holes to facilitate the reset in FDSOI FeFET, though at a slower speed and hold the reset state; iii) With scaling, S/D inner fringe field can enable fast reset, thus offering a potential efficiency boost approach; iv) a compact FDSOI FeFET model is developed that can capture the BTBT effect and reproduce the observed behaviors; v) the reset mechanism is also validated in a NAND string composed of FDSOI FeFETs, demonstrating its relevant applications. These insights show the strategies in improving reset efficiency, i.e., enhanced BTBT and inner fringe field.

42 ENGINEERING↗
NASA NTRS2004

A Discussion of Using a Reconfigurable Processor to Implement the Discrete Fourier Transform

This paper presents the design and implementation of the Discrete Fourier Transform (DFT) algorithm on a reconfigurable processor system. While highly applicable to many engineering problems, the DFT is an extremely computationally intensive algorithm. Consequently, the eventual goal of this work is to enhance the execution of a floating-point precision DFT algorithm by off loading the algorithm from the computing system. This computing system, within the context of this research, is a typical high performance desktop computer with an may of field programmable gate arrays (FPGAs). FPGAs are hardware devices that are configured by software to execute an algorithm. If it is desired to change the algorithm, the software is changed to reflect the modification, then download to the FPGA, which is then itself modified. This paper will discuss methodology for developing the DFT algorithm to be implemented on the FPGA. We will discuss the algorithm, the FPGA code effort, and the results to date.

White, Michael J.↗
NASA NTRS1971

Digital telemetry system eliminates data redundancy

Floating aperature, zero-order predictor /ZOP/ circuit eliminates telemetered data redundancy by examining data from each sensor before it is multiplexed and transmitted. Digital devices to implement design are off-the-shelf items such as gates, registers and flip-flops, which are readily amenable to large-scale integration techniques.

Hymer, R. L.↗
NASA NTRS1986

MOSFET Power Controller

High current and voltage controlled remotely. Remote Power Conroller includes two series-connected banks of parallel-connected MOSFET's to withstand high current and voltage. Voltage sharing between switch banks, low-impedance, gate-drive circuits used. Provided controlled range for turn on. Individually trimmable to insure simultaneous switching within few nanoseconds during both turn on and turn off. Control circuit for each switch bank and over-current trip circuit float independently and supplied power via transformer T1 from inverter. Control of floating stages by optocouplers.

Mitchell, J.↗
NASA NTRS1987

The fault-tree compiler

The Fault Tree Compiler Program is a new reliability tool used to predict the top event probability for a fault tree. Five different gate types are allowed in the fault tree: AND, OR, EXCLUSIVE OR, INVERT, and M OF N gates. The high level input language is easy to understand and use when describing the system tree. In addition, the use of the hierarchical fault tree capability can simplify the tree description and decrease program execution time. The current solution technique provides an answer precise (within the limits of double precision floating point arithmetic) to the five digits in the answer. The user may vary one failure rate or failure probability over a range of values and plot the results for sensitivity analyses. The solution technique is implemented in FORTRAN; the remaining program code is implemented in Pascal. The program is written to run on a Digital Corporation VAX with the VMS operation system.

Martensen, Anna L.↗
NASA NTRS1989

The Fault Tree Compiler (FTC): Program and mathematics

The Fault Tree Compiler Program is a new reliability tool used to predict the top-event probability for a fault tree. Five different gate types are allowed in the fault tree: AND, OR, EXCLUSIVE OR, INVERT, AND m OF n gates. The high-level input language is easy to understand and use when describing the system tree. In addition, the use of the hierarchical fault tree capability can simplify the tree description and decrease program execution time. The current solution technique provides an answer precisely (within the limits of double precision floating point arithmetic) within a user specified number of digits accuracy. The user may vary one failure rate or failure probability over a range of values and plot the results for sensitivity analyses. The solution technique is implemented in FORTRAN; the remaining program code is implemented in Pascal. The program is written to run on a Digital Equipment Corporation (DEC) VAX computer with the VMS operation system.

Butler, Ricky W.↗