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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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53 records · Page 3
All sourcesNASA NTRSDOE OSTI
NASA NTRS2012

NAND Flash Qualification Guideline

Better performing Forward Error Correction on the forward link along with adequate power in the data open an uplink operations trade space that enable missions to: Command to greater distances in deep space (increased uplink margin). Increase the size of the payload data (latency may be a factor). Provides space for the security header/trailer of the CCSDS Space Data Link Security Protocol. Note: These higher rates could be used for relief of emergency communication margins/rates and not limited to improving top-end rate performance. A higher performance uplink could also reduce the requirements on flight emergency antenna size and/or the performance required from ground stations. Use of a selective repeat ARQ protocol may increase the uplink design requirements but the resultant development is deemed acceptable, due the factor of 4 to 8 potential increase in uplink data rate.

Floating Gate Memory↗
NASA NTRS2009

Comparison of TID Response and SEE Characterization of Single and Multi Level High Density NAND Flash Memories

Heavy ion single-event measurements and TID response for 8Gb commercial NAND flash memories are reported. Radiation results of multi-level flash technology are compared with results from single-level flash technology. In general, these commercial high density memories appear to be much less susceptible to SEE and have better TID response compared to older generations of flash memories. The charge pump survived up to 600 krads.

nonvolatile memory↗
NASA NTRS1989

Floating-diffusion electrometer with adjustable sensitivity

The effective capacitance of the floating diffusion in a floating-diffusion electrometer is modified to adjust electrometer sensitivity. This is done by changing the direct potential applied to a gate electrode proximate to the floating diffusion.

Tower, John R.↗
NASA NTRS1977

Design, fabrication, and evaluation of charge-coupled devices with aluminum-anodized-aluminum gates

A 4-phase, 49 1/2 bit CCD shift register was designed and fabricated using two levels of aluminum metallization with anodic Al2O3 insulation separating the layers. Test circuitry was also designed and constructed. A numerical analysis of an MOS-RC transmission line was made and results are given to characterize performance for various conductivities. The electrical design of the CCD included a low-noise dual-gate input and a balanced floating diffusion output circuit. Metallization was accomplished both by low voltage DC sputtering and thermal evaporation. The audization was according to published procedures using a buffered tartaric acid bath. Approximately 20 wafers were processed with 50 complete chips per wafer. All devices failed by shorting between the metal levels at some point. Experimental procedures eliminated temperature effects from sintering and drying, anodic oxide thickness, edge effects, photoresist stripping procedures, and metallization techniques as the primary causes of failure. It was believed from a study of SEM images that protuberances (hillocks) grow up from the first level metal through the oxide either causing a direct short or producing a weak, highly stressed insulation point which fails at low voltage. The cause of these hillocks is unknown; however, they have been observed to grow during temperature excursions to 470 C.

Gassaway, J. D.↗
NASA NTRS2011

CMOS Imager Has Better Cross-Talk and Full-Well Performance

A complementary metal oxide/semiconductor (CMOS) image detector now undergoing development is designed to exhibit less cross-talk and greater full-well capacity than do prior CMOS image detectors of the same type. Imagers of the type in question are designed to operate from low-voltage power supplies and are fabricated by processes that yield device features having dimensions in the deep submicron range. Because of the use of low supply potentials, maximum internal electric fields and depletion widths are correspondingly limited. In turn, these limitations are responsible for increases in cross-talk and decreases in charge-handling capacities. Moreover, for small pixels, lateral depletion cannot be extended. These adverse effects are even more accentuated in a back-illuminated CMOS imager, in which photogenerated charge carriers must travel across the entire thickness of the device. The figure shows a partial cross section of the structure in the device layer of the present developmental CMOS imager. (In a practical imager, the device layer would sit atop either a heavily doped silicon substrate or a thin silicon oxide layer on a silicon substrate, not shown here.) The imager chip is divided into two areas: area C, which contains readout circuits and other electronic circuits; and area I, which contains the imaging (photodetector and photogenerated-charge-collecting) pixel structures. Areas C and I are electrically isolated from each other by means of a trench filled with silicon oxide. The electrical isolation between areas C and I makes it possible to apply different supply potentials to these areas, thereby enabling optimization of the supply potential and associated design features for each area. More specifically, metal oxide semiconductor field-effect transistors (MOSFETs) that are typically included in CMOS imagers now reside in area C and can remain unchanged from established designs and operated at supply potentials prescribed for those designs, while the dopings and the lower supply potentials in area I can be tailored to optimize imager performance. In area I, the device layer includes an n+ -doped silicon layer on which is grown an n-doped silicon layer. A p-doped silicon layer is grown on top of the n -doped layer. The total imaging device thickness is the sum of the thickness of the n+, n, and p layers. A pixel photodiode is formed between a surface n+ implant, a p implant underneath it, the aforementioned p layer, and the n and n+ layers. Adjacent to the diode is a gate for transferring photogenerated charges out of the photodiode and into a floating diffusion formed by an implanted p+ layer on an implanted n-doped region. Metal contact pads are added to the back-side for providing back-side bias.

Pain, Bedabrata↗
NASA NTRS2016

Fabrication of a Silicon Nanowire on a Bulk Substrate by Use of a Plasma Etching and Total Ionizing Dose Effects on a Gate-All-Around Field-Effect Transistor

The gate all around transistor is investigated through experiment. The suspended silicon nanowire for the next generation is fabricated on bulk substrate by plasma etching method. The scallop pattern generated by Bosch process is utilized to form a floating silicon nanowire. By combining anisotropic and istropic silicon etch process, the shape of nanowire is accurately controlled. From the suspended nanowire, the gate all around transistor is demonstrated. As the silicon nanowire is fully surrounded by the gate, the device shows excellent electrostatic characteristics.

Transistor↗
NASA NTRS2020

Progress in Interferometric Rayleigh Scattering to Measure Fluctuations Spectra of Velocity and Temperature in High Speed Flows

A new, spectrally-resolved, Rayleigh scattering setup at NASA Ames is further developed to measure fluctuations in velocity and temperature. Using a combination of a continuous-wave laser, a stabilized Fabry-Perot interferometer (FPI), an EMCCD camera, and a photo-multiplier tube, the setup was demonstrated to provide fairly accurate measurements of time-averaged velocity, temperature, density and spectrum of density fluctuations in a high-speed free jet (Panda & White, 2018). This paper describes further progress in fast measurement of the Rayleigh-Brillouin spectrum via a 16-anode linear-array of photo-multiplier tube and a multi-channel, photo-electron counter. Rayleigh scattered light from a 0.4mm long probe volume was directly imaged through the FPI and was imaged on the linear array. Synchronous photo-electron counting over a series of short, contiguous gates provided time-evolution of the fringes at a 10 kHz sampling rate. Sample spectra collected from a Mach 0.98 jet show spectral content floating on high noise-floor. Efforts to collect longer time series of data and different schemes of extracting velocity and temperature information are now in progress.

Panda, J.↗
NASA NTRS2004

A Discussion of Using a Reconfigurable Processor to Implement the Discrete Fourier Transform

This paper presents the design and implementation of the Discrete Fourier Transform (DFT) algorithm on a reconfigurable processor system. While highly applicable to many engineering problems, the DFT is an extremely computationally intensive algorithm. Consequently, the eventual goal of this work is to enhance the execution of a floating-point precision DFT algorithm by off loading the algorithm from the computing system. This computing system, within the context of this research, is a typical high performance desktop computer with an may of field programmable gate arrays (FPGAs). FPGAs are hardware devices that are configured by software to execute an algorithm. If it is desired to change the algorithm, the software is changed to reflect the modification, then download to the FPGA, which is then itself modified. This paper will discuss methodology for developing the DFT algorithm to be implemented on the FPGA. We will discuss the algorithm, the FPGA code effort, and the results to date.

White, Michael J.↗
NASA NTRS1971

Digital telemetry system eliminates data redundancy

Floating aperature, zero-order predictor /ZOP/ circuit eliminates telemetered data redundancy by examining data from each sensor before it is multiplexed and transmitted. Digital devices to implement design are off-the-shelf items such as gates, registers and flip-flops, which are readily amenable to large-scale integration techniques.

Hymer, R. L.↗
NASA NTRS1986

MOSFET Power Controller

High current and voltage controlled remotely. Remote Power Conroller includes two series-connected banks of parallel-connected MOSFET's to withstand high current and voltage. Voltage sharing between switch banks, low-impedance, gate-drive circuits used. Provided controlled range for turn on. Individually trimmable to insure simultaneous switching within few nanoseconds during both turn on and turn off. Control circuit for each switch bank and over-current trip circuit float independently and supplied power via transformer T1 from inverter. Control of floating stages by optocouplers.

Mitchell, J.↗
NASA NTRS1987

The fault-tree compiler

The Fault Tree Compiler Program is a new reliability tool used to predict the top event probability for a fault tree. Five different gate types are allowed in the fault tree: AND, OR, EXCLUSIVE OR, INVERT, and M OF N gates. The high level input language is easy to understand and use when describing the system tree. In addition, the use of the hierarchical fault tree capability can simplify the tree description and decrease program execution time. The current solution technique provides an answer precise (within the limits of double precision floating point arithmetic) to the five digits in the answer. The user may vary one failure rate or failure probability over a range of values and plot the results for sensitivity analyses. The solution technique is implemented in FORTRAN; the remaining program code is implemented in Pascal. The program is written to run on a Digital Corporation VAX with the VMS operation system.

Martensen, Anna L.↗
NASA NTRS1989

The Fault Tree Compiler (FTC): Program and mathematics

The Fault Tree Compiler Program is a new reliability tool used to predict the top-event probability for a fault tree. Five different gate types are allowed in the fault tree: AND, OR, EXCLUSIVE OR, INVERT, AND m OF n gates. The high-level input language is easy to understand and use when describing the system tree. In addition, the use of the hierarchical fault tree capability can simplify the tree description and decrease program execution time. The current solution technique provides an answer precisely (within the limits of double precision floating point arithmetic) within a user specified number of digits accuracy. The user may vary one failure rate or failure probability over a range of values and plot the results for sensitivity analyses. The solution technique is implemented in FORTRAN; the remaining program code is implemented in Pascal. The program is written to run on a Digital Equipment Corporation (DEC) VAX computer with the VMS operation system.

Butler, Ricky W.↗
NASA NTRS2011

Fast Image Texture Classification Using Decision Trees

Texture analysis would permit improved autonomous, onboard science data interpretation for adaptive navigation, sampling, and downlink decisions. These analyses would assist with terrain analysis and instrument placement in both macroscopic and microscopic image data products. Unfortunately, most state-of-the-art texture analysis demands computationally expensive convolutions of filters involving many floating-point operations. This makes them infeasible for radiation- hardened computers and spaceflight hardware. A new method approximates traditional texture classification of each image pixel with a fast decision-tree classifier. The classifier uses image features derived from simple filtering operations involving integer arithmetic. The texture analysis method is therefore amenable to implementation on FPGA (field-programmable gate array) hardware. Image features based on the "integral image" transform produce descriptive and efficient texture descriptors. Training the decision tree on a set of training data yields a classification scheme that produces reasonable approximations of optimal "texton" analysis at a fraction of the computational cost. A decision-tree learning algorithm employing the traditional k-means criterion of inter-cluster variance is used to learn tree structure from training data. The result is an efficient and accurate summary of surface morphology in images. This work is an evolutionary advance that unites several previous algorithms (k-means clustering, integral images, decision trees) and applies them to a new problem domain (morphology analysis for autonomous science during remote exploration). Advantages include order-of-magnitude improvements in runtime, feasibility for FPGA hardware, and significant improvements in texture classification accuracy.

Thompson, David R.↗
NASA NTRS1992

Performance of a multistep fluorescence-gated proportional counter for hard X-ray astronomy

Results from the first flight of our proportional counter in an imaging telescope led us to rebuild the detector. We have used a Penning gas mixture (xenon + 1 percent isobutylene) and introduced a preamplification region to improve the energy resolution. We have rebuilt the pressure vessel making novel use of molybdenum as the housing material in order to reduce the residual instrument background, particularly in the fluorescence-gated mode for which the detector design has been optimized. We have also increased the sensitive gas depth from 9 to 14 cm to further increase the sensitivity to both fluorescent pairs and conventional singles. Our calibrations have shown that the overall energy resolution of the detector has been enhanced by a factor of 2, and we predict that the sensitivity at float will increase by a factor of 3 in the 50-70 keV energy band.

Dietz, K. L.↗
NASA NTRS2011

SpaceCube 2.0: An Advanced Hybrid Onboard Data Processor

The SpaceCube 2.0 is a compact, high performance, low-power onboard processing system that takes advantage of cutting-edge hybrid (CPU/FPGA/DSP) processing elements. The SpaceCube 2.0 design concept includes two commercial Virtex-5 field-programmable gate array (FPGA) parts protected by gradiation hardened by software" technology, and possesses exceptional size, weight, and power characteristics [5x5x7 in., 3.5 lb (approximately equal to 12.7 x 12.7 x 17.8 cm, 1.6 kg) 5-25 W, depending on the application fs required clock rate]. The two Virtex-5 FPGA parts are implemented in a unique back-toback configuration to maximize data transfer and computing performance. Draft computing power specifications for the SpaceCube 2.0 unit include four PowerPC 440s (1100 DMIPS each), 500+ DSP48Es (2x580 GMACS), 100+ LVDS high-speed serial I/Os (1.25 Gbps each), and 2x190 GFLOPS single-precision (65 GFLOPS double-precision) floating point performance. The SpaceCube 2.0 includes PROM memory for CPU boot, health and safety, and basic command and telemetry functionality; RAM memory for program execution; and FLASH/EEPROM memory to store algorithms and application code for the CPU, FPGA, and DSP processing elements. Program execution can be reconfigured in real time and algorithms can be updated, modified, and/or replaced at any point during the mission. Gigabit Ethernet, Spacewire, SATA and highspeed LVDS serial/parallel I/O channels are available for instrument/sensor data ingest, and mission-unique instrument interfaces can be accommodated using a compact PCI (cPCI) expansion card interface. The SpaceCube 2.0 can be utilized in NASA Earth Science, Helio/Astrophysics and Exploration missions, and Department of Defense satellites for onboard data processing. It can also be used in commercial communication and mapping satellites.

Lin, Michael↗
NASA NTRS1995

AMCC casting development. Volume 1: Executive Summary

The Advanced Combustion Chamber Casting (AMCC) has been a technically challenging part due to its size, configuration, and alloy type. The height and weight of the wax pattern assembly necessitated the development of a hollow gating system to ensure structural integrity of the shell throughout the investment process. The complexity in the jacket area of the casting required the development of an innovative casting technology that PCC has termed 'TGC' or Thermal Gradient Control. This method, of setting up thermal gradients in the casting during solidification, represents a significant process improvement for PCC and has been successfully implemented on other programs. Metallurgical integrity of the final four castings was very good. Only the areas of the parts that utilized 'TGC Shape & Location System #2' showed any significant areas of microshrinkage when evaluated by non-destructive tests. Alumina oxides detected by FPI on the 'float' surfaces (top sid surfaces of the casting during solidification) of the part were almost entirely less than the acceptance criteria of .032 inches in diameter. Destructive chem mill of the castings was required to determine the effect of the process variables used during the processing of these last four parts (with the exception of the 'Shape & Location of TGC' variable).

Source record↗
NASA NTRS1990

Turbomachinery rotor support with damping

Damping seals, damping bearings, and a support sleeve are presented for the ball bearings of a high speed rotor. The ball bearings consist of a duplex set having the outer races packaged tightly within the sleeve while the sleeve provides a gap with a support member so that the bearings may float with the sleeve. The sleeve has a web extending radially between the pair of outer races and acts in conjunction with one or more springs to apply an axial preload to the outer races. The sleeves have a series of slits which provide the sleeve with a spring-like quality so that the spring acts to center the rotor upon which the bearings are mounted during start up and shut down. A damping seal or a damping bearing may be used in conjunction with the ball bearings and supporting sleeve, the damping seal and damping bearing having rotor portions including rigid outer surfaces mounted within the bore of a stator portion having triangular shaped pockets on the surface facing the rotor. Axial gates are provided between adjacent pockets in sections of the stator permitting fluid to flow with less resistance axially relative to the flow of fluids circumferentially between the rotor and the stator.

Vonpragenau, George L.↗