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At least 55 records · Page 3

All sources NASA NTRS DOE OSTI

DOE OSTI2018

PIMS: Memristor-Based Processing-in-Memory-and-Storage.

Continued progress in computing has augmented the quest for higher performance with a new quest for higher energy efficiency. This has led to the re-emergence of Processing-In-Memory (PIM) ar- chitectures that offer higher density and performance with some boost in energy efficiency. Past PIM work either integrated a standard CPU with a conventional DRAM to improve the CPU- memory link, or used a bit-level processor with Single Instruction Multiple Data (SIMD) control, but neither matched the energy consumption of the memory to the computation. We originally proposed to develop a new architecture derived from PIM that more effectively addressed energy efficiency for high performance scientific, data analytics, and neuromorphic applications. We also originally planned to implement a von Neumann architecture with arithmetic/logic units (ALUs) that matched the power consumption of an advanced storage array to maximize energy efficiency. Implementing this architecture in storage was our original idea, since by augmenting storage (in- stead of memory), the system could address both in-memory computation and applications that accessed larger data sets directly from storage, hence Processing-in-Memory-and-Storage (PIMS). However, as our research matured, we discovered several things that changed our original direc- tion, the most important being that a PIM that implements a standard von Neumann-type archi- tecture results in significant energy efficiency improvement, but only about a O(10) performance improvement. In addition to this, the emergence of new memory technologies moved us to propos- ing a non-von Neumann architecture, called Superstrider, implemented not in storage, but in a new DRAM technology called High Bandwidth Memory (HBM). HBM is a stacked DRAM tech- nology that includes a logic layer where an architecture such as Superstrider could potentially be implemented.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2021

Performance Characteristics of the BlueField-2 SmartNIC

High-performance computing (HPC) researchers have long envisioned scenarios where application workflows could be improved through the use of programmable processing elements embedded in the network fabric. Recently, vendors have introduced programmable Smart Network Interface Cards (SmartNICs) that enable computations to be offloaded to the edge of the network. There is great interest in both the HPC and high-performance data analytics (HPDA) communities in understanding the roles these devices may play in the data paths of upcoming systems. This paper focuses on characterizing both the networking and computing aspects of NVIDIA’s new BlueField-2 SmartNIC when used in a 100Gb/s Ethernet environment. For the networking evaluation we conducted multiple transfer experiments between processors located at the host, the SmartNIC, and a remote host. These tests illuminate how much effort is required to saturate the network and help estimate the processing headroom available on the SmartNIC during transfers. For the computing evaluation we used the stress-ng benchmark to compare the BlueField-2 to other servers and place realistic bounds on the types of offload operations that are appropriate for the hardware. Our findings from this work indicate that while the BlueField-2 provides a flexible means of processing data at the network’s edge, great care must be taken to not overwhelm the hardware. While the host can easily saturate the network link, the SmartNIC’s embedded processors may not have enough computing resources to sustain more than half the expected bandwidth when using kernel-space packet processing. From a computational perspective, encryption operations, memory operations under contention, and on-card IPC operations on the SmartNIC perform significantly better than the general-purpose servers used for comparisons in our experiments. Therefore, applications that mainly focus on these operations may be good candidates for offloading to the SmartNIC.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2022

In situ data acquisition and real-time analysis system

A testing system for evaluating the performance of an electrical/electronic UUT under dynamic operating conditions. The testing system includes a dynamic testing component (e.g., a centrifuge) for applying a stimulus to the UUT, and an iDAQ system configured to perform in situ data acquisition and real-time data analysis. The iDAQ system may also be subject to the stimulus. The iDAQ system includes a processor (e.g., an SoC) component, a power supply, a CR/I component, an IR component, and a single enclosure. The processor component may control the dynamic testing component, including varying in real-time the stimulus applied to the UUT. The processor component may include multiple input channels, and a high current/voltage subcomponent of the power supply may be configured to supply up to five hundred volts.

Benyhesan, Mohammad K.↗

DOE OSTI2019

Coupled‐cluster singles, doubles and perturbative triples with density fitting approximation for massively parallel heterogeneous platforms

Abstract A high‐performance implementation of the coupled‐cluster singles, doubles, and perturbative triples [CCSD(T)] is developed in the Massively Parallel Quantum Chemistry program. Novel features include: (1) reduced memory requirements via a density‐fitting (DF) CCSD implementation utilizing distributed lazy evaluation for tensors with more than two unoccupied indices and (2) the ability to utilize efficiently many‐core nodes (Intel Xeon Phi) and heterogeneous nodes with multiple NVIDIA GPUs on each node. All data that are greater than quadratic in the system size are distributed among processes. Excellent strong scaling is observed on distributed‐memory computers equipped with conventional CPUs, Intel Xeon Phi processors, and heterogeneous nodes with multiple NVIDIA GPUs Canonical CCSD(T) energies can be evaluated for systems containing 200 electrons and 1000 basis functions in a few days using a small size commodity cluster, with even larger computations possible on leadership‐class computing resources.

Peng, Chong↗

DOE OSTI2021

Developing an Automated Uncertainty Quantification Tool to Improve Watershed-Scale Predictions of Water and Nutrient Cycling

Managing the flow of water, nutrients, and contaminants in watersheds is vital to addressing pressing issues related to water scarcity, access to clean drinking water, energy production, resilience to natural and anthropogenic perturbations, and ecological restoration. Decisions about the management of watersheds critically depend on the accuracy with which the flow of water and chemicals through the watershed can be predicted by computer models. Prediction uncertainty can be reduced by matching the model to data, which are collected in the field at great expense. The contribution of watershed characterization data to reducing uncertainty of relevant model predictions can be evaluated in a so-called data-worth analysis, which provides transparent, quantitative metrics about a data set’s value for the support of relevant watershed management objectives. To achieve this goal, we developed a software package that implements the data-worth analysis approach for use with state-of-the-art watershed models. The purpose of the proposed data-worth analysis is to help decision-makers allocate resources for watershed characterization such that the uncertainty in model predictions can be significantly reduced, which leads to better, more effective management decisions. At the same time, watershed characterization costs can be reduced. The specific technical objectives of this SBIR/STTR Phase II project were to develop a framework and associated software toolsets that implement the uncertainty quantification and data-worth analysis approach for use with state-of-the-art watershed models. This goal was achieved by (A) developing a user-friendly, robust software package that is accessible to a wide audience, including watershed managers, policy-makers, and public stakeholders; (B) by demonstrating application of the prototype on several use cases that are representative of complex watershed management challenges spanning a range of scales and that consider different open-source, DOE-based codes and other modeling platforms; and (C) by gathering information about the needs and requirements from potential users to help guide future developments, ensuring that the final product will be commercially viable. The developed software consists of a graphical user interface that guides the user through a sequence of analysis steps, supported by toolsets that leverage state-of-the-art computational simulation-optimization capabilities. A prototype of the software runs on multiple platforms (PC, Mac, multi-processor Linux environment), is linked to diverse watershed simulators (e.g., ECOSYS, TOUGH2, TOUGHREACT, Amanzi-ATS), performs multiple analysis tasks (predictive simulations, sensitivity analysis, uncertainty analysis, automatic parameter estimation, and data-worth analysis, multicomponent geothermometry), and is readily extensible to include external simulators and analysis tools. The software is being commercialized and will be continually updated to address user needs.

58 GEOSCIENCES↗

DOE OSTI2022

Relaxation of stationary states on a quantum computer yields a unique spectroscopic fingerprint of the computer’s noise

Abstract Quantum computing has the potential to revolutionize computing, but its significant sensitivity to noise requires sophisticated error correction and mitigation. Traditionally, noise on the quantum device is characterized directly through qubit and gate measurements, but this approach has drawbacks in that it does not adequately capture the effect of noise on realistic multi-qubit applications. In this paper, we simulate the relaxation of stationary quantum states on a quantum computer to obtain a unique spectroscopic fingerprint of the computer’s noise. In contrast to traditional approaches, we obtain the frequency profile of the noise as it is experienced by the simulated stationary quantum states. Data from multiple superconducting-qubit IBM processors show that noise generates a bath within the simulation that exhibits both colored noise and non-Markovian behavior. Our results provide a direction for noise mitigation but also suggest how to use noise for quantum simulations of open systems.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2022

Controlling prediction functional blocks used by a branch predictor in a processor

An electronic device includes a processor, a branch predictor in the processor, and a predictor controller in the processor. The branch predictor includes multiple prediction functional blocks, each prediction functional block configured for generating predictions for control transfer instructions (CTIs) in program code based on respective prediction information, the branch predictor configured to select, from among predictions generated by the prediction functional blocks for each CTI, a selected prediction to be used for that CTI. The predictor controller keeps a record of prediction functional blocks from which the branch predictor previously selected predictions for CTIs. The predictor controller uses information from the record for controlling which prediction functional blocks are used by the branch predictor for generating predictions for CTIs.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2018

Symplectic multi-particle tracking on GPUs

A symplectic multi-particle tracking model is implemented on the Graphic Processing Units (GPUs) using the Compute Unified Device Architecture (CUDA) language. The symplectic tracking model can preserve phase space structure and reduce non-physical effects in long term simulation, which is important for beam property evaluation in particle accelerators. Though this model is computationally expensive, it is very suitable for parallelization and can be accelerated significantly by using GPUs. In this paper, we optimized the implementation of the symplectic tracking model on both single GPU and multiple GPUs. Using a single GPU processor, the code achieves a factor of 2-10 speedup for a range of problem sizes compared with the time on a single state-of-the-art Central Processing Unit (CPU) node with similar power consumption and semiconductor technology. It also shows good scalability on a multi-GPU cluster at Oak Ridge Leadership Computing Facility. In an application to beam dynamics simulation, the GPU implementation helps save more than a factor of two total computing time in comparison to the CPU implementation.

43 PARTICLE ACCELERATORS↗

DOE OSTI2026

Classic and Quantum Task-Based Intelligent Runtime for QIRs Running on Multiple QPUs

High-performance computing systems are rapidly evolving into heterogeneous platforms that fuse quantum accelerators with traditional classical processing units (CPUs) and graphical processing units (GPUs). This convergence calls for runtimes capable of managing both classical and quantum workloads in a unified manner. We introduce an intelligent, task-based runtime that marries the Intelligent RuntIme System (IRIS) asynchronous scheduler with a quantum programming stack through the Quantum Intermediate Representation Execution Engine (QIR-EE). Our design allows programs written in the quantum intermediate representation (QIR) to be dispatched concurrently to a variety of back-ends, including multiple quantum simulators and nascent quantum processors, enabling genuine hybrid execution on a single node. To illustrate its practicality, we partition a 4-qubit and 20-qubit circuit into three sub-circuits using quantum circuit cutting via the QCut library. Each sub-circuit is simulated independently by the QIR-EE driver within IRIS, after which a classical post-processing step merges the simulation results to recover the outcome of the original full-circuit computation. This case study demonstrates how finer task granularity can enable the parallel execution and lower the simulation burden per quantum task while preserving overall accuracy, highlighting the feasibility of our hybrid approach.

Miniskar, Narasinga Rao [ORNL] (ORCID:000000018259↗

DOE OSTI2025

DISTRI: Distributed Multi-Facility HPC Simulator (DISTRI) v2.1

DISTRI is an advanced network simulator designed for multi-facility computational infrastructures with agentic behavior. It simulates HPC facilities where computational resources act as autonomous agents, making intelligent decisions about job scheduling, load balancing, and resource allocation. The simulator focuses on developing and testing decentralized algorithms that promote resilience and efficiency in multi-facility environments. Key Features: - Agentic Resource Behavior: Processors and DTNs act as autonomous agents with decision-making capabilities - Pheromone-Based Load Balancing: Decentralized load balancing inspired by ant colony optimization - Dual Topology Support: Mesh (normal operations) and Dumbell (network testing) topologies - Comprehensive TCP Simulation: Realistic TCP implementations with multiple congestion control algorithms - Failure Resilience Testing: Processor failure simulation with automatic job reassignment - Extensive Visualization: Detailed performance analysis and metrics collection - Research-Ready: Designed for algorithm development and benchmarking

Bez, Jean Luca [Lawrence Berkeley National Laborat↗

DOE OSTI2026

AthenaK: A Performance-portable Version of the Athena++ Adaptive Mesh Refinement Framework

We describe AthenaK: a new implementation of the Athena++ block-based adaptive mesh refinement framework using the Kokkos programming model. Finite volume methods for Newtonian, special relativistic, and general relativistic (GR) hydrodynamics and magnetohydrodynamics (MHD), and GR-radiation hydrodynamics and MHD, as well as a module for evolving Lagrangian tracer or charged test particles (e.g., cosmic rays) are implemented using the framework. In two companion papers, we describe (1) a new solver for the Einstein equations based on the Z4c formalism, and (2) a GRMHD solver in dynamical spacetimes also implemented using the framework, enabling new applications in numerical relativity. By adopting Kokkos, the code can be run on virtually any hardware, including CPUs, GPUs from multiple vendors, and emerging Advanced RISC Machine processors. AthenaK shows excellent performance and weak scaling, achieving over 1 billion cell updates per second for hydrodynamics in three dimensions on a single NVIDIA Grace Hopper processor. It does this with a typical parallel efficiency of 80% on 65,536 AMD GPUs on the OLCF Frontier system. Such performance portability enables AthenaK to leverage modern exascale computing systems for challenging applications in astrophysical fluid dynamics, numerical relativity, and multimessenger astrophysics.

79 ASTRONOMY AND ASTROPHYSICS↗

DOE OSTI2022

Compressing micro-operations in scheduler entries in a processor

An electronic device includes a processor having a micro-operation queue, multiple scheduler entries, and scheduler compression logic. When a pair of micro-operations in the micro-operation queue is compressible in accordance with one or more compressibility rules, the scheduler compression logic acquires the pair of micro-operations from the micro-operation queue and stores information from both micro-operations of the pair of micro-operations into different portions in a single scheduler entry. In this way, the scheduler compression logic compresses the pair of micro-operations into the single scheduler entry.

Boyer, Michael W.↗

DOE OSTI2020

Power system model parameter conditioning tool

A power system model parameter conditioning tool including a server control processor in communication with phasor measurement unit monitored data records of multiple disturbance events, a model calibration unit providing event screening, power system model simulation, and simultaneous tuning of model parameters. The model calibration performing a simulation using default model parameters, the processor comparing the simulation results to the monitored data. If the prediction is within threshold, then terminating conditioning; else performing parameter identifiability analysis to determine differing effects of various model parameters on power system model accuracy, selecting a parameter set causing a degradation in power system model prediction, and updating the default model parameters corresponding to members of the parameter set with values selected to reduce the degradation. A method and a non-transitory computer readable medium are also disclosed.

Baone, Chaitanya Ashok↗

DOE OSTI2018

Sparse Matrix-Matrix Multiplication on Multilevel Memory Architectures: Algorithms and Experiments

Architectures with multiple classes of memory media are becoming a common part of mainstream supercomputer deployments. So called multi-level memories offer differing characteristics for each memory component including variation in bandwidth, latency and capacity. This paper investigates the performance of sparse matrix multiplication kernels on two leading highperformance computing architectures — Intel's Knights Landing processor and NVIDIA's Pascal GPU. We describe a data placement method and a chunking-based algorithm for our kernels that exploits the existence of the multiple memory spaces in each hardware platform. We evaluate the performance of these methods w.r.t. standard algorithms using the auto-caching mechanisms Our results show that standard algorithms that exploit cache reuse performed as well as multi-memory-aware algorithms for architectures such as Ki\iLs where the memory subsystems have similar latencies. However, for architectures such as GPUS where memory subsystems differ significantly in both bandwidth and latency, multi-memory-aware methods are crucial for good performance. In addition, our new approaches permit the user to run problems that require larger capacities than the fastest memory of each compute node without depending on the software-managed cache mechanisms.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2025

Broadband unidirectional visible imaging using wafer-scale nano-fabrication of multi-layer diffractive optical processors

We present a broadband and polarization-insensitive unidirectional imager that operates at the visible part of the spectrum, where image formation occurs in one direction, while in the opposite direction, it is blocked. This approach is enabled by deep learning-driven diffractive optical design with wafer-scale nano-fabrication using high-purity fused silica to ensure optical transparency and thermal stability. Our design achieves unidirectional imaging across three visible wavelengths (covering red, green, and blue parts of the spectrum), and we experimentally validated this broadband unidirectional imager by creating high-fidelity images in the forward direction and generating weak, distorted output patterns in the backward direction, in alignment with our numerical simulations. This work demonstrates wafer-scale production of diffractive optical processors, featuring 16 levels of nanoscale phase features distributed across two axially aligned diffractive layers for visible unidirectional imaging. This approach facilitates mass-scale production of ~0.5 billion nanoscale phase features per wafer, supporting high-throughput manufacturing of hundreds to thousands of multi-layer diffractive processors suitable for large apertures and parallel processing of multiple tasks. Beyond broadband unidirectional imaging in the visible spectrum, this study establishes a pathway for artificial-intelligence-enabled diffractive optics with versatile applications, signaling a new era in optical device functionality with industrial-level, massively scalable fabrication.

36 MATERIALS SCIENCE↗

DOE OSTI2023

Integration of Ag-CBRAM crossbars and Mott ReLU neurons for efficient implementation of deep neural networks in hardware

In-memory computing with emerging non-volatile memory devices (eNVMs) has shown promising results in accelerating matrix-vector multiplications. However, activation function calculations are still being implemented with general processors or large and complex neuron peripheral circuits. Here, we present the integration of Ag-based conductive bridge random access memory (Ag-CBRAM) crossbar arrays with Mott rectified linear unit (ReLU) activation neurons for scalable, energy and area-efficient hardware (HW) implementation of deep neural networks. We develop Ag-CBRAM devices that can achieve a high ON/OFF ratio and multi-level programmability. Compact and energy-efficient Mott ReLU neuron devices implementing ReLU activation function are directly connected to the columns of Ag-CBRAM crossbars to compute the output from the weighted sum current. We implement convolution filters and activations for VGG-16 using our integrated HW and demonstrate the successful generation of feature maps for CIFAR-10 images in HW. Our approach paves a new way toward building a highly compact and energy-efficient eNVMs-based in-memory computing system.

Mott insulators↗

DOE OSTI2018

End-System Aware Peak Link Utilization Transport for Big Data Transfer over Dedicated Connections

High-performance networks provisioning 10/40-Gbps dedicated channels have been rapidly developed andincreasingly deployed to support big data transfers on the order of terabytes or petabytes in large-scale network-intensiveapplications. However, end users have not seen corresponding increase in application throughput mainly because traditional end-to-end transport methods are not optimized for such connections. New congestion or flow control mechanisms are desirable to meet the challenges brought to transport protocol design by dedicated connections. The advent and proliferation of multi-core processors make it now possible to improve application throughput by providing multiple processing and network resources to a single data transfer. Based on the existing PLUT method, we proposed a new dynamic buffer management scheme and an automatic parallelism tuning mechanism to achieve the maximal bottleneck rate. The performance superiority of PLUT is justified by the experimental results collected over a local 10Gbps dedicated connection.

Rao, Nageswara↗

DOE OSTI2023

Sparse matrix‐vector and matrix‐multivector products for the truncated SVD on graphics processors

Summary Many practical algorithms for numerical rank computations implement an iterative procedure that involves repeated multiplications of a vector, or a collection of vectors, with both a sparse matrix and its transpose. Unfortunately, the realization of these sparse products on current high performance libraries often deliver much lower arithmetic throughput when the matrix involved in the product is transposed. In this work, we propose a hybrid sparse matrix layout, named CSRC, that combines the flexibility of some well‐known sparse formats to offer a number of appealing properties: (1) CSRC can be obtained at low cost from the popular CSR (compressed sparse row) format; (2) CSRC has similar storage requirements as CSR; and especially, (3) the implementation of the sparse product kernels delivers high performance for both the direct product and its transposed variant on modern graphics accelerators thanks to a significant reduction of atomic operations compared to a conventional implementation based on CSR. This solution thus renders considerably higher performance when integrated into an iterative algorithm for the truncated singular value decomposition (SVD), such as the randomized SVD or, as demonstrated in the experimental results, the block Golub–Kahan–Lanczos algorithm.

Aliaga, José I.↗