The NASA Electronic Parts and Packaging (NEPP) Program: Overview and Update FY15 and Beyond
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Parts Assurance↗
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The NASA Electronic Parts and Packaging (NEPP) Program: Overview and Roadmap for FY16
This presentation provides an overview of the NEPP Program as well as the current roadmap for NEPP tasks.
NASA Electronic Parts and Packaging (NEPP) Program↗
The NASA Electronic Parts and Packaging (NEPP) Program: Overview and Roadmap for FY16
This presentation provides an overview of the NEPP Program as well as the current roadmap for NEPP tasks.
Technology Evaluation↗
The NASA Electronic Parts and Packaging (NEPP) Program: An Overview
This presentation provides an overview of the NEPP Program. The NEPP Mission is to provide guidance to NASA for the selection and application of microelectronics technologies; Improve understanding of the risks related to the use of these technologies in the space environment; Ensure that appropriate research is performed to meet NASA mission assurance needs. NEPP's Goals are to provide customers with appropriate and cost-effective risk knowledge to aid in: Selection and application of microelectronics technologies; Improved understanding of risks related to the use of these technologies in the space environment; Appropriate evaluations to meet NASA mission assurance needs; Guidelines for test and application of parts technologies in space; Assurance infrastructure and support for technologies in use by NASA space systems.
NASA Electronic Parts and Packaging (NEPP) Program↗
The NASA Electronic Parts and Packaging (NEPP) Program: An Overview
This presentation provides an overview of the NEPP Program. The NEPP Mission is to provide guidance to NASA for the selection and application of microelectronics technologies; Improve understanding of the risks related to the use of these technologies in the space environment; Ensure that appropriate research is performed to meet NASA mission assurance needs. NEPP's Goals are to provide customers with appropriate and cost-effective risk knowledge to aid in: Selection and application of microelectronics technologies; Improved understanding of risks related to the use of these technologies in the space environment; Appropriate evaluations to meet NASA mission assurance needs; Guidelines for test and application of parts technologies in space; Assurance infrastructure and support for technologies in use by NASA space systems.
Technology Evaluation↗
NASA Electronic Parts and Packaging (NEPP) Program - Radiation Activities
The NEPP mission is to provide guidance to NASA for the selection and application of microelectronics technologies, to improve understanding of the risks related to the use of these technologies in the space environment and to ensure that appropriate research is performed to meet NASA mission assurance needs.
LaBel, Kenneth A.↗
The NASA Electronic Parts and Packaging (NEPP) Program: An Overview
This presentation provides an overview of the NEPP Program. The NEPP Mission is to provide guidance to NASA for the selection and application of microelectronics technologies; Improve understanding of the risks related to the use of these technologies in the space environment; Ensure that appropriate research is performed to meet NASA mission assurance needs. NEPP's Goals are to provide customers with appropriate and cost-effective risk knowledge to aid in: Selection and application of microelectronics technologies; Improved understanding of risks related to the use of these technologies in the space environment; Appropriate evaluations to meet NASA mission assurance needs; Guidelines for test and application of parts technologies in space; Assurance infrastructure and support for technologies in use by NASA space systems.
parts assurance↗
Introduction and NASA Electronic Parts and Packaging (NEPP) Program Overview
This presentation includes an introduction to the space radiation environment, the effects on electronics, the environment in action, flight projects, mission needs, and radiation hardness assurance (RHA).
Technology Evaluation↗
The NASA Electronic Parts and Packaging (NEPP) Program: Overview and the New Tenets for Cost Conscious Mission Assurance on Electrical, Electronic, and Electromechanical (EEE) Parts
The NEPP Program focuses on the reliability aspects of electronic devices (integrated circuits such as a processor in a computer). There are three principal aspects of this reliability: 1) Lifetime, inherent failure and design issues related to the EEE parts technology and packaging; 2) Effects of space radiation and the space environment on these technologies, and; 3) Creation and maintenance of the assurance support infrastructure required for mission success. The NEPP mission is to provide guidance to NASA for the selection and application of microelectronics technologies, to improve understanding of the risks related to the use of these technologies in the space environment, and to ensure that appropriate EEE parts research is performed to meet NASA mission assurance needs. NEPPs FY15 goals are to represent the NASA voice to the greater aerospace EEE parts community including supporting anti-counterfeit and trust, provide relevant guidance to cost-effective missions, aid insertion of advanced (and commercial) technologies, resolve unexpected parts issues, ensure access to appropriate radiation test facilities, and collaborate as widely as possible with external entities. In accordance with the changing mission profiles throughout NASA, the NEPP Program has developed a balanced portfolio of efforts to provide agency-wide assurance for not only traditional spacecraft developments, but also those in-line with the new philosophies emerging worldwide. In this presentation, we shall present an overview of this program and considerations for EEE parts assurance as applied to cost conscious missions.
space radiation↗
Investigation of the Semicoa SCF9550 and the International Rectifier IRHM57260SE for Single-Event Gate Rapture and Single-Event Burnout : NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Assurance
Single-event-effect test results for hi-rel total-dose-hardened power MOSFETs are presented in this report. TheSCF9550 from Semicoa and the IRHM57260SE from International Rectifier were tested to NASA test condition/standards and requirements.The IRHM57260SE performed much better when compared to previous testing. These initial results confirm that parts from the Temecula line are marginally comparable to the El Segundo line. The SCF9550 from Semicoa was also tested and represents the initial parts offering from this vendor. Both parts experienced single-event gate rupture (SEGR) and single-event burnout (SEB). All of the SEGR was from gate to drain.
Single Event Gate Rupture↗
NASA Electronic Parts and Packaging (NEPP) Program Status and Technology Investments Overview
The presentation provides an updated, high-level overview of the NEPP Program. The latest organizational chart is presented that shows the names of the Program and Assistant Program Managers. Additionally, the recent work that is on-going with the updating of several NASA NPDs, NPRs and technical standards is reviewed. Internal and external organizational interfaces are described. Finally, the current technology focus areas are described. These areas include passives, wide-band gap power devices, processor units (CPUs and GPUs), 2.5D and 3D device architectures, memories, and data analytics.
NEPAG↗
NASA Electronic Parts and Packaging (NEPP) Program
Recent Findings from Audits, New Technology Data Reviews a) Disabled Chip Burn-ins A recent audit for a QML device discovered that the chip was disabled during the static burn-in, thus it was not drawing any current. Recommendation: For new SMDs add a statement within the burn-in paragraphs stating that the parts shall be kept in their enabled state during the burn-in. b) Class Q 160-hr/125oC Burn-in This is being interpreted as a static burn-in (even for CMOS technology). Recommendation: Provide clarification in MIL-STD-883, Test Method 5004. c) At Frequency (Dynamic) Burn-ins Test equipment limitation is being cited for not doing burn-ins at the application frequency. Recommendation: The burn-in task group to discuss and provide guidance. When the SMD says that the part can be used at 200 MHz, then doing burn-in at 6 MHz (cited as burn-in equipment limitation frequency) is not going to be meaningful! d) Two Static Burn-ins Some manufacturers are doing electrical testing between the two static burn-ins, whereas others do electricals after completing both static burn-ins. Recommendation: Provide clarification in MIL-STD-883, Test Method 5004. e) Thermal Imaging For a device with hot spots, the thermal resistance, junction-to-case, would be much higher than the guidelines given in MIL-STD-1835. One of the suppliers used thermal imaging to find hot spots on the die. Recommendation: Assign a task group to evaluate the effectiveness of thermal imaging at the product development stage.
Class Y↗
The NASA Electronic Parts and Packaging (NEPP) Program
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Electronic Parts↗
SiC vs. Si for High Radiation Environments: NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Assurance
Commercial silicon carbide and silicon Schottky barrier power diodes have been subjected to 203 MeV proton irradiation and the effects of the resultant displacement damage on the I-V characteristics have been observed. Changes in forward bias I-V characteristics are reported for fluences up to 4 x 10(exp 14) p/cm2. For devices of both material types, the series resistance is observed to increase as the fluence increases. The changes in series resistance result from changes in the free carrier concentration due to carrier removal by the defects produced. A simple model is presented that allows calculation of the series resistance of the device and then relates the carrier removal rate to the changes in series resistance. Using this model to calculate the carrier removal rate in both materials reveals that the carrier removal rate in silicon is less than that in silicon carbide, indicating that silicon is the more radiation tolerant material.
Schottky barrier power diodes↗
Evaluation of Small Form Factor Fiber Optic Interconnects for the NASA Electronics Parts and Packaging Program (NEPP)
The Diamond AVIM optical fiber connector has been used for over a decade in flight environments. AVIM which stands for Aviation Intermediate Maintenance is always referenced as a fiber optic connector type from the DIN (Deutsches Institut fur Normung) family of optical fiber connectors. The newly available Mini AVIM and DMI (Definition Multimedia Interface) connectors also by Diamond provide similar features as the high performance AVIM with the added benefits of being small form factor for board mount and internal box use where long connectors and strain relief can not be accommodated. Transceiver, fiber laser technology and receiver optic technology based on small sized constraints will benefit the most by the reduction in connector form factor. It is for this reason that the Mini AVIM is being evaluated for multimode and single mode optical fiber use in both fiber based and cable based packaging configurations. In a fiber based termination, there are no cable materials to bond to the connector. The only bonding that is conducted is the mounting of the fiber with epoxy to the connector ferrules (which are called DMI ferrules). In a cable configuration, the compatibility of the connector subcomponents along with the upjacketing materials of the cable around the fiber needs to be considered carefully for termination fabrication. Cabled terminations will show greater insertion loss and high probability of failures during thermal cycling testing. This is due to the stressing of the combination of materials that each have different Coefficients of Thermal Expansion (CTE's) and that are bonded together to the connector subcomponents. As the materials flex during thermal excursions, forces are applied to the termination and can make the system fail if the grouping of materials (per their CTE's) are not compatible and this includes cable materials, epoxies, ferrule and connector body components. For this evaluation, multimode 100 micron core step index fiber was used for the fiber terminated condition, and single mode SMF-28 upjacketed with W.L. Gore Flexlite was used for the cabled configuration. For background purposes, a comparison is presented here for information purposes between the high performance AVIM connector features and the Mini AVIM small form factor connectors. Basic connector features are described here.
Ott, Melanie↗
Capacitor Test, Evaluation. and Modeling Within NASA Electronic Parts and Packaging (NEPP) Program. "Why Ceramic Capacitors Fracture During Manual Soldering and How to Avoid Failures"
Presentation discusses: (1) Why Multi-Layer Ceramic Capacitors(MLCCs) crack during manual soldering? Workmanship and parts issues. (2) Do existing qualification requirements assure crack-free soldering? MIL-spec Thermal Shock (TS) testing. MIL-spec Resistance to Soldering Heat (RSH) test. (3) What test can assure reliable soldering? Mechanical characteristics of ceramics. Comparison of three TS techniques: LND, TSD, and IWT. (4) Simulation of TS conditions.
Teverovsky, Alexander↗
Users Guide on Scaled CMOS Reliability: NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Assurance
Reliability of advanced CMOS technology is a complex problem that is usually addressed from the standpoint of specific failure mechanisms rather than overall reliability of a finished microcircuit. A detailed treatment of CMOS reliability in scaled devices can be found in Ref. 1; it should be consulted for a more thorough discussion. The present document provides a more concise treatment of the scaled CMOS reliability problem, emphasizing differences in the recommended approach for these advanced devices compared to that of less aggressively scaled devices. It includes specific recommendations that can be used by flight projects that use advanced CMOS. The primary emphasis is on conventional memories, microprocessors, and related devices.
Scaled CMOS↗
Single-Event Effect (SEE) Survey of Advanced Reconfigurable Field Programmable Gate Arrays: NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Assurance
The NEPP Reconfigurable Field-Programmable Gate Array (FPGA) task has been charged to evaluate reconfigurable FPGA technologies for use in space. Under this task, the Xilinx single-event-immune, reconfigurable FPGA (SIRF) XQR5VFX130 device was evaluated for SEE. Additionally, the Altera Stratix-IV and SiliconBlue iCE65 were screened for single-event latchup (SEL).
Xilinx Single-Event Effects (SEE) Test Consortium↗