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Results for “Neural Circuits”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
NASA NTRS1991

Ferroelectric Memory Capacitors For Neural Networks

Thin-film ferroelectric capacitors proposed as nonvolatile analog memory devices. Intended primarily for use as synaptic connections in electronic neural networks. Connection strengths (synaptic weights) stored as nonlinear remanent polarizations of ferroelectric films. Ferroelectric memory and interrogation capacitors combined into memory devices in vertical or lateral configurations. Photoconductive layer modulated by light provides variable resistance to alter bias signal applied to memory capacitor. Features include nondestructive readout, simplicity, and resistance to ionizing radiation. Interrogated without destroying stored analog data. Also amenable to very-large-scale integration. Allows use of ac coupling, eliminating errors caused by dc offsets in amplifier circuits of neural networks.

Thakoor, Sarita↗
DOE OSTI2024

Evolution of connectivity architecture in the Drosophila mushroom body

Brain evolution has primarily been studied at the macroscopic level by comparing the relative size of homologous brain centers between species. How neuronal circuits change at the cellular level over evolutionary time remains largely unanswered. Here, using a phylogenetically informed framework, we compare the olfactory circuits of three closely related Drosophila species that differ in their chemical ecology: the generalists Drosophila melanogaster and Drosophila simulans and Drosophila sechellia that specializes on ripe noni fruit. We examine a central part of the olfactory circuit that, to our knowledge, has not been investigated in these species—the connections between projection neurons and the Kenyon cells of the mushroom body—and identify species-specific connectivity patterns. We found that neurons encoding food odors connect more frequently with Kenyon cells, giving rise to species-specific biases in connectivity. These species-specific connectivity differences reflect two distinct neuronal phenotypes: in the number of projection neurons or in the number of presynaptic boutons formed by individual projection neurons. Finally, behavioral analyses suggest that such increased connectivity enhances learning performance in an associative task. Our study shows how fine-grained aspects of connectivity architecture in an associative brain center can change during evolution to reflect the chemical ecology of a species.

59 BASIC BIOLOGICAL SCIENCES↗
NASA NTRS1990

Porous-Floating-Gate Field-Effect Transistor

Porous-floating-gate, "vertical" field-effect transistor proposed as programmable analog memory device especially suitable for use in electronic neural networks. Analog value of electrical conductance of device represents synaptic weight (strength of synaptic connection) repeatedly modified by application of suitable writing or erasing voltage. Suited for hardware implementations of massively parallel neural-network architectures for two important reasons: vertical transistor structure requires only two external electrodes, and use of tailored amorphous semiconductors provides choice of very wide range of low conductivity values, dictated by overall power dissipation requirements in massively parallel neural-network circuits.

Thakoor, Anilkumar P.↗
NASA NTRS2003

Artificial Neural Network with Hardware Training and Hardware Refresh

A neural network circuit is provided having a plurality of circuits capable of charge storage. Also provided is a plurality of circuits each coupled to at least one of the plurality of charge storage circuits and constructed to generate an output in accordance with a neuron transfer function. Each of a plurality of circuits is coupled to one of the plurality of neuron transfer function circuits and constructed to generate a derivative of the output. A weight update circuit updates the charge storage circuits based upon output from the plurality of transfer function circuits and output from the plurality of derivative circuits. In preferred embodiments, separate training and validation networks share the same set of charge storage circuits and may operate concurrently. The validation network has a separate transfer function circuits each being coupled to the charge storage circuits so as to replicate the training network s coupling of the plurality of charge storage to the plurality of transfer function circuits. The plurality of transfer function circuits may be constructed each having a transconductance amplifier providing differential currents combined to provide an output in accordance with a transfer function. The derivative circuits may have a circuit constructed to generate a biased differential currents combined so as to provide the derivative of the transfer function.

Tuan A Duong↗
DOE OSTI2024

When in-memory computing meets spiking neural networks—A perspective on device-circuit-system-and-algorithm co-design

This review explores the intersection of bio-plausible artificial intelligence in the form of spiking neural networks (SNNs) with the analog in-memory computing (IMC) domain, highlighting their collective potential for low-power edge computing environments. Through detailed investigation at the device, circuit, and system levels, we highlight the pivotal synergies between SNNs and IMC architectures. Additionally, we emphasize the critical need for comprehensive system-level analyses, considering the inter-dependencies among algorithms, devices, circuit, and system parameters, crucial for optimal performance. An in-depth analysis leads to the identification of key system-level bottlenecks arising from device limitations, which can be addressed using SNN-specific algorithm–hardware co-design techniques. This review underscores the imperative for holistic device to system design-space co-exploration, highlighting the critical aspects of hardware and algorithm research endeavors for low-power neuromorphic solutions.

Physics↗
NASA NTRS1992

GaAs Optoelectronic Integrated-Circuit Neurons

Monolithic GaAs optoelectronic integrated circuits developed for use as artificial neurons. Neural-network computer contains planar arrays of optoelectronic neurons, and variable synaptic connections between neurons effected by diffraction of light from volume hologram in photorefractive material. Basic principles of neural-network computers explained more fully in "Optoelectronic Integrated Circuits For Neural Networks" (NPO-17652). In present circuits, devices replaced by metal/semiconductor field effect transistors (MESFET's), which consume less power.

Lin, Steven H.↗
NASA NTRS1988

Electronic Neural-Network Simulator

Experimental circuits faster than simulation programs run on digital computers. Serial shift register routes clock pulses C1 to neurons in sequence. Clock pulses C2 interrogate neurons. Neuron interconnection information stored in simulated synapses. Can be expanded to greater complexity.

Moopenn, Alex W.↗
NASA NTRS1995

Remote Neural Pendants In A Welding-Control System

Neural network integrated circuits enhance functionalities of both remote terminals (called "pendants") and communication links, without necessitating installation of additional wires in links. Makes possible to incorporate many features into pendant, including real-time display of critical welding parameters and other process information, capability for communication between technician at pendant and host computer or technician elsewhere in system, and switches and potentiometers through which technician at pendant exerts remote control over such critical aspects of welding process as current, voltage, rate of travel, flow of gas, starting, and stopping. Other potential manufacturing applications include control of spray coating and of curing of composite materials. Potential nonmanufacturing uses include remote control of heating, air conditioning, and lighting in electrically noisy and otherwise hostile environments.

Venable, Richard A.↗
NASA NTRS2003

Cascade Back-Propagation Learning in Neural Networks

The cascade back-propagation (CBP) algorithm is the basis of a conceptual design for accelerating learning in artificial neural networks. The neural networks would be implemented as analog very-large-scale integrated (VLSI) circuits, and circuits to implement the CBP algorithm would be fabricated on the same VLSI circuit chips with the neural networks. Heretofore, artificial neural networks have learned slowly because it has been necessary to train them via software, for lack of a good on-chip learning technique. The CBP algorithm is an on-chip technique that provides for continuous learning in real time. Artificial neural networks are trained by example: A network is presented with training inputs for which the correct outputs are known, and the algorithm strives to adjust the weights of synaptic connections in the network to make the actual outputs approach the correct outputs. The input data are generally divided into three parts. Two of the parts, called the "training" and "cross-validation" sets, respectively, must be such that the corresponding input/output pairs are known. During training, the cross-validation set enables verification of the status of the input-to-output transformation learned by the network to avoid over-learning. The third part of the data, termed the "test" set, consists of the inputs that are required to be transformed into outputs; this set may or may not include the training set and/or the cross-validation set. Proposed neural-network circuitry for on-chip learning would be divided into two distinct networks; one for training and one for validation. Both networks would share the same synaptic weights.

Duong, Tuan A.↗
NASA NTRS1991

High-Gain AlxGa1-xAs/GaAs Transistors For Neural Networks

High-gain AlxGa1-xAs/GaAs npn double heterojunction bipolar transistors developed for use as phototransistors in optoelectronic integrated circuits, especially in artificial neural networks. Transistors perform both photodetection and saturating-amplification functions of neurons. Good candidates for such application because structurally compatible with laser diodes and light-emitting diodes, detect light, and provide high current gain needed to compensate for losses in holographic optical elements.

Kim, Jae-Hoon↗
DOE OSTI2024

Formation and retrieval of cell assemblies in a biologically realistic spiking neural network model of area CA3 in the mouse hippocampus

The hippocampal formation is critical for episodic memory, with area Cornu Ammonis 3 (CA3) a necessary substrate for auto-associative pattern completion. Recent theoretical and experimental evidence suggests that the formation and retrieval of cell assemblies enable these functions. Yet, how cell assemblies are formed and retrieved in a full-scale spiking neural network (SNN) of CA3 that incorporates the observed diversity of neurons and connections within this circuit is not well understood. Here, we demonstrate that a data-driven SNN model quantitatively reflecting the neuron type-specific population sizes, intrinsic electrophysiology, connectivity statistics, synaptic signaling, and long-term plasticity of the mouse CA3 is capable of robust auto-association and pattern completion via cell assemblies. Our results show that a broad range of assembly sizes could successfully and systematically retrieve patterns from heavily incomplete or corrupted cues after a limited number of presentations. Furthermore, performance was robust with respect to partial overlap of assemblies through shared cells, substantially enhancing memory capacity. These novel findings provide computational evidence that the specific biological properties of the CA3 circuit produce an effective neural substrate for associative learning in the mammalian brain.

hetero-association↗
NASA NTRS1990

Analog Delta-Back-Propagation Neural-Network Circuitry

Changes in synapse weights due to circuit drifts suppressed. Proposed fully parallel analog version of electronic neural-network processor based on delta-back-propagation algorithm. Processor able to "learn" when provided with suitable combinations of inputs and enforced outputs. Includes programmable resistive memory elements (corresponding to synapses), conductances (synapse weights) adjusted during learning. Buffer amplifiers, summing circuits, and sample-and-hold circuits arranged in layers of electronic neurons in accordance with delta-back-propagation algorithm.

Eberhart, Silvio↗
DOE OSTI2024

A Lie algebraic theory of barren plateaus for deep parameterized quantum circuits

Variational quantum computing schemes train a loss function by sending an initial state through a parametrized quantum circuit, and measuring the expectation value of some operator. Despite their promise, the trainability of these algorithms is hindered by barren plateaus (BPs) induced by the expressiveness of the circuit, the entanglement of the input data, the locality of the observable, or the presence of noise. Up to this point, these sources of BPs have been regarded as independent. In this work, we present a general Lie algebraic theory that provides an exact expression for the variance of the loss function of sufficiently deep parametrized quantum circuits, even in the presence of certain noise models. Our results allow us to understand under one framework all aforementioned sources of BPs. This theoretical leap resolves a standing conjecture about a connection between loss concentration and the dimension of the Lie algebra of the circuit’s generators.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2025

Introduction: Neuromorphic Materials

The explosive growth in data collection and the need to process it efficiently, as well as the desire to automate increasingly complex tasks in transportation, medical care, manufacturing, security and many other fields have motivated a growing interest in neuromorphic computing. Unlike the binary, transistorbased ON/OFF logic gates and separate logic and memory functionalities employed in digital computing, neuromorphic computing is inspired by animal brains that use interconnected synapses and neurons to perform processing, storage and transmission of information at the same location, while only consuming ~20 W or less of power. Motivated by the brain’s efficiency, adaptability, self-learning and resiliency qualities, neuromorphic computing can be broadly defined as an approach to processing and storing information using hardware and algorithms inspired by models of biological neural systems. Present research in neuromorphic computing encompasses approaches that vary significantly in their degree of neuro-inspiration, from systems that only incorporate features such as asynchronous, event-driven operation or use crossbar arrays of non-volatile memory (NVM) elements to accelerate deep neural networks (DNNs), to designs that embrace the extreme parallelism, sparsity, reconfigurability, adaptability, complexity and stochasticity observed in nervous systems. The term ‘neuromorphic’ computing is often credited to Carver Mead, who in the 1980s investigated Si-based analog electronics to replicate functions of the animal retina. Earlier important advances in this field include the work of Frank Rosenblatt, who proposed the concept of the perceptron, Bernard Widrow, who used this concept to build one of the first analog neural networks, the Adaline and many other researchers (see ref. 6 for an historical perspective on neuromorphic computing). With the recent increase in the use of artificial intelligence and large language models, and rising concerns over the associated energy costs, interest in neuromorphic hardware has expanded rapidly. According to some estimates, driven largely by the drastic growth in the training use of artificial intelligence (AI) models using the current computing architectures, the energy cost of computing is projected to reach the energy supply worldwide by 2045. Furthermore, while this is not a realistic outcome, it means that, if more efficient computing technologies are not developed -- soon -- the world will soon become one where demand for energy and market constraints limit the continued increase of societal access to AI and cloud services from data centers. Data centers used for training and use of these models consume hundreds of terawatt hours of electricity, already past 4% of the US electricity demand.

Circuits↗