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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
NASA NTRS1972

A class of all digital phase locked loops - Modelling and analysis.

An all digital phase locked loop which tracks the phase of the incoming signal once per carrier cycle is proposed. The different elements and their functions, and the phase lock operation are explained in detail. The general digital loop operation is governed by a non-linear difference equation from which a suitable model is developed. The lock range for the general model is derived. The performance of the digital loop for phase step, and frequency step inputs for different levels of quantization without loop filter, are studied. The analytical results are checked by simulating the actual system on the digital computer.

Reddy, C. P.↗
NASA NTRS1973

A class of all digital phase locked loops - Modeling and analysis

An all digital phase locked loop which tracks the phase of the incoming signal once per carrier cycle is proposed. The different elements and their functions, and the phase lock operation are explained in detail. The general digital loop operation is governed by a nonlinear difference equation from which a suitable model is developed. The lock range for the general model is derived. The performance of the digital loop for phase step and frequency step inputs for different levels of quantization without loop filter are studied. The analytical results are checked by simulating the actual system on the digital computer.

Reddy, C. P.↗
NASA NTRS1972

Simplified formula for mean cycle-slip time of phase-locked loops with steady-state phase error.

Previous work shows that the mean time from lock to a slipped cycle of a phase-locked loop is given by a certain double integral. Accurate numerical evaluation of this formula for the second-order loop is extremely vexing because the difference between exponentially large quantities is involved. The presented article demonstrates a method in which a much-reduced precision program can be used to obtain the mean first-cycle slip time for a loop of arbitrary degree tracking at a specified SNR and steady-state phase error. It also presents a simple approximate formula that is asymptotically tight at higher loop SNR.

Tausworthe, R. C.↗
NASA NTRS1974

Binary phase locked loops for Omega receivers

An all-digital phase lock loop (PLL) is considered because of a number of problems inherent in an employment of analog PLL. The digital PLL design presented solves these problems. A single loop measures all eight Omega time slots. Memory-aiding leads to the name of this design, the memory-aided phase lock loop (MAPLL). Basic operating principles are discussed and the superiority of MAPLL over the conventional digital phase lock loop with regard to the operational efficiency for Omega applications is demonstrated.

Chamberlin, K.↗
NASA NTRS1988

A digitally implemented phase-locked loop detection scheme for analysis of the phase and power stability of a calibration tone

A digital phase-locked loop (PLL) scheme is described which detects the phase and power of a high SNR calibration tone. The digital PLL is implemented in software directly from the given description. It was used to evaluate the stability of the Goldstone Deep Space Station open loop receivers for Radio Science. Included is a derivative of the Allan variance sensitivity of the PLL imposed by additive white Gaussian noise; a lower limit is placed on the carrier frequency.

Densmore, A. C.↗
NASA NTRS1985

Ensuring fault tolerance of phase-locked clocks

Processors within a real-time multiprocessor system must be synchronized with as little overhead as possible. Although synchronization can be achieved via both software (e.g., interactive convergence and interactive consistency algorithms) and hardware (e.g., multistage synchronizers and phase-locked clocks), phase-locked clocks are most attractive due to their small overheads. Despite the fact that synchronization of the multiprocessor system with phase-locked clocks is totally different in nature from the interactive consistency algorithm, it is presently proven that it must satisfy the same condition, N equal to or greater than 3m + 1, where N is the total number of clocks in the multiprocessor system and m is the maximum number of faults tolerable. Also presented are results showing how to design phase-locked clocks so as to be impervious up to a given arbitrary number of malicious failures.

Krishna, C. M.↗
NASA NTRS1975

Phase-locked loops

An attempt to systematically outline the work done in the area of phase-locked loops which are now used in modern communication system design is presented. The analog phase-locked loops are well documented in several books but discrete, analog-digital, and digital phase-locked loop work is scattered. Apart from discussing the various analysis, design, and application aspects of phase-locked loops, a number of references are given in the bibliography.

Gupta, S. C.↗
NASA NTRS1975

Uniform sampling analysis of a hybrid phase-locked loop with a sample-and-hold phase detector

Phase-locked-loop (PLL) bit synchronizers often employ integrate-and-dump type phase detectors that provide phase error information only at discrete points in time. Usually these phase detectors are followed by sample-and-hold circuits to produce a stairstep error voltage as the input to a standard analog circuit loop filter. When the loop is configured in this manner, it is referred to as a hybrid PLL. Sampled-data analysis methods (Z transforms) are used to determine the stability and transient response of this loop.

Barab, S.↗
NASA NTRS1978

Phase-locked loops and their application

A collection of papers is presented on the characteristics and capabilities of phase-locked loops (PLLs), along with some applications of interest. The discussion covers basic theory (linear and nonlinear); acquisition; threshold; stability; frequency demodulation and detection; tracking; cycle slipping and loss of lock; phase-locked oscillators; operation and performance in the presence of noise; AGC, AFC, and APC circuits and systems; digital PLL; and applications and miscellaneous. With the rapid development of IC technology, PLLs are expected to be used widely in consumer electronics.

Lindsey, W. C.↗
NASA NTRS1991

Digital phase-lock loop

An improved digital phase lock loop incorporates several distinctive features that attain better performance at high loop gain and better phase accuracy. These features include: phase feedback to a number-controlled oscillator in addition to phase rate; analytical tracking of phase (both integer and fractional cycles); an amplitude-insensitive phase extractor; a more accurate method for extracting measured phase; a method for changing loop gain during a track without loss of lock; and a method for avoiding loss of sampled data during computation delay, while maintaining excellent tracking performance. The advantages of using phase and phase-rate feedback are demonstrated by comparing performance with that of rate-only feedback. Extraction of phase by the method of modeling provides accurate phase measurements even when the number-controlled oscillator phase is discontinuously updated.

Thomas, Jr., Jess B.↗
NASA NTRS1978

Phase-locked telemetry system for rotary instrumentation of turbomachinery, phase 1

A telemetry system for use in making strain and temperature measurements on the rotating components of high speed turbomachines employs phase locked transmitters, which offer greater measurement channel capacity and reliability than existing systems which employ L-C carrier oscillators. A prototype transmitter module was tested at 175 C combined with 40,000 g's acceleration.

Adler, A.↗
NASA NTRS1998

Integrated Advanced Microwave Sounding Unit-A (AMSU-A). Performance Verification Report: METSAT Phase Locked Oscillator Assembly, P/N 1334360-1, S/N's F03 and F04

Two Flight Model AMSU-A Phase Locked Oscillators (P/N 1348360-1, S/Ns F03 and F04) have been tested per AES Test Procedure AE-26758. The tests included vibration testing, thermal cycle testing, AM/FM Noise testing, and full functional testing. EMI/REO 2 Testing was not performed. (See test data for S/N F01). Both AMSU-A Phase Locked Oscillators satisfactorily passed all performance requirements of the AE-26633 Product specification. During thermal cycling of PLO serial number F03, the oven and data logger momentarily lost power, including a loss of data. The unit did not experience any thermal stress. TAR 003134 describes the corrective action. Prior to testing PLO serial number FO4, power was applied to the unit. (+15v,-15v) the unit did not display the proper phase lock. Upon test equipment check out a connector was found to be defective. TAR 003133 describes the corrective action. After completion of testing of PLO serial number F04 was installed into Receiver Assembly F02. Upon testing F02 Receiver Assembly the unit was found not to phase lock at ambient temperature. Removal of PLO Assembly F04 was required. R2 was the real issue. Solithane was secondary. Troubleshooting revealed excessive solithane on inner PLL Assembly cover inhibiting optimum grounding. Also, R2 was reselected which increased the lock range from -30 C to +60 C. TAR 002737 describes the corrective action.

Pines, D.↗
NASA NTRS1995

Parallel Digital Phase-Locked Loops

Wide-band microwave receivers of proposed type include digital phase-locked loops in which band-pass filtering and down-conversion of input signals implemented by banks of multirate digital filters operating in parallel. Called "parallel digital phase-locked loops" to distinguish them from other digital phase-locked loops. Systems conceived as cost-effective solution to problem of filtering signals at high sampling rates needed to accommodate wide input frequency bands. Each of M filters process 1/M of spectrum of signal.

Sadr, Ramin↗
NASA NTRS1977

Extrasensitive phase-locked-loop circuit

Modified phase-locked loop (PLL) generates clock from incoming data signal. To minimize effects of threshold phase-detector gain variations, the PLL uses a dither oscillator, a dither band-pass filter, and correlator instead of coherent amplitude detector.

Nyiri, E. J.↗
NASA NTRS1975

Digital phase-locked loop

An digital phase-locked loop is provided for deriving a loop output signal from an accumulator output terminal. A phase detecting exclusive OR gate is fed by the loop digital input and output signals. The output of the phase detector is a bi-level digital signal having a duty cycle indicative of the relative phase of the input and output signals. The accumulator is incremented at a first rate in response to a first output level of the phase detector and at a second rate in response to a second output level of the phase detector.

Cliff, R. A.↗
NASA NTRS1968

Phase-lock loop frequency control and the dropout problem

Technique automatically sets the frequency of narrow band phase-lock loops within automatic lock-in-range. It presets a phase-lock loop to a desired center frequency with a closed loop electronic frequency discriminator and holds the phase-lock loop to that center frequency until lock is achieved.

Attwood, S.↗