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High Field Magnet Programme -- European Strategy Input

In this submission, we describe research goals, implementation, and timelines of the High Field Magnet Programme, hosted by CERN. The programme pursues accelerator-magnet R&D with low-temperature- and high-temperature superconductor technology with a main focus on the FCC-hh. Following a long tradition of magnet R&D for high-energy particle colliders, HFM R&D fosters important societal impact through synergies with other fields.

43 PARTICLE ACCELERATORS

A versatile pulse programmer for pulsed nuclear magnetic resonance spectroscopy.

A digital pulse programmer producing the standard pulse sequences required for pulsed nuclear magnetic resonance spectroscopy is described. In addition, a 'saturation burst' sequence, useful in the measurement of long relaxation times in solids, is provided. Both positive and negative 4 V trigger pulses are produced that are fully synchronous with a crystal-controlled time base, and the pulse programmer may be phase-locked with a maximum pulse jitter of 3 ns to the oscillator of a coherent pulse spectrometer. Medium speed TTL integrated circuits are used throughout.

Tarr, C. E.

Lunar observations verifier editor programmer's manual, revision 1

The prime purpose of the programmer's manual is to aid the programmer in understanding the programming aspects of the program. A description of the input, the printout, the deck setup, and tape configuration may be obtained from the LOVE user's guide.

Barnett, E. L.

A programmable sampling format telemetry system

This paper describes the programmable sampling format telemetry system to be used by the near-earth Small Astronomy Satellite-C (SAS-C) and possible future SAS missions. The concept of the programmable sampling format is introduced and the features of the system are illustrated by an example. The SAS-C telemetry system is described at the block diagram level and redundancy of the system is discussed briefly.

Peterson, M. R.

A programmable power processor for a 25 kW power module

The paper presents the concept and major design problems of a programmable power processor for the 25 kW electrical power system for the Shuttle Orbiter. The load will be handled by three parallel power stages operated in phase sequence with each power transistor having its own commutating diode and filter inductor. The power stages will be run at a fixed frequency of 10 kHz with the 'on'-time variable up to 100%. The input filter bank in the breadboard programmable power processor is planned to be a series-parallel combination of tantalum cased tantalum wet-slug capacitors.

Kapustka, R. E.

Programmable performance - One aspect of smart sensing systems

Programmable performance is the ability to flexibly alter basic spatial, spectral, and radiometric system response as a function of time. In this paper programmable performance is defined as a functional element of smart sensor systems for the 1990's. The uses and benefits of these classes of sensor systems are discussed with reference to multispectral scanners of the earth's surface. An overall technology trend is identified which couples a high degree of sensor performance flexibility to a need for advanced device technology developments.

Jobson, D. J.

An integrated control panel utilizing a programmable varistor-multiplexed dichroic liquid crystal display

Due to the conflicting demands of modern aircraft for increased systems/sensors and the decrease in cockpit panel size, weight, volume, and power, conventional discrete/dedicated methods of display and control are fast becoming obsolete. A means is sought to integrate the control and display into multifunctional programmable devices, thus giving the ability to increase system functions and yet conserve panel space. A potential solution to the control portion of the problem has come to be known as the Integrated Control Panel (ICP) approach. Flat panel display technology and controls using programmable flat panel displays with transparent capacitive touch control overlays offer the largest potential advantages. The flat panel display made of varistor-multiplexed dichroic liquid crystal (LCD) developed by GE in recent years appears to offer the ideal monochrome solution.

Whitton, I. J.

A fast, programmable hardware architecture for spaceborne SAR processing

The launch of spaceborne SARs during the 1980's is discussed. The satellite SARs require high quality and high throughput ground processors. Compression ratios in range and azimuth of greater than 500 and 150 respectively lead to frequency domain processing and data computation rates in excess of 2000 million real operations per second for C-band SARs under consideration. Various hardware architectures are examined and two promising candidates and proceeds to recommend a fast, programmable hardware architecture for spaceborne SAR processing are selected. Modularity and programmability are introduced as desirable attributes for the purpose of HTSP hardware selection.

Bennett, J. R.

A programmable power processor for high power space applications

A Programmable Power Processor (P3) has been developed for application in future large space power systems. The P3 is capable of operation over a wide range of input voltage (26 to 375 Vdc) and output voltage (24 to 180 Vdc). The peak output power capability is 18 kW (180 V at 100 A). The output characteristics of the P3 can be programmed to any voltage and/or current level within the limits of the processor and may be controlled as a function of internal or external parameters. Seven breadboard P3s and one 'flight-type' engineering model P3 have been built and tested both individually and in electrical power systems. The programmable feature allows the P3 to be used in a variety of applications by changing the output characteristics. Test results, including efficiency at various input/output combinations, transient response, and output impedance, are presented.

Lanier, J. R., Jr.

Programmable, secondary frequency standard based infrared synthesizer using tunable lead-salt diode lasers

Quantum phase noise limited Lorentzian power spectral densities were achieved with tunable lead-salt diode lasers. Linewidths as narrow as 22 kHz were observed. A truly programmable infrared synthesizer was produced by frequency-offset-locking the tunable diode lasers to the combination of a stable CO2 (or CO) reference laser and a programmable microwave frequency synthesizer. Absolute frequency accuracy and reproducibility of about + or - 30 kHz (0.000001 kaysers) relative to the primary Cs frequency standard may now be obtained with this technique.

Freed, C.

Planning fuel-conservative descents in an airline environmental using a small programmable calculator: Algorithm development and flight test results

A simple, airborne, flight-management descent algorithm was developed and programmed into a small programmable calculator. The algorithm may be operated in either a time mode or speed mode. The time mode was designed to aid the pilot in planning and executing a fuel-conservative descent to arrive at a metering fix at a time designated by the air traffic control system. The speed model was designed for planning fuel-conservative descents when time is not a consideration. The descent path for both modes was calculated for a constant with considerations given for the descent Mach/airspeed schedule, gross weight, wind, wind gradient, and nonstandard temperature effects. Flight tests, using the algorithm on the programmable calculator, showed that the open-loop guidance could be useful to airline flight crews for planning and executing fuel-conservative descents.

Knox, C. E.

Microcomputer-based programmable optical signal processor

A microcomputer-based real-time programmable optical signal processing system utilizing a magneto-optic spatial light modulator (MOSLM) and a liquid crystal light valve (LCLV) is described. This system can perform a myriad of complicated optical operations, such as image correlation, image subtraction, and matrix multiplication. Its important asserts are its programmability and the capability of real-time addressing. These are important for telerobotic vision in space automation applications. Design specifications and suggestions for practical implementation of the system are discussed. Some preliminary experimental demonstrations are conducted to demonstrate applications of the proposed system to image correlation for optical pattern recognition, image subtraction for lC chip inspection, and matrix multiplication for optical computing.

Yu, F. T. S.

Evaluation of automated decisionmaking methodologies and development of an integrated robotic system simulation. Appendix B: ROBSIM programmer's guide

The purpose of the Robotic Simulation (ROBSIM) program is to provide a broad range of computer capabilities to assist in the design, verification, simulation, and study of robotic systems. ROBSIM is programmed in FORTRAM 77 and implemented on a VAX 11/750 computer using the VMS operating system. The programmer's guide describes the ROBSIM implementation and program logic flow, and the functions and structures of the different subroutines. With the manual and the in-code documentation, an experienced programmer can incorporate additional routines and modify existing ones to add desired capabilities.

Haley, D. C.

Programmable Pulser

User controls number of clock pulses to prevent burnout. New digital programmable pulser circuit in three formats; freely running, counted, and single pulse. Operates at frequencies up to 5 MHz, with no special consideration given to layout of components or to terminations. Pulser based on sequential circuit with four states and binary counter with appropriate decoding logic. Number of programmable pulses increased beyond 127 by addition of another counter and decoding logic. For very large pulse counts and/or very high frequencies, use synchronous counters to avoid errors caused by propagation delays. Invaluable tool for initial verification or diagnosis of digital or digitally controlled circuity.

Baumann, Eric

RT_BUILD: An expert programmer for implementing and simulating Ada real-time control software

The RT BUILD is an expert control system programmer that creates real-time Ada code from block-diagram descriptions of control systems. Since RT BUILD embodies substantial knowledge about the implementation of real-time control systems, it can perform many, if not most of the functions normally performed by human real-time programmers. Though much basic research was done in automatic programming, RT BUILD appears to be the first application of this research to an important problem in flight control system development. In particular, RT BUILD was designed to directly increase productivity and reliability for control implementations of large complex systems.

Lehman, Larry L.

Structural Tailoring of Advanced Turboprops (STAT) programmer's manual

The Structural Tailoring of Advanced Turboprops (STAT) computer program was developed to perform numerical optimizations on highly swept propfan blades. This manual describes the functionality of the STAT system from a programmer's viewpoint. It provides a top-down description of module intent and interaction. The purpose of this manual is to familiarize the programmer with the STAT system should he/she wish to enhance or verify the program's function.

Brown, K. W.

Feedforward, high density, programmable read only neural network based memory system

Neural network-inspired, nonvolatile, programmable associative memory using thin-film technology is demonstrated. The details of the architecture, which uses programmable resistive connection matrices in synaptic arrays and current summing and thresholding amplifiers as neurons, are described. Several synapse configurations for a high-density array of a binary connection matrix are also described. Test circuits are evaluated for operational feasibility and to demonstrate the speed of the read operation. The results are discussed to highlight the potential for a read data rate exceeding 10 megabits/sec.

Daud, Taher

Programmable synaptic chip for electronic neural networks

A binary synaptic matrix chip has been developed for electronic neural networks. The matrix chip contains a programmable 32X32 array of 'long channel' NMOSFET binary connection elements implemented in a 3-micron bulk CMOS process. Since the neurons are kept off-chip, the synaptic chip serves as a 'cascadable' building block for a multi-chip synaptic network as large as 512X512 in size. As an alternative to the programmable NMOSFET (long channel) connection elements, tailored thin film resistors are deposited, in series with FET switches, on some CMOS test chips, to obtain the weak synaptic connections. Although deposition and patterning of the resistors require additional processing steps, they promise substantial savings in silicon area. The performance of synaptic chip in a 32-neuron breadboard system in an associative memory test application is discussed.

Moopenn, A.