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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
NASA NTRS2005

Optimum Integrated Heterodyne Photoreceiver for Coherent Lidar Applications

Many coherent lidar applications, particularly airborne and space-based applications, impose stringent power and size constraints while requiring high levels of sensitivity. For this reason, optimization of the lidar heterodyne photoreceiver is one of the critical steps in ensuring full utilization of limited resources to achieve the required sensitivity. The analysis of 2-micron heterodyne receivers shows that substantial improvement of the order of 3 dB can be obtained by proper optimization of the receiver key control parameters and elimination of its parasitic capacitances by integrating the detector, its bias circuit, and the preamplifier on a single substrate. This paper describes analytical steps for defining optimum heterodyne receiver design parameters and development of experimental devices operating at 2-micron wavelength.

Amzajerdian, Farzin↗
NASA NTRS2002

Silicon base plate with low parasitic electrical interference for sensors

A microgyroscope has a baseplate made of the same material as the rest of the microgyroscope. The baseplate is a silicon baseplate having a heavily p-doped epilayer covered by a thick dielectric film and metal electrodes. The metal electrodes are isolated from the ground plane by the dielectric. This provides very low parasitic capacitive coupling between the electrodes. The thick dielectric reduces the capacitance between the electrodes and the ground plane.

Tang, Tony K.↗
NASA NTRS2009

Differential InP HEMT MMIC Amplifiers Embedded in Waveguides

Monolithic microwave integrated-circuit (MMIC) amplifiers of a type now being developed for operation at frequencies of hundreds of gigahertz contain InP high-electron-mobility transistors (HEMTs) in a differential configuration. The differential configuration makes it possible to obtain gains greater than those of amplifiers having the single-ended configuration. To reduce losses associated with packaging, the MMIC chips are designed integrally with, and embedded in, waveguide packages, with the additional benefit that the packages are compact enough to fit into phased transmitting and/or receiving antenna arrays. Differential configurations (which are inherently balanced) have been used to extend the upper limits of operating frequencies of complementary metal oxide/semiconductor (CMOS) amplifiers to the microwave range but, until now, have not been applied in millimeter- wave amplifier circuits. Baluns have traditionally been used to transform from single-ended to balanced configurations, but baluns tend to be lossy. Instead of baluns, finlines are used to effect this transformation in the present line of development. Finlines have been used extensively to drive millimeter- wave mixers in balanced configurations. In the present extension of the finline balancing concept, finline transitions are integrated onto the affected MMICs (see figure). The differential configuration creates a virtual ground within each pair of InP HEMT gate fingers, eliminating the need for inductive vias to ground. Elimination of these vias greatly reduces parasitic components of current and the associated losses within an amplifier, thereby enabling more nearly complete utilization of the full performance of each transistor. The differential configuration offers the additional benefit of multiplying (relative to the single-ended configuration) the input and output impedances of each transistor by a factor of four, so that it is possible to use large transistors that would otherwise have prohibitively low impedances. Yet another advantage afforded by the virtual ground of the differential configuration is elimination of the need for a ground plane and, hence, elimination of the need for back-side metallization of the MMIC chip. In turn, elimination of the back-side metallization simplifies fabrication, reduces parasitic capacitances, and enables mounting of the MMIC in the electric-field plane ("E-plane") of a waveguide. E-plane mounting is consistent with (and essential for the utility of) the finline configuration, in which transmission lines lie on a dielectric sheet in the middle of a broad side of the waveguide. E-plane mounting offers a combination of low loss and ease of assembly because no millimeter-wave wire bonds or transition substrates are required. Moreover, because there is no ground plane behind the MMIC, the impedance for the detrimental even (single-ended) mode is high, suppressing coupling to that mode. Still another advantage of E-plane mounting is that the fundamental waveguide mode is inherently differential, eliminating the need for a balun to excite the differential mode.

Kangaslahti, Pekka↗
NASA NTRS2006

Single-Chip T/R Module for 1.2 GHz

A single-chip CMOS-based (complementary-metal-oxide-semiconductorbased) transmit/receive (T/R) module is being developed for L-band radar systems. Previous T/R module implementations required multiple chips employing different technologies (GaAs, Si, and others) combined with off-chip transmission lines and discrete components including circulators. The new design eliminates the bulky circulator, significantly reducing the size and mass of the T/R module. Compared to multi-chip designs, the single-chip CMOS can be implemented with lower cost. These innovations enable cost-effective realization of advanced phased array and synthetic aperture radar systems that require integration of thousands of T/R modules. The circulator is a ferromagnetic device that directs the flow of the RF (radio frequency) power during transmission and reception. During transmission, the circulator delivers the transmitted power from the amplifier to the antenna, while preventing it from damaging the sensitive receiver circuitry. During reception, the circulator directs the energy from the antenna to the low-noise amplifier (LNA) while isolating the output of the power amplifier (PA). In principle, a circulator could be replaced by series transistors acting as electronic switches. However, in practice, the integration of conventional series transistors into a T/R chip introduces significant losses and noise. The prototype single-chip T/R module contains integrated transistor switches, but not connected in series; instead, they are connected in a shunt configuration with resonant circuits (see figure). The shunt/resonant circuit topology not only reduces the losses associated with conventional semiconductor switches but also provides beneficial transformation of impedances for the PA and the LNA. It provides full singlepole/ double-throw switching for the antenna, isolating the LNA from the transmitted signal and isolating the PA from the received signal. During reception, the voltage on control line RX/TX (raised bar) is high, causing the field-effect transistor (FET) switch S1 to be closed, forming a parallel resonant tank circuit L1||C1. This circuit presents high impedance to the left of the antenna, so that the received signal is coupled to the LNA. At the same time, FET switches S2 and S3 are open, so that C2 is removed from the circuit (except for a small parasitic capacitance). The combination of L2 and C3 forms a matching network that transforms the antenna impedance of 50 ohms to a higher value from the perspective of the LNA input terminal. This transformation of impedance improves LNA noise figure by increasing the received voltage delivered to the input transistor. This allows lower transconductance and therefore a smaller transistor, which makes it possible to design the CMOS LNA for low power consumption. During transmission, the voltage on control line RX/TX (raised bar) is low, causing switch S1 to be open. In this configuration, the combination of L1 and C1 transforms the antenna impedance to a lower value from the perspective of the PA. This low impedance is helpful in producing a relatively high output power compatible with the low CMOS operating potential. At the same time, switches S2 and S3 are closed, forming the parallel resonant tank circuit L2||C2. This circuit presents high impedance to the right of the antenna, directing the PA output signal to the antenna and away from the LNA. During this time, S3 presents a short circuit across the LNA input terminals to guarantee that the voltage seen by the LNA is small enough to prevent damage.

Moussessian, Alina↗
NASA NTRS2010

Optimal and Local Connectivity Between Neuron and Synapse Array in the Quantum Dot/Silicon Brain

This innovation is used to connect between synapse and neuron arrays using nanowire in quantum dot and metal in CMOS (complementary metal oxide semiconductor) technology to enable the density of a brain-like connection in hardware. The hardware implementation combines three technologies: 1. Quantum dot and nanowire-based compact synaptic cell (50x50 sq nm) with inherently low parasitic capacitance (hence, low dynamic power approx.l0(exp -11) watts/synapse), 2. Neuron and learning circuits implemented in 50-nm CMOS technology, to be integrated with quantum dot and nanowire synapse, and 3. 3D stacking approach to achieve the overall numbers of high density O(10(exp 12)) synapses and O(10(exp 8)) neurons in the overall system. In a 1-sq cm of quantum dot layer sitting on a 50-nm CMOS layer, innovators were able to pack a 10(exp 6)-neuron and 10(exp 10)-synapse array; however, the constraint for the connection scheme is that each neuron will receive a non-identical 10(exp 4)-synapse set, including itself, via its efficacy of the connection. This is not a fully connected system where the 100x100 synapse array only has a 100-input data bus and 100-output data bus. Due to the data bus sharing, it poses a great challenge to have a complete connected system, and its constraint within the quantum dot and silicon wafer layer. For an effective connection scheme, there are three conditions to be met: 1. Local connection. 2. The nanowire should be connected locally, not globally from which it helps to maximize the data flow by sharing the same wire space location. 3. Each synapse can have an alternate summation line if needed (this option is doable based on the simple mask creation). The 10(exp 3)x10(exp 3)-neuron array was partitioned into a 10-block, 10(exp 2)x10(exp 3)-neuron array. This building block can be completely mapped within itself (10,000 synapses to a neuron).

Duong, Tuan A.↗
NASA NTRS2010

Temperature Dependence of Thin Film Spiral Inductors on Alumina Over a Temperature Range of 25 to 475 C

In this paper, we present an analysis of inductors on an Alumina substrate over the temperature range of 25 to 475 C. Five sets of inductors, each set consisting of a 1.5, 2.5, 3.5, and a 4.5 turn inductor with different line width and spacing, were measured on a high temperature probe station from 10 MHz to 30 GHz. From these measured characteristics, it is shown that the inductance is nearly independent of temperature for low frequencies compared to the self resonant frequency, the parasitic capacitances are independent of temperature, and the resistance varies nearly linearly with temperature. These characteristics result in the self resonant frequency decreasing by only a few percent as the temperature is increased from 25 to 475 C, but the maximum quality factor decreases by a factor of 2 to 3. These observations based on measured data are confirmed through 2D simulations using Sonnet software.

Ponchak, George E.↗
NASA NTRS2012

Feedback Augmented Sub-Ranging (FASR) Quantizer

This innovation is intended to reduce the size, power, and complexity of pipeline analog-to-digital converters (ADCs) that require high resolution and speed along with low power. Digitizers are important components in any application where analog signals (such as light, sound, temperature, etc.) need to be digitally processed. The innovation implements amplification of a sampled residual voltage in a switched capacitor amplifier stage that does not depend on charge redistribution. The result is less sensitive to capacitor mismatches that cause gain errors, which are the main limitation of such amplifiers in pipeline ADCs. The residual errors due to mismatch are reduced by at least a factor of 16, which is equivalent to at least 4 bits of improvement. The settling time is also faster because of a higher feedback factor. In traditional switched capacitor residue amplifiers, closed-loop amplification of a sampled and held residue signal is achieved by redistributing sampled charge onto a feedback capacitor around a high-gain transconductance amplifier. The residual charge that was sampled during the acquisition or sampling phase is stored on two or more capacitors, often equal in value or integral multiples of each other. During the hold or amplification phase, all of the charge is redistributed onto one capacitor in the feedback loop of the amplifier to produce an amplified voltage. The key error source is the non-ideal ratios of feedback and input capacitors caused by manufacturing tolerances, called mismatches. The mismatches cause non-ideal closed-loop gain, leading to higher differential non-linearity. Traditional solutions to the mismatch errors are to use larger capacitor values (than dictated by thermal noise requirements) and/or complex calibration schemes, both of which increase the die size and power dissipation. The key features of this innovation are (1) the elimination of the need for charge redistribution to achieve an accurate closed-loop gain of two, (2) a higher feedback factor in the amplifier stage giving a higher closed-loop bandwidth compared to the prior art, and (3) reduced requirement for calibration. The accuracy of the new amplifier is mainly limited by the sampling networks parasitic capacitances, which should be minimized in relation to the sampling capacitors.

Guilligan, Gerard↗
NASA NTRS2014

Passive Resonant Bidirectional Converter with Galvanic Barrier

A passive resonant bidirectional converter system that transports energy across a galvanic barrier includes a converter using at least first and second converter sections, each section including a pair of transfer terminals, a center tapped winding; a chopper circuit interconnected between the center tapped winding and one of the transfer terminals; an inductance feed winding interconnected between the other of the transfer terminals and the center tap and a resonant tank circuit including at least the inductance of the center tap winding and the parasitic capacitance of the chopper circuit for operating the converter section at resonance; the center tapped windings of the first and second converter sections being disposed on a first common winding core and the inductance feed windings of the first and second converter sections being disposed on a second common winding core for automatically synchronizing the resonant oscillation of the first and second converter sections and transferring energy between the converter sections until the voltage across the pairs of transfer terminals achieves the turns ratio of the center tapped windings.

Rosenblad, Nathan S.↗
DOE OSTI2021

MEMS metal-quartz gyroscope

The present disclosure relates to a gyroscope that makes use of a shuttle having a first plurality of fingers, a stator having a second plurality of fingers, at least one fixed support structure, and a plurality of flexors for supporting the shuttle for vibratory motion relative to the stator. The fingers of the shuttle are able to move in a vibratory motion adjacent the fingers of the stator without contacting the fingers of the stator. Portions of the fingers of at least one of the shuttle and the stator also make use of a grounded metal material layer to reduce parasitic capacitive coupling between the fingers of the shuttle and the fingers of the stator.

Park, Sangtae↗
DOE OSTI2024

The Compensating Common-Gate Frontend Circuit Used as Current Source Receiver

A very low power frontend circuit using the compensating common-gate scheme is described. It combines features of the regular common-gate topology and the trans-impedance amplifier (TIA) schemes allowing designers to achieve low input impedance and sufficient bandwidth with small power consumption. It can be used as an interface between detectors and the pseudo-thyristors we developed to complete a full frontend signal chain. Simulation shows that in a 65 nm process, it is possible to achieve an input impedance <1K Ohms allowing a charge detection <6fC with 3pF parasitic capacitance, using static power below 20 micro-Watts/channel.

Fu, T.↗
DOE OSTI2020

Improved Frequency-Domain Steady-State Modeling of the Dual-Active-Bridge Converter Considering Finite ZVS Transition Time Effects

This article presents an improved analytical modeling (IAM) approach for the dual-active-bridge (DAB) converter in the frequency-domain. Specifically, finite transition times are incorporated into the improved modeling that are significant in DAB converters operated at high frequency. The IAM approach is first motivated by comparing traditional frequency-domain modeling against realistic simulation results in LTspice. Next, the IAM approach is mathematically developed in an iterative fashion, where the conventional frequency-domain approach is used as the initialization of the operational behavior of the converter. Subsequent iterations of the IAM algorithm incorporate finite rise- and falltimes of device output capacitances based on detailed switching behavior analyses, which may considerably perturb the desired modulation parameters (i.e., phase shift and zero states). While the initially proposed IAM approach demonstrates advantages over ideal modeling, it is still shown to exhibit errors when applied to device transitions with significant nonlinearity in parasitic output capacitance. To account for this, a three-slope approximation to the switching transition is then motivated and developed, which enables significantly improved steady-state prediction accuracy. Simulation and experimental results confirm unacceptable inaccuracies associated with the conventional frequency-domain modeling across a wide range of operating conditions, alongside enhanced accuracy provided by the proposed modeling approach.

14 SOLAR ENERGY↗
DOE OSTI2026

Tradeoffs in single stage drift step recovery diode generator design

A high-voltage generator of nanosecond pulses utilizing a drift step recovery diode (DSRD) as an opening switch in the compression section is designed to operate at peak voltages of 4 kV and repetition rates of 2 MHz in burst mode at reduced voltages. The generator is used to perform empirical studies on the output metrics of a DSRD generator with a focus on matching the circuit of the reverse current loop parameters and DSRD to the load. The dynamic impedance introduced by nonlinear elements in the DSRD was investigated with respect to the driving circuit by varying the number of DSRDs connected in series. Experimental results indicate that optimization of the driving circuit for the DSRD is key to minimizing losses and achieving optimal pulse compression. Furthermore, the results also indicate trends in DSRD performance as larger storage inductances and longer pumping times are used, limiting the pulse compression capabilities of a single stage DSRD generator.

Electrical properties and parameters↗
DOE OSTI2020

Characterization of an architecture for front-end pixel binning in an integrating pixel array detector

Optimization of an area detector involves compromises between various parameters like frame rate, read noise, dynamic range and pixel size. We have implemented and tested a novel front-end binning design in a photon-integrating hybrid pixel array detector using the MM-PAD- 2.0 pixel architecture. In this architecture, the pixels can be optionally binned in a 2 x 2 pixel configuration using a network of switches to selectively direct the output of 4 sensor pixels to a single amplifier input. Doing this allows a trade-off between frame rate and spatial resolution. Tests show that the binned pixels perform well, but with some degradation on performance as compared to an un-binned pixel. The increased parasitic input capacitance does reduce the signal collected per x-ray as well as increases the noise of the pixel. Here, the increase in noise is, however, less than the factor of 2 increase one would observe for binning in post-processing. Spatial scans across the binned pixels show that no measured signal intensity is lost at the inner binning unit boundaries. In the high flux regime, at a 2 x 2 pixel wide beam spot (FWHM) size, binned mode responds linearly up to a photon flux of 10 7 x-rays/s, and performs comparably with un-binned mode up to a photon flux of 10 8 x-rays/s. While this study demonstrates a proof of concept for front-end binning in integrating detectors, we also identify changes to this early-stage prototype which can further improve the performance of binning pixel structures.

47 OTHER INSTRUMENTATION↗
DOE OSTI2023

Frequency Response Analysis to Monitor and Identify Changes in the Impedance of a Photovoltaic Panel Measured Online using a Power Optimizer

Photovoltaic (PV) cells are generally modeled as a current source due to photocurrent, p-n junction diodes with parasitic resistance, capacitance, and inductance. This paper proposes online frequency response analysis (FRA) to measure the impedance of a PV panel using an existing panel-level power optimizer in a PV system. The algorithm will actively perturb a small signal into a 300 W rooftop PV panel and compute its small signal impedance. The technology discussed is easy to incorporate, requires no additional hardware, doesn't alter the stability of the system, and is implemented at a steady-state point. The power optimizer initially stabilizes at an operating point and then perturbs the PV current via FRA and computes PV panel impedance. The relative standard deviation test conducted indoors under 300 W/m 2 illumination on a PV panel shows a less than 5% error rate in PV panel impedance magnitude and phase is measured using a power optimizer.

14 SOLAR ENERGY↗
NASA NTRS1976

Experimental investigation of a double-diffused MOS structure

Self-aligned polysilicon gate technology was applied to double-diffused MOS (DMOS) construction in a manner that retains processing simplicity and effectively eliminates parasitic overlap capacitance because of the self-aligning feature. Depletion mode load devices with the same dimensions as the DMOS transistors were integrated. The ratioless feature results in smaller dimension load devices, allowing for higher density integration with no increase in the processing complexity of standard MOS technology. A number of inverters connected as ring oscillators were used as a vehicle to test the performance and to verify the anticipated benefits. The propagation time-power dissipation product and process related parameters were measured and evaluated. This report includes (1) details of the process; (2) test data and design details for the DMOS transistor, the load device, the inverter, the ring oscillator, and a shift register with a novel tapered geometry for the output stages; and (3) an analytical treatment of the effect of the distributed silicon gate resistance and capacitance on the speed of DMOS transistors.

Lin, H. C.↗
NASA NTRS1988

Schottky Diode With Surface Channel

Straighforward design changes improve performance and simplify fabrication. Anode contact finger forms bridge over channel material removed to reduce parasitic shunt capacitance. Device made by standard processing techniques readily accommodating changes of design.

Bishop, William↗
NASA NTRS1989

Microwave field effect transistor

Electrodes of a high power, microwave field effect transistor are substantially matched to external input and output networks. The field effect transistor includes a metal ground plane layer, a dielectric layer on the ground plane layer, a gallium arsenide active region on the dielectric layer, and substantially coplanar spaced source, gate, and drain electrodes having active segments covering the active region. The active segment of the gate electrode is located between edges of the active segments of the source and drain electrodes. The gate and drain electrodes include inactive pads remote from the active segments. The pads are connected directly to the input and output networks. The source electrode is connected to the ground plane layer. The space between the electrodes and the geometry of the electrodes extablish parasitic shunt capacitances and series inductances that provide substantial matches between the input network and the gate electrode and between the output network and the drain electrode. Many of the devices are connected in parallel and share a common active region, so that each pair of adjacent devices shares the same source electrodes and each pair of adjacent devices shares the same drain electrodes. The gate electrodes for the parallel devices are formed by a continuous stripe that extends between adjacent devices and is connected at different points to the common gate pad.

Huang, Ho-Chung↗
DOE OSTI2022

A High-Accuracy Power Loss Model of SiC MOSFETs in Current Source Inverter Considering Current Commutation and Parasitic Parameters

Power loss estimation of power electronic devices is important to the efficiency optimization of motor drives used in many applications. However, most existing simplified power loss models of silicon carbide (SiC) MOSFETs are not sufficiently accurate due to their neglect of parasitic parameters in the current commutation loop. In addition, the loss model of the voltage source inverter (VSI) cannot be directly applied to the current source inverter (CSI) because of differences between their commutation loops. First, the commutation processes for VSIs and CSIs are compared. The voltage and current trajectories of SiC MOSFETs in the switching transition of a CSI-based motor drive system are analyzed in detail. Based on these results, the conduction and switching losses of SiC MOSFETs in CSIs are modeled considering the current commutation details. In addition, the proposed analytical model includes parasitic inductances and capacitances in the current commutation loop. Experimental results have verified that the proposed power loss model delivers higher accuracy loss predictions than the conventional loss model.

current commutation, current source inverter, powe↗