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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 55 records · Page 3

LowFive v1.0

LowFive is a new data transport layer based on the HDF5 data model, for in situ workflows. Executables using LowFive can communicate in situ (using in-memory data and MPI message passing), reading and writing traditional HDF5 files to physical storage, and combining the two modes. Minimal and often no source-code modification is needed for programs that already use HDF5. LowFive maintains deep copies or shallow references of datasets, configurable by the user. More than one task can produce (write) data, and more than one task can consume (read) data, accommodating fan-in and fan-out in the workflow task graph. LowFive supports data redistribution from n producer processes to m consumer processes.

Morozov, Dmitriy↗

Evaluating Operators in Deep Neural Networks for Improving Performance Portability of SYCL

SYCL is a portable programming model for heterogeneous computing, so it is important to obtain reasonable performance portability of SYCL. Towards the goal of better understanding and improving performance portability of SYCL for machine learning workloads, we have been developing benchmarks for basic operators in deep neural networks (DNNs). These operators could be offloaded to heterogeneous computing devices such as graphics processing units (GPUs) to speed up computation. In this work, we introduce the benchmarks, evaluate the performance of the operators on GPU-based systems, and describe the causes of the performance gap between the SYCL and Compute Unified Device Architecture (CUDA) kernels. We find that the causes are related to the utilization of the texture cache for read-only data, optimization of the memory accesses with strength reduction, shared local memory accesses, and register usage per thread. We hope that the efforts of developing benchmarks for studying performance portability will stimulate discussion and interactions within the community.

97 MATHEMATICS AND COMPUTING↗

Accelerating shared file checkpoint with local burst buffers

A data management system and method for accelerating shared file checkpointing. Written application data is aggregated in an application data file created in a local burst buffer memory at a compute node, and an associated data mapping built index to maintain information related to the offsets into a shared file at which segments of the application data is to be stored in a parallel file system, and where in the buffer those segments are located. The node asynchronously transfers a data file containing the application data and the associated data mapping index to a file server for shared file storage. The data management system and method further accelerates shared file checkpointing in which a shared file, together with a map file that specifies how the shared file is to be distributed, is asynchronously transferred to local burst buffer memories at the nodes to accelerate reading of the shared file.

Gooding, Thomas↗

First Demonstration of Vertical 2T-nC FeRAM Hybrid Cell and its Scalability for High-Density 3D Ferroelectric Capacitor Memory

In this article, we perform a comprehensive experimental and modeling study into the scaling of vertical 2T-nC ferroelectric random-access memory (FeRAM) hybrid cell to demonstrate a high performance and high-density 3D capacitor memory. We demonstrate: i) first time successful integration of the vertical 2T-3C FeRAM cell by stacking the vertical metal-ferroelectricmetal (MFM) stack on top of Si CMOS transistors; ii) successful experimental operation of the memory cell, including the quasi-nondestructive read out (QNRO) of the polarization without write back after 106 read cycles; iii) the write bit line (WBL) heavily screens the coupling between neighboring strings, making it a minor concern; V ) aggressive stacking of the WBLs, i.e., number of MFMs in a string, could facilitate the self-boosting during write operation due to ferroelectric linear capacitance (CFE), which allows self-boosted inhibition for Vw/2 scheme and worsens the Vw/3 scheme as disturb increases to intolerable 2Vw/3; v) aggressive horizontal scaling significantly increases the read disturb to cells on neighboring planes due to capacitance between two WBLs (Cz).

42 ENGINEERING↗

Algorithms for Efficient Reproducible Floating Point Summation

We define “reproducibility” as getting bitwise identical results from multiple runs of the same program, perhaps with different hardware resources or other changes that should not affect the answer. Many users depend on reproducibility for debugging or correctness. However, dynamic scheduling of parallel computing resources, combined with nonassociative floating point addition, makes reproducibility challenging even for summation, or operations like the BLAS. We describe a “reproducible accumulator” data structure (the “binned number”) and associated algorithms to reproducibly sum binary floating point numbers, independent of summation order. We use a subset of the IEEE Floating Point Standard 754-2008 and bitwise operations on the standard representations in memory. Our approach requires only one read-only pass over the data, and one reduction in parallel, using a 6-word reproducible accumulator (more words can be used for higher accuracy), enabling standard tiling optimization techniques. Summing n words with a 6-word reproducible accumulator requires approximately 9 n floating point operations (arithmetic, comparison, and absolute value) and approximately 3 n bitwise operations. The final error bound with a 6-word reproducible accumulator and our default settings can be up to 2 29 times smaller than the error bound for conventional (recursive) summation on ill-conditioned double-precision inputs.

Computer Science↗

Thrifty Array Format (TAF) file specifications

Thrifty Array Foram (TAF) files store numeric data in a binary format, minimizing storage requirements while preserving quick read access. Real data of any size and dimensionality can be stored in this format at varying degrees of numeric precision. Implicit array are associated with each dimension, eliminating the need to explicitly store uniformly-spaced grid vectors. Unlimited text comments may be included with the array for user documentation, and every file begins with a text synopsis of the binary structure. The format is deliberately designed for memory mapping, where portions of the array can be read without loading the entire file at once.

97 MATHEMATICS AND COMPUTING↗

Impacts to FeRAM design arising from interfacial dielectric layers and wake up modulation in ferroelectric hafnium zirconium oxide

As ferroelectric hafnium zirconium oxide (HZO) becomes more widely utilized in ferroelectric microelectronics, integration impacts of intentional and non-intentional dielectric interfaces and their effects upon the ferroelectric film wake up and circuit parameters become important to understand. In this work, the effect of the addition of a linear dielectric aluminum oxide, Al 2 O 3 , below a ferroelectric Hf 0.58 Zr 0.42 O 2 film in a capacitor structure for FeRAM applications with NbN electrodes was measured. Depolarization fields resulting from the linear dielectric is observed to induce a reduction of the remanent polarization of the ferroelectric. Addition of the aluminum oxide also impacts the wake up of the HZO with respect to the cycling voltage applied. Intricately linked to the design of a FeRAM 1C/1T cell, the metal-ferroelectric-insulator-metal (MFIM) devices are observed to significantly shift charge related to the read states based on aluminum oxide thickness and wake up cycling voltage. As a result, a 33% reduction in the separation of read states is measured, which complicates how a memory cell is designed and illustrates the importance of clean interfaces in devices.

30 DIRECT ENERGY CONVERSION↗

Integrating PGAS and MPI-based Graph Analysis

This project demonstrates that Chapel programs can interface with MPI-based libraries written in C++ without storing multiple copies of shared data. Chapel is a language for productive parallel computing using global address spaces (PGAS). We identified two approaches to interface Chapel code with the MPI-based Grafiki and Trilinos libraries. The first uses a single Chapel executable to call a C function that interacts with the C++ libraries. The second uses the mmap function to allow separate executables to read and write to the same block of memory on a node. We also encapsulated the second approach in Docker/Singularity containers to maximize ease of use. Comparisons of the two approaches using shared and distributed memory installations of Chapel show that both approaches provide similar scalability and performance.

97 MATHEMATICS AND COMPUTING↗

Nonvolatile memory cells from hafnium zirconium oxide ferroelectric tunnel junctions using Nb and NbN electrodes

Ferroelectric tunnel junctions (FTJs) utilizing hafnium zirconium oxide (HZO) have attracted interest as non-volatile memory for microelectronics due to ease of integration into back-end-of-line (BEOL) complementary metal oxide semiconductor fabrication. This work examines asymmetric electrode NbN/HZO/Nb devices with 7 nm thick HZO as FTJs in a memory structure, with an output resistance that can be controlled by read and write voltages. The individual FTJs are measured to have a tunneling electroresistance of 10 during the read state without significant filament conduction formation and reasonable ferroelectric performance. Endurance and remanent polarizations of up to 10 5 cycles and 20 μC/cm 2 , respectively, are measured and are shown to be dependent on the cycling voltage. Electrical measurements demonstrate how magnitude of the write pulse can modulate the high state resistance and the read pulse influences both resistance values as well as separation of resistance states. Then, by using two opposite switching FTJ devices in series, a programmable nonvolatile resistor divider is demonstrated. Measurements of these two FTJ unit memory cells show wide applicability to a BEOL microfabrication process for a re-readable, rewritable, and nonvolatile memory cell.

42 ENGINEERING↗

Reconfigurable quantum phononic circuits via piezo-acoustomechanical interactions

Abstract We show that piezoelectric strain actuation of acoustomechanical interactions can produce large phase velocity changes in an existing quantum phononic platform: aluminum nitride on suspended silicon. Using finite element analysis, we demonstrate a piezo-acoustomechanical phase shifter waveguide capable of producing ± π phase shifts for GHz frequency phonons in 10s of μm with 10s of volts applied. Then, using the phase shifter as a building block, we demonstrate several phononic integrated circuit elements useful for quantum information processing. In particular, we show how to construct programmable multi-mode interferometers for linear phononic processing and a dynamically reconfigurable phononic memory that can switch between an ultra-long-lifetime state and a state strongly coupled to its bus waveguide. From the master equation for the full open quantum system of the reconfigurable phononic memory, we show that it is possible to perform read and write operations with over 90% quantum state transfer fidelity for an exponentially decaying pulse.

Taylor, Jeffrey C. (ORCID:0000000215982436)↗

Implementing Arbitrary/Common Concurrent Writes of CRCW PRAM

The Parallel Random Access Machines (PRAM) abstraction is the simplest and most elegant algorithmic model for the design and analysis of parallel algorithms. It consists of different models categorized based on the underlying memory access mode used, the most powerful of which is the Concurrent Read Concurrent Write (CRCW) model. A PRAM algorithm describes a series of rounds, each of which consists of a collection of operations that can be executed concurrently within the same time step. However, the lack of support for concurrent memory accesses and the prevalence of asynchronous programming models led to the belief that implementing CRCW PRAM algorithms is unattainable and prompted many to avoid this model except for theoretical studies of optimal performance.In this work, we study the arbitrary and common concurrent writes in the CRCW PRAM model and explore implementation challenges on general-purpose systems. Moreover, we examine current practices for implementing common/arbitrary concurrent writes and propose a new efficient lightweight and thread-safe method to implement concurrent writes through leveraging atomic instructions. To demonstrate the efficacy of our method, we developed OpenMP kernels for classical CRCW PRAM algorithms and provide experimental results and comparisons based on run time performance measured over the x86 multicore architecture. Our results show a performance speedup compared to current practices up to 4.5x across all our benchmarks.

Ghanim, Fady↗

Harnessing ferro-valleytricity in pentalayer rhombohedral graphene for memory and compute

Two-dimensional materials with multiple degrees of freedom, including spin, valleys, and orbitals, open up an exciting avenue for engineering multifunctional devices. Beyond spintronics, these degrees of freedom can lead to novel quantum effects such as valley-dependent Hall effects and orbital magnetism, which could revolutionize next-generation electronics. However, achieving independent control over valley polarization and orbital magnetism has been a challenge due to the need for large electric fields. A recent breakthrough involving pentalayer rhombohedral graphene has demonstrated the ability to individually manipulate anomalous Hall signals and orbital magnetic hysteresis, forming what is known as a valley-magnetic quartet. Here, we leverage the electrically tunable ferro-valleytricity of pentalayer rhombohedral graphene to develop nonvolatile memory and in-memory computation applications. We propose an architecture for a dense, scalable, and selector-less nonvolatile memory array that harnesses the electrically tunable ferro-valleytricity. In our designed array architecture, nondestructive read and write operations are conducted by sensing the valley state through two different pairs of terminals, allowing for independent optimization of read/write peripheral circuits. The power consumption of our PRG-based array is remarkably low, with only ∼6 nW required per write operation and ∼2.3 nW per read operation per cell. This consumption is orders of magnitude lower than that of the majority of state-of-the-art cryogenic memories. Additionally, we engineer in-memory computation by implementing majority logic operations within our proposed nonvolatile memory array without modifying the peripheral circuitry. In conclusion, our framework presents a promising pathway toward achieving ultra-dense cryogenic memory and in-memory computation capabilities.

2D materials↗

Enhanced read resolution in reconfigurable memristive synapses for Spiking Neural Networks

Abstract The synapse is a key element circuit in any memristor-based neuromorphic computing system. A memristor is a two-terminal analog memory device. Memristive synapses suffer from various challenges including high voltage, SET or RESET failure, and READ margin issues that can degrade the distinguishability of stored weights. Enhancing READ resolution is very important to improving the reliability of memristive synapses. Usually, the READ resolution is very small for a memristive synapse with a 4-bit data precision. This work considers a step-by-step analysis to enhance the READ current resolution or the read current difference between two resistance levels for a current-controlled memristor-based synapse. An empirical model is used to characterize the $${\hbox {HfO}}_{2}$$ HfO 2 based memristive device. $$1\textrm{st}$$ 1 st and $$2\textrm{nd}$$ 2 nd stage device of our proposed synapse design can be scaled to enhance the READ current margin up to $$\sim$$ ∼ 4.3 $$\times$$ × and $$\sim$$ ∼ 21%, respectively. Moreover, READ current resolution can be enhanced with run-time adaptation techniques such as READ voltage scaling and body biasing. The READ voltage scaling and body biasing can improve the READ current resolution by about 46% and 15%, respectively. TENNLab’s neuromorphic computing framework is leveraged to evaluate the effect of READ current resolution on classification, control, and reservoir computing applications. Higher READ current resolution shows better accuracy than lower resolution even when facing different levels of read noise.

97 MATHEMATICS AND COMPUTING↗

Reducing Memory Consumption in Calico with Shared Memory

This document details the work to reduce memory consumption in Calico. Calico is SimTools’ Constructive Solid Geometry (CSG) and geometry painting library. It is primarily used to paint material volume fractions in the Eulerian meshes of the physics codes. Calico provides point-in-body checks for the geometry supplied by an Oso model, which are then aggregated by the host codes. In addition, Calico can be used to build Oso models and is used by Ingen for that purpose. Oso models, and thus Calico, provide support for various CSG primitives such as spheres, cylinders, surfaces generated by rotating tabular curve data, and STL files as well as binary combinations of those primitives. Prior to refactoring Calico will run out of memory on CTS-1 machines when 36 MPI ranks are used per node when reading STL models on the order of 1.5 GB. This limitation is a bottleneck in designer workflow. This problem has been alleviated through the use of data structures to both reduce memory consumption and to leverage MPI-3 shared memory. This report details the data structures targeted for refactoring in Calico, the methods and implementation details for reducing memory consumption and leveraging shared memory, and results for one test problem. Results show a memory reduction when loading a 1 GB STL file by a factor of 27.5, from 93.4 to 3.4 GB.

97 MATHEMATICS AND COMPUTING↗

Unconventional unidirectional magnetoresistance in heterostructures of a topological semimetal and a ferromagnet

Unidirectional magnetoresistance (UMR) in a bilayer heterostructure, consisting of a spin-source material and a magnetic layer, refers to a change in the longitudinal resistance on the reversal of magnetization and originates from the interaction of non-equilibrium spin accumulation and magnetization at the interface. Since the spin polarization of an electric-field-induced non-equilibrium spin accumulation in conventional spin-source materials is restricted to be in the film plane, the ensuing UMR can only respond to the in-plane component of magnetization. However, magnets with perpendicular magnetic anisotropy are highly desired for magnetic memory and spin-logic devices, whereas the electrical read-out of perpendicular magnetic anisotropy magnets through UMR is critically missing. Here, in this study, we report the discovery of an unconventional UMR in the heterostructures of a topological semimetal (WTe 2 ) and a perpendicular magnetic anisotropy ferromagnetic insulator (Cr 2 Ge 2 Te 6 ), which allows to electrically read the up and down magnetic states of the Cr 2 Ge 2 Te 6 layer through longitudinal resistance measurements.

Kao, I-Hsuan [Carnegie Mellon Univ., Pittsburgh, P↗

Towards Scalable 3D Integration of 2T-nC FeRAM with Hundreds of Layer Stacking

In this article, we study the limits of the number of capacitors and read history dependence in a 2T-nC ferroelectric random-access memory (FeRAM) cell, paving the way for its high-density integration toward hundreds of stacked layers. Through a comprehensive experimental and simulation study on the scaling behavior of the 2T-nC FeRAM architecture, we demonstrate: (i) successful fabrication of 2T-64C cells with robust memory operation and clearly distinguishable ‘0’ and ‘1’ states, even in 64- capacitor configurations; (ii) that the parasitic capacitance of the floating node originates predominantly from the linear component of the ferroelectric capacitor, and its impact on n-scaling—due to degraded sense margin—can be mitigated by floating unselected capacitors with enough TΩ isolation; (iii) that sharing write and read transistors among n capacitors introduces a read history dependence issue due to fluctuating floating node voltage (VFN); and (iv) that a proposed FN discharge scheme can effectively eliminate read-sequence dependence, at the cost of reduced read endurance.

36 MATERIALS SCIENCE↗

Antiferromagnetic memory storage devices from magnetic transition metal dichalcogenides

Switchable antiferromagnetic (AFM) memory devices are provided based on magnetically intercalated transition metal dichalcogenides (TMDs) of the form AxMC2, where A is a magnetic element of stoichiometry x between 0 and 1, M is a transition metal of stoichiometry 1, and C is a chalcogen of stoichiometry 2. Memory storage is achieved by fabricating these materials into crosses of two or more bars and driving DC current pulses along the bars to rotate the AFM order to a fixed angle with respect to the current pulse. Application of current pulses along different bars can switch the AFM order between multiple directions. Standard resistance measurements can detect the orientation of the AFM order as high or low resistance states. The state of the device can be set by the input current pulses, and read-out by the resistance measurement, forming a non-volatile, AFM memory storage bit.

Analytis, James G.↗

Wave Measurements taken NW of Culebra Is., PR, 2023

Wave and sea surface temperature measurements collected by a Sofar Spotter buoy in 2023. The buoy was deployed on July 27, 2023 at 11:30 UTC northwest of Culebra Island, Puerto Rico, (18.3878 N, 65.3899 W) and recovered on Nov 5, 2023 at 12:45 UTC. Data are saved here in netCDF format, organized by month, and include directional wave statistics, GPS, and SST measurements at 30-minute intervals. Figures produced from these data are provided here as well. They include timeseries of wave height/period/direction and SST, GPS location, wave roses, and directional spectra. Additionally, raw CSV files from the Spotter's memory card can also be found below. NetCDF files can be read in python using the netCDF4 or Xarray packages, or through MATLAB using the "ncread()" command.

16 TIDAL AND WAVE POWER↗