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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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All sourcesNASA NTRSDOE OSTI
NASA NTRS1974

Hot ion plasma heating experiments in SUMMA

A new superconducting magnetic mirror apparatus (SUMMA) is described using photographs, diagrams, characteristics graphs, and block diagrams. The apparatus consists of a magnet facility, a plasma test section, the electrode assembly, a charge-exchange neutral particle analyzer, and apparatus for emission spectroscopy. Initial results of hot ion plasma heating experiments conducted in this facility are reported. The purpose of these experiments was twofold: (1) to make a reliable electrode assembly for steady-state operation in the new SUMMA magnetic field configuration and test-section geometry; and (2) to see how ion heating scales as the midplane magnetic field is varied up to 3.5 tesla.

Reinmann, J. J.↗
NASA NTRS2012

Spaceflight Ground Support Equipment Reliability & System Safety Data

Presented were Reliability Analysis, consisting primarily of Failure Modes and Effects Analysis (FMEA), and System Safety Analysis, consisting of Preliminary Hazards Analysis (PHA), performed to ensure that the CoNNeCT (Communications, Navigation, and Networking re- Configurable Testbed) Flight System was safely and reliably operated during its Assembly, Integration and Test (AI&T) phase. A tailored approach to the NASA Ground Support Equipment (GSE) standard, NASA-STD-5005C, involving the application of the appropriate Requirements, S&MA discipline expertise, and a Configuration Management system (to retain a record of the analysis and documentation) were presented. Presented were System Block Diagrams of selected GSE and the corresponding FMEA, as well as the PHAs. Also discussed are the specific examples of the FMEAs and PHAs being used during the AI&T phase to drive modifications to the GSE (via "redlining" of test procedures, and the placement of warning stickers to protect the flight hardware) before being interfaced to the Flight System. These modifications were necessary because failure modes and hazards were identified during the analysis that had not been properly mitigated. Strict Configuration Management was applied to changes (whether due to upgrades or expired calibrations) in the GSE by revisiting the FMEAs and PHAs to reflect the latest System Block Diagrams and Bill Of Material. The CoNNeCT flight system has been successfully assembled, integrated, tested, and shipped to the launch site without incident. This demonstrates that the steps taken to safeguard the flight system when it was interfaced to the various GSE were successful.

Fernandez, Rene↗
NASA NTRS1989

Design of an orbital debris radar ground demonstration

A breadboard radar system is being designed and tested at NASA Johnson for dealing with the space debris problem that could present a growing threat to Space Station Freedom. The major design problems are due to the small radar cross section of such debris (below -30 dBm2), the high closing velocities of the particles with respect to the Space Station (10 km/sec and higher), and the stringent weight, power-consumption, maintenance, and reliability constraints on spaceborne systems. Consideration is given to the preliminary implementation of a ground demonstration radar for testing concepts, technologies, and performance envelopes for application to the space-borne debris detection and tracking radar. Simulation results and techniques developed for predicting system performance and for evaluating antenna parameters are given. The design process of the electronically steered phased array antenna is briefly described, and block diagrams for the implementation of the radar system are given.

Paz, I.↗
NASA NTRS1973

The applicability of frame imaging from a spinning spacecraft. Volume 1: Summary report

A detailed study was made of frame-type imaging systems for use on board a spin stabilized spacecraft for outer planets applications. All types of frame imagers capable of performing this mission were considered, regardless of the current state of the art. Detailed sensor models of these systems were developed at the component level and used in the subsequent analyses. An overall assessment was then made of the various systems based upon results of a worst-case performance analysis, foreseeable technology problems, and the relative reliability and radiation tolerance of the systems. Special attention was directed at restraints imposed by image motion and the limited data transmission and storage capability of the spacecraft. Based upon this overall assessment, the most promising systems were selected and then examined in detail for a specified Jupiter orbiter mission. The relative merits of each selected system were then analyzed, and the system design characteristics were demonstrated using preliminary configurations, block diagrams, and tables of estimated weights, volumes and power consumption.

Botticelli, R. A.↗
NASA NTRS1986

RT_BUILD: An expert programmer for implementing and simulating Ada real-time control software

The RT BUILD is an expert control system programmer that creates real-time Ada code from block-diagram descriptions of control systems. Since RT BUILD embodies substantial knowledge about the implementation of real-time control systems, it can perform many, if not most of the functions normally performed by human real-time programmers. Though much basic research was done in automatic programming, RT BUILD appears to be the first application of this research to an important problem in flight control system development. In particular, RT BUILD was designed to directly increase productivity and reliability for control implementations of large complex systems.

Lehman, Larry L.↗
NASA NTRS1989

Reliable magnetic tape recording for real-time data acquisition systems

The design of a real-time magnetic tape I/O system using automatic error recovery and data spooling is discussed. Real time requirements (data acquired at one rate and recorded at another by queing) must be met and data integrity must be provided regardless of tape failures or I/O errors. Automatic blocking services should be used for multiple local records storage. Avoidance of operational delays and loss of data is essential, noting the problems of the tape drives of the NASA Langley cryogenic wind tunnel. A series of block diagrames and flow charts are included.

Richard W Ross↗
NASA NTRS1981

Geostationary multipurpose platforms

In addition to the advantages generally associated with orbital platforms, such as improved reliability, economies of scale, simple connectivity of elements, reduced tracking demands and the restraint of orbital object population growth, geostationary platforms yield: (1) continuous access by fixed ground antennas for communications services; (2) continuous monitoring of phenomena over chosen regions of the earth's surface; (3) a preferred location for many solar-terrestrial physics experiments. The geostationary platform also offers a low-risk and economical solution to the impending saturation of the orbital arc/frequency spectrum, maximizing the capacity of individual slots and increasing the utility of the entire arc. It also allows the use of many small, simple and inexpensive earth stations through complexity inversion and high power per beam. Block diagram and operational flowcharts are provided.

Bekey, I.↗
NASA NTRS1997

Soft-Decision Decoding of Binary Linear Block Codes Based on an Iterative Search Algorithm

This correspondence presents a suboptimum soft-decision decoding scheme for binary linear block codes based on an iterative search algorithm. The scheme uses an algebraic decoder to iteratively generate a sequence of candidate codewords one at a time using a set of test error patterns that are constructed based on the reliability information of the received symbols. When a candidate codeword is generated, it is tested based on an optimality condition. If it satisfies the optimality condition, then it is the most likely (ML) codeword and the decoding stops. If it fails the optimality test, a search for the ML codeword is conducted in a region which contains the ML codeword. The search region is determined by the current candidate codeword and the reliability of the received symbols. The search is conducted through a purged trellis diagram for the given code using the Viterbi algorithm. If the search fails to find the ML codeword, a new candidate is generated using a new test error pattern, and the optimality test and search are renewed. The process of testing and search continues until either the MEL codeword is found or all the test error patterns are exhausted and the decoding process is terminated. Numerical results show that the proposed decoding scheme achieves either practically optimal performance or a performance only a fraction of a decibel away from the optimal maximum-likelihood decoding with a significant reduction in decoding complexity compared with the Viterbi decoding based on the full trellis diagram of the codes.

Lin, Shu↗
NASA NTRS2004

High-Temperature Probe Station Developed to Characterize Microwave Devices Through 500 C

A photograph and a block diagram of the high-temperature probe station are shown. The system consists of the ceramic heater mounted on a NASA shuttle tile insulator, a direct current power supply, a personal-computer-based data acquisition and temperature controller, microwave probes, a microscope, and a network analyzer. The ability to perform microwave tests at high temperatures is becoming necessary. There is now a need for sensors and communication circuits that can operate at 500 C and above for aircraft engine development and monitoring during flight. To address this need, researchers have fabricated devices using wide bandgap semiconductors such as SiC with targeted operating temperatures of 500 to 600 C. However, the microwave properties of these devices often change drastically with temperature, so any designs that are intended to be used in such an environment must be characterized at high temperatures. For some reliability, lifetime, and direct-current testing, the device under test can be packaged and characterized in an oven. However, for RF and microwave measurements, it is usually not possible to establish a calibrated reference plane at the device terminals within a package. In addition, the characteristics of the package would vary over a 500 C temperature range, and this would have to be accounted for when the data were analyzed. A high temperature probe station allows circuits and devices to be characterized through on wafer measurements across a broad temperature range with known reference plane. The conventional, commercially available thermal wafer-probe stations that are used to evaluate microwave devices across a controlled temperature range have a typical upper limit of 200 C. Standalone thermal heating chucks are available with an extended upper temperature range of 300 to 400 C. To effectively characterize devices at temperatures up to and surpassing 500 C, Glenn researchers developed a custom probe station. In the past, custom probe stations have been developed to test devices under other extreme environments, such as cryogenic temperatures as low as 37 K. Similarly, this custom probe station was specifically modified for high-temperature use. It allows devices to be measured quickly and flexibly, without the use of wire bonds and test fixtures. The probe station is shown making scattering parameter measurements from 1 to 50 GHz with a Hewlett-Packard 8510C Network Analyzer. There is a half-wafer of silicon directly on top of the heater to provide a uniform heated platform for our sample. A quarter wafer of silicon carbide forms the substrate for our test circuit of several transmission lines.

Downey, Alan N.↗
NASA NTRSDate not supplied

The System Complexity Metric (SCM) Predicts System Costs and Failure Rates

A complex system has many parts and interactions and so is difficult to understand. Systems with higher complexity generally have higher costs and failure rates. A System Complexity Metric (SCM) is defined to be the sum of the number of nodes, N, in the system block diagram plus the number of one-way interactions, I, between the nodes. SCM = N + I. SCMs are easily determined by direct inspection of high level block diagrams of life support systems. System cost was found to be directly proportional to SCM. The system MTBF (Mean Time Before Failure) is the inverse of the system failure rate. MTBF = 1/f. The system MTBF was found to be proportional to SCM^(-2.2) for estimated preflight MTBFs. As is typical for systems that are not extensively tested and redesigned to eliminate unexpected failure modes, the life support flight failure rates were about ten times higher than the preflight estimates and the MTBFs one-tenth the preflight estimates. The system MTBF was found to be proportional to SCM^(-2.6) for observed flight MTBFs.

System compleity↗
NASA NTRS1996

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

In his research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second(Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high- speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.

Lin, Shu↗
NASA NTRS1996

High-Speed Soft-Decision Decoding of Two Reed-Muller Codes

In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing, a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study, which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating, and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these sub-trellises.

Lin, Shu↗
NASA NTRS1996

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.

Lin, Shu↗
NASA NTRS1996

High-Speed Soft-Decision Decoding of Two Reed-Muller Codes

In his research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RNI subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a hi ch data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these sub-trellises.

Lin, Shu↗
NASA NTRS2007

Proposed Array-based Deep Space Network for NASA

The current assets of the Deep Space Network (DSN) of the National Aeronautics and Space Administration (NASA), especially the 70-m antennas, are aging and becoming less reliable. Furthermore, they are expensive to operate and difficult to upgrade for operation at Ka-band (321 GHz). Replacing them with comparable monolithic large antennas would be expensive. On the other hand, implementation of similar high-sensitivity assets can be achieved economically using an array-based architecture, where sensitivity is measured by G/T, the ratio of antenna gain to system temperature. An array-based architecture would also provide flexibility in operations and allow for easy addition of more G/T whenever required. Therefore, an array-based plan of the next-generation DSN for NASA has been proposed. The DSN array would provide more flexible downlink capability compared to the current DSN for robust telemetry, tracking and command services to the space missions of NASA and its international partners in a cost effective way. Instead of using the array as an element of the DSN and relying on the existing concept of operation, we explore a broader departure in establishing a more modern concept of operations to reduce the operations costs. This paper presents the array-based architecture for the next generation DSN. It includes system block diagram, operations philosophy, user's view of operations, operations management, and logistics like maintenance philosophy and anomaly analysis and reporting. To develop the various required technologies and understand the logistics of building the array-based lowcost system, a breadboard array of three antennas has been built. This paper briefly describes the breadboard array system and its performance.

telemetry↗
NASA NTRS2007

"Smart" Sensor Module

An assembly that contains a sensor, sensor-signal-conditioning circuitry, a sensor-readout analog-to-digital converter (ADC), data-storage circuitry, and a microprocessor that runs special-purpose software and communicates with one or more external computer(s) has been developed as a prototype of "smart" sensor modules for monitoring the integrity and functionality (the "health") of engineering systems. Although these modules are now being designed specifically for use on rocket-engine test stands, it is anticipated that they could also readily be designed to be incorporated into health-monitoring subsystems of such diverse engineering systems as spacecraft, aircraft, land vehicles, bridges, buildings, power plants, oilrigs, and defense installations. The figure is a simplified block diagram of the "smart" sensor module. The analog sensor readout signal is processed by the ADC, the digital output of which is fed to the microprocessor. By means of a standard RS-232 cable, the microprocessor is connected to a local personal computer (PC), from which software is downloaded into a randomaccess memory in the microprocessor. The local PC is also used to debug the software. Once the software is running, the local PC is disconnected and the module is controlled by, and all output data from the module are collected by, a remote PC via an Ethernet bus. Several smart sensor modules like this one could be connected to the same Ethernet bus and controlled by the single remote PC. The software running in the microprocessor includes driver programs for operation of the sensor, programs that implement self-assessment algorithms, programs that implement protocols for communication with the external computer( s), and programs that implement evolutionary methodologies to enable the module to improve its performance over time. The design of the module and of the health-monitoring system of which it is a part reflects the understanding that the main purpose of a health-monitoring system is to detect damage and, therefore, the health-monitoring system must be able to function effectively in the presence of damage and should be capable of distinguishing between damage to itself and damage to the system being monitored. A major benefit afforded by the self-assessment algorithms is that in the output of the module, the sensor data indicative of the health of the engineering system being monitored are coupled with a confidence factor that quantifies the degree of reliability of the data. Hence, the output includes information on the health of the sensor module itself in addition to information on the health of the engineering system being monitored.

Mahajan, Ajay↗