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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

The future of computing beyond Moore’s Law

Moore’s Law is a techno-economic model that has enabled the information technology industry to double the performance and functionality of digital electronics roughly every 2 years within a fixed cost, power and area. Advances in silicon lithography have enabled this exponential miniaturization of electronics, but, as transistors reach atomic scale and fabrication costs continue to rise, the classical technological driver that has underpinned Moore’s Law for 50 years is failing and is anticipated to flatten by 2025. Here, this article provides an updated view of what a post-exascale system will look like and the challenges ahead, based on our most recent understanding of technology roadmaps. It also discusses the tapering of historical improvements, and how it affects options available to continue scaling of successors to the first exascale machine. Lastly, this article covers the many different opportunities and strategies available to continue computing performance improvements in the absence of historical technology drivers. This article is part of a discussion meeting issue ‘Numerical algorithms for high-performance computational science’.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

Hyperuniform and nearly hyperuniform random network materials

This invention is in the field of physical chemistry and relates to novel hyperuniform and nearly hyperuniform random network materials and methods of making said materials. Methods are described for controlling or altering the band gap of a material, and in particular commercially useful materials such as amorphous silicon. These methods can be exploited in the design of semiconductors, transistors, diodes, solar cells and the like.

36 MATERIALS SCIENCE↗
DOE OSTI2023

A Smart Silicon Carbide Power Module With Pulse Width Modulation Over Wi-Fi and Wireless Power Transfer-Enabled Gate Driver, Featuring Onboard State of Health Estimator and High-Voltage Scaling Capabilities

A wide range of utility applications require controllable switches with features such as high-voltage blocking and high-current carrying capacity, especially at high pulse width modulation (PWM) frequency. Low- and medium-voltage utility applications such as motor drives and flexible AC transmission systems as well as solid state transformers could also benefit from a low-cost high-voltage switching module. Wide-bandgap semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) metal oxide semiconductor field effect transistors (MOSFETs) are considered to be the present and next-generation device choices, although they have limitations. For relatively high-voltage applications with demanding thermal management, SiC is still the only choice, and GaN dominates the low-voltage regime. This manuscript proposes a new half-bridge power MOSFET module that is suitable for conventional H-bridge of multilevel configurations used in high-voltage applications. Constructed from bare SiC dies, this half-bridge module takes advantage of (1) optimized MOSFET placement inside the module, (2) customized heat exchanger, manifold, and cooling, (3) integrated gate driver module with pulse width modulation (PWM) over wi-fi to eliminate the need for low-voltage signals, (4) wireless power transfer (WPT)-enabled gate driver and other ancillary circuits, (5) and the option to incorporate an onboard state-of-health (SOH) estimator module. The entire architecture has been designed and built at the National Renewable Energy Laboratory (NREL) in Golden, CO.

Ga2O3 devices↗
DOE OSTI2025

Gate control of electron correlations towards Mott field effect transistors (MottFET)

The modulation of channel conductance in field-effect transistors (FETs) via metal-insulator-semiconductor structures has revolutionized information processing and storage. However, the limitations of silicon-based FETs in electrical switching have driven the search for new materials capable of overcoming these constraints. Electrostatic gating of competing electronic phases in a Mott material near its metal-to-insulator transition (MIT) offers the prospects of substantial modulation of the conducting electrons and electrical resistivity through small changes in band filling. While electrostatic control of the MIT has been previously reported, the advancement of Mott materials toward novel Mott-based transistors, MottFETs requires the realization of their unique physical properties in a solid-state device. In this study, we present gate control of electron correlation using a solid-state device utilizing the oxide Mott system La 1-x Sr x VO 3 as a correlated FET channel. We report on a gate resistance response that cannot be explained in a purely electrostatic framework. This behavior suggests an enhancement in effective mass and a reduction in effective carrier density as the system approaches its insulating state, consistent with theoretical predictions for Mott systems, suggesting at least 100× charge gain originating from the correlated behavior. These preliminary results pave the way toward the development of highly efficient, low-power electronic devices that could surpass the performance bottlenecks of conventional FETs by leveraging the electronic phase transitions of correlated electron systems.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2025

Aluminum Boron Nitride Ferroelectric Field-Effect Transistors With ZnO Semiconductor Channel

The discovery of ferroelectricity in hafnium zirconium oxide (HfxZr 1−x O2) and related fluorite materials has spurred interest in ferroelectric devices suitable for integration with silicon integrated circuits (ICs), especially those that can be embedded in the back-end-of-line (BEOL) process. More recently, ferroelectricity has been found in wurtzite aluminum nitride-based materials, such as scandium and boron-doped aluminum nitride (Al 1−x ScxN and Al 1−x BxN). Although these materials currently have undesirably large coercive electric fields, and small breakdown electric field-to-coercive electric field ratio, their low processing temperatures and large remanent polarization offer intriguing possibilities for device applications. Furthermore, we report ferroelectric field-effect transistors (FeFETs) with a 15 nm thick Al0.88B0.12N layer and an 11 nm ZnO semiconductor channel, achieving a memory window >1 V and switching voltages ( V switch ) <±10 V.

42 ENGINEERING↗
DOE OSTI2025

Emerging applications: Neuromorphic computing and reservoir computing

The emergence of doped hafnium oxide (HfO 2 )-based ferroelectric films has enabled highly scalable and silicon-compatible ferroelectric devices, opening new frontiers in neuromorphic and reservoir computing. Among these, ferroelectric field-effect transistors (FeFETs) are particularly promising due to their analog memory characteristics and unique polarization dynamics. These properties make FeFETs ideal candidates for artificial synapses in neuromorphic architectures, supporting deep neural networks and spiking neural networks based on leaky-integrate-and-fire (LIF) mechanisms. Beyond neuromorphic computing, FeFETs also play a crucial role in physical reservoir computing, leveraging their intrinsic nonlinear and history-dependent behavior for efficient real-time learning. This approach offers significant advantages for time-series processing and edge artificial intelligence (AI) applications, addressing the growing need for energy-efficient computing. As a result, this article explores the principles, key demonstrations, and future potential of FeFET-based neuromorphic and reservoir computing, highlighting their impact on next-generation AI hardware.

36 MATERIALS SCIENCE↗
DOE OSTI2025

Thermal Optimization and Experimental Demonstration of a Silicon Carbide, Half-Bridge Power Module

This paper describes modeling and experimental work to design and demonstrate a silicon carbide (SiC), single-side-cooled power module. Two SiC metal-oxide-semiconductor field-effect transistors (MOSFET) were used for each switch position and packaged on a metalized ceramic substrate. Thermal modeling was first conducted to optimize the module packaging to minimize junction-to-fluid thermal resistance and device temperature variations. This procedure identified the optimal device placement and baseplate thickness to maximize thermal performance. A heat exchanger - incorporating impinging jets of water-ethylene glycol - was designed to cool the module's baseplate to minimize thermal resistance and pumping power. The heat exchanger used relatively low fluid velocities (<1.5 m/s) to minimize erosion-corrosion effects and relatively large fluid channel sizes (>=1 mm) to prevent clogging. The power module concept was fabricated, and experiments were conducted to measure its thermal performance. Direct current was used to power the module devices, and junction temperatures were measured via device temperature-sensitive parameters. The experimental results were found to be in good agreement with model predictions (within 2%) and yielded junction-to-fluid thermal resistance values as low as about 15 mm2 K/W at relatively low pumping power values. The results demonstrate the improved performance associated with jet impingement cooling and represent an improvement over existing channel-flow-type cold plates, which can enable improvements to power density and reliability.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Lossless Phonon Transition Through GaN‐Diamond and Si‐Diamond Interfaces

Abstract Advancing Silicon (Si) technology beyond Moore's law through 3D architectures requires highly efficient heat management methods compatible with foundry processes. While continued increases in transistor density can be achieved through 3D architectures, self‐heating in the upper tiers degrades the performance. Self‐heating is a critical problem for high‐power, high‐frequency, wide bandgap, and ultra‐wide bandgap devices as well. Diamond, known for its exceptional thermal conductivity, offers a viable solution in both these cases. Since thermal boundary resistance (between the channel/junction and diamond plays a crucial role in overall thermal resistance, this study investigates various dielectrics for interface engineering, such as Silicon dioxide (SiO 2 ), amorphous‐ Silicon Carbide (a‐SiC), and Silicon Nitride (SiN x ), to make a phonon bridge at gallium nitride (GaN)‐diamond and Si‐diamond interfaces. The a‐SiC interlayer reduces diamond/GaN (<5 m 2 K per GW) and diamond/Si (<2 m 2 K per GW) thermal boundary resistances by linking low‐ and high‐frequency phonons, boosting phonon transport through the interface. Engineered interfaces enhance heat spreading from the channel/junction and rule out premature failure.

Malakoutian, Mohamadali↗
DOE OSTI2025

Tunable 3D Aerosol Jet Printing of Low‐Power Redox‐Gated Transistors with Multicomponent Inks

Printed hybrid electronics (PHE) offer a promising alternative for microelectronics fabrication, addressing some limitations of traditional subtractive manufacturing. Despite the versatility of PHE, particularly in the customization of printing inks, these devices have not yet matched the performance of silicon-based electronics due to challenges in gating mechanisms and operational stability. However, the potential of low-voltage redox-gating to achieve significant carrier modulations in correlated metal oxides remains unexplored in PHE. This study systematically investigates vanadium dioxide (VO 2 ) nanoparticles and redox inks, linking their organization in solution to their morphology, phase state, and properties in solid films and multilayered structures. Using an aerosol jet printer (AJP), a solid-state VO 2 transistor is fabricated, operating at just 0.4 V gating voltage. The printed VO 2 films demonstrate redox-modulated conductivity and consistent transistor behavior. The solid-state redox gating materials also provide long-term stability, with the device maintaining performance over 6000 cycles without degradation. These results highlight the potential of redox gating to enhance the application of functional nanoparticles in printed hybrid microelectronics, especially for flexible, low-voltage, and energy-efficient devices.

36 MATERIALS SCIENCE↗
DOE OSTI2025

Probability Density Function for the spatial and intensity distribution of neutron-induced defects in Silicon

The ability to model semiconductor device degradation under neutron irradiation depends upon having a robust modeling capability for the neutron-induced collision cascades as well as a means to analytically fit the resulting probability distributions of defect production and ionizing energy deposition for purposes of extrapolation to low-probability, high-consequence scenarios. In this paper, the widely-utilized binary collision approximation codes MARLOWE and SRIM are deployed in conjunction with a critical examination of their parameterizations as benchmarked against higher-fidelity molecular dynamics simulations. A simple 3-parameter form described by the Generalized Logistic Distribution is shown to be a good fit to Frenkel pair and ionization intensity distributions in bulk silicon. The BCA codes are then applied to simulate cascades in 5 nm layers of a representative gate-all-around nanosheet transistor, where joint probability distributions of threshold levels of damage to multiple layers are evaluated.

36 MATERIALS SCIENCE↗
DOE OSTI2022

Conductivity and size quantization effects in semiconductor $$\delta$$-layer systems

Abstract We present an open-system quantum-mechanical 3D real-space study of the conduction band structure and conductive properties of two semiconductor systems, interesting for their beyond-Moore and quantum computing applications: phosphorus $$\delta$$ δ -layers and P $$\delta$$ δ -layer tunnel junctions in silicon. In order to evaluate size quantization effects on the conductivity, we consider two principal cases: nanoscale finite-width structures, used in transistors, and infinitely-wide structures, electrical properties of which are typically known experimentally. For devices widths $$W<10$$ W < 10 nm, quantization effects are strong and it is shown that the number of propagating modes determines not only the conductivity, but the distinctive spatial distribution of the current-carrying electron states. For $$W>10$$ W > 10 nm, the quantization effects practically vanish and the conductivity tends to the infinitely-wide device values. For tunnel junctions, two distinct conductivity regimes are predicted due to the strong conduction band quantization.

36 MATERIALS SCIENCE↗
DOE OSTI2022

Low temperature CVD growth of WSe 2 enabled by moisture-assisted defects in the precursor powder

Two-dimensional transition metal dichalcogenides (TMDs) have been proposed for a wide variety of applications, such as neuromorphic computing, flexible field effect transistors, photonics, and solar cells, among others. However, for most of these applications to be feasible, it is necessary to integrate these materials with the current existing silicon technology. Although chemical vapor deposition is a promising method for the growth of high-quality and large-area TMD crystals, the high temperatures necessary for the growth make this technique incompatible with the processes used in the semiconductor industry. Herein, we demonstrate the possibility of low-temperature growth of TMDs, using tungsten selenide (WSe 2 ) as a model, by simply using moisture-assisted defective tungsten oxide (WO 3 ) precursor powders during the growth of these materials. Density functional theory calculations reveal the mechanism by which moisture promotes the defect formation on the precursor crystal structure and how it dictates the reduction of the temperature of the growth. The results were compared with the standard growth at high temperatures and with a precursor mixture with alkali salts to show the high quality of the WSe 2 grown at temperatures as low as 550 °C. To conclude, the work improves the understanding of nucleation and growth mechanisms of WSe 2 at low temperatures and provides a useful strategy for the growth of TMDs at temperatures required for the back-end-of-line compatibility with current silicon technology.

2D materials↗
DOE OSTI2020

DFF Layout Variations in CMOS SOI—Analysis of Hardening by Design Options

Four D flip-flop (DFF) layouts were created from the same schematic in Sandia National Laboratories’ CMOS7 silicon-on-insulator (SOI) process. Single-event upset (SEU) modeling and testing showed an improved response with the use of shallow (not fully bottomed) N-type metal-oxide-semiconductor field-effect transistors (NMOSFETs), extending the size of the drain implant and increasing the critical charge of the transmission gates in the circuit design and layout. This research also shows the importance of correctly modeling nodal capacitance, which is a major factor determining SEU critical charge. Accurate SEU models enable the understanding of the SEU vulnerabilities and how to make the design more robust.

42 ENGINEERING↗
DOE OSTI2024

Low Resistance Contact to P-Type Monolayer WSe 2

Advanced microelectronics in the future may require semiconducting channel materials beyond silicon. Two-dimensional (2D) semiconductors, with their atomically thin thickness, hold great promise for future electronic devices. One challenge to achieving high-performance 2D semiconductor field effect transistors (FET) is the high contact resistance at the metal-semiconductor interface. Here, in this study, we develop a charge-transfer doping strategy with WSe 2 /α-RuCl 3 heterostructures to achieve low-resistance ohmic contact for p-type monolayer WSe2 transistors. We show that hole doping as high as 3 × 10 13 cm -2 can be achieved in the WSe 2 /α-RuCl 3 heterostructure due to its type-III band alignment, resulting in an ohmic contact with resistance of 4 kΩ μm. Based on that, we demonstrate p-type WSe 2 transistors with an on-current of 35 μA·μm -1 and an I ON /I OFF ratio exceeding 10 9 at room temperature.

36 MATERIALS SCIENCE↗
DOE OSTI2021

FAIR DEAL Grand Challenge Overview

While it is likely practically a bad idea to shrink a transistor to the size of an atom, there is no arguing that it would be fantastic to have atomic-scale control over every aspect of a transistor – a kind of crystal ball to understand and evaluate new ideas. This project showed that it was possible to take a niche technique used to place dopants in silicon with atomic precision and apply it broadly to study opportunities and limitations in microelectronics. In addition, it laid the foundation to attaining atomic-scale control in semiconductor manufacturing more broadly.

74 ATOMIC AND MOLECULAR PHYSICS↗
DOE OSTI2023

Radiation tolerance studies of the HV-mux GaNFETs for the HL-LHC ATLAS ITk Strip detector

For the High-Luminosity upgrade of the LHC, the current ATLAS inner detector will be replaced with a new silicon charged-particle tracker, the ITk, which consists of the ITk Pixel and the ITk Strip subdetector. The high voltage multiplexing (HV-Mux) GaNFETs are radiation-tolerant transistors that permit switching off high voltage to malfunctioning sensors on the ITk Strip modules. To ensure the reliability of the GaNFETs in the high radiation environment expected at the HL-LHC, a sample of the production batch was exposed to gamma radiation. Finally, the GaNFETs were characterized pre-irradiation and post-irradiation, and monitored during irradiation.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2022

Atomic-scale defects generated in the early/intermediate stages of dielectric breakdown in Si/SiO 2 transistors

In this study, electrically detected magnetic resonance and near-zero-field magnetoresistance measurements were used to study atomic-scale traps generated during high-field gate stressing in Si/SiO 2 MOSFETs. The defects observed are almost certainly important to time-dependent dielectric breakdown. The measurements were made with spin-dependent recombination current involving defects at and near the Si/SiO 2 boundary. The interface traps observed are P b0 and P b1 centers, which are silicon dangling bond defects. The ratio of P b0 /P b1 is dependent on the gate stressing polarity. Electrically detected magnetic resonance measurements also reveal generation of E' oxide defects near the Si/SiO 2 interface. Near-zero-field magnetoresistance measurements made throughout stressing reveal that the local hyperfine environment of the interface traps changes with stressing time; these changes are almost certainly due to the redistribution of hydrogen near the interface.

42 ENGINEERING↗
DOE OSTI2020

Accessing Atomic-scale Phosphorus Dopant Distribution in Precise Silicon Devices by Advanced STEM Imaging and Spectroscopy

The structural and chemical characterization at the atomic-scale plays a critical role in understanding the structure-property relationship in precise electrical devices such as those produced by atomic-precision advanced manufacturing (APAM). APAM, utilizing hydrogen lithography in a scanning tunneling microscope, offers a potential pathway to ultra-efficient transistors, and has been developed to produce phosphorus (P)-based donor devices integrated into bare Si substrates. Structural characterization of the buried, Si with P dopant (Si:P) delta-layer in the devices by scanning transmission electron microscopy (STEM), however, is a challenge due to similar atomic number and low concentration of the P dopants. In this paper, we describe several efforts of utilizing advanced STEM imagining and spectroscopic techniques to quantify the Si:P deltalayers. STEM imaging combining low-angle and high-angle annular dark-field (LAADF, HAADF) detectors as well as atomic-scale elemental mapping using energy-dispersive X-ray spectroscopy (EDS) are used to reveal the P and defect distribution across the delta-layer processed under various thermal conditions.

47 OTHER INSTRUMENTATION↗