Search NASA⌕ Search

SEARCH · Search NASA

Results for “System on Chip (SOC)”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
NASA NTRS2005

Use of Field Programmable Gate Array Technology in Future Space Avionics

Fulfilling NASA's new vision for space exploration requires the development of sustainable, flexible and fault tolerant spacecraft control systems. The traditional development paradigm consists of the purchase or fabrication of hardware boards with fixed processor and/or Digital Signal Processing (DSP) components interconnected via a standardized bus system. This is followed by the purchase and/or development of software. This paradigm has several disadvantages for the development of systems to support NASA's new vision. Building a system to be fault tolerant increases the complexity and decreases the performance of included software. Standard bus design and conventional implementation produces natural bottlenecks. Configuring hardware components in systems containing common processors and DSPs is difficult initially and expensive or impossible to change later. The existence of Hardware Description Languages (HDLs), the recent increase in performance, density and radiation tolerance of Field Programmable Gate Arrays (FPGAs), and Intellectual Property (IP) Cores provides the technology for reprogrammable Systems on a Chip (SOC). This technology supports a paradigm better suited for NASA's vision. Hardware and software production are melded for more effective development; they can both evolve together over time. Designers incorporating this technology into future avionics can benefit from its flexibility. Systems can be designed with improved fault isolation and tolerance using hardware instead of software. Also, these designs can be protected from obsolescence problems where maintenance is compromised via component and vendor availability.To investigate the flexibility of this technology, the core of the Central Processing Unit and Input/Output Processor of the Space Shuttle AP101S Computer were prototyped in Verilog HDL and synthesized into an Altera Stratix FPGA.

Ferguson, Roscoe C.↗
NASA NTRS2019

Radiation specification and testing of heterogenous microprocessor SOCs

Modern commercial microprocessor devices include multiple processor architectures, buses, basic peripherals, and application hardware such as Graphics Processing Units (GPUs) and Digital Signal Processors (DSPs) in one device. Developing RHBD versions of similar devices risks sacrificing processing performance for system-wide radiation requirements. The heterogenous structure of modern commercial system on a chip (SOC) devices, in design and performance goals for subsystems, suggests a similar approach to specifying Radiation Hardened by Design (RHBD) requirements.

Ballast, Jon↗
NASA NTRS2001

Electrically Isolating Thermally Coupled Device for Noise Suppression of Circuits in Deep Space

Mixed mode rad hard avionics Systems on a Chip (SoC) designed for deep space applications such as Europa orbiters and Europa Landers will require data isolation circuits to block noise. This paper presents the simulation performance for a novel rad hard SOI CMOS compatible thermal transducer used for on-chip data isolation in SoC. The research presented involves the use of commercially available computer aided design tools to model the transient electrothermal behavior of the transducer. Both one- and two-dimensional analyses of a prototype thermal transducer were performed. Results indicate that thermal-based data isolator technology can pass a data bit in under a microsecond and, as a measurement of feasibility, I(exp 2)C bus specifications can be met.

Mantooth, A.↗
NASA NTRS2004

High Electron Mobility Transistor Structures on Sapphire Substrates Using CMOS Compatible Processing Techniques

System-on-a-chip (SOC) processes are under intense development for high-speed, high frequency transceiver circuitry. As frequencies, data rates, and circuit complexity increases, the need for substrates that enable high-speed analog operation, low-power digital circuitry, and excellent isolation between devices becomes increasingly critical. SiGe/Si modulation doped field effect transistors (MODFETs) with high carrier mobilities are currently under development to meet the active RF device needs. However, as the substrate normally used is Si, the low-to-modest substrate resistivity causes large losses in the passive elements required for a complete high frequency circuit. These losses are projected to become increasingly troublesome as device frequencies progress to the Ku-band (12 - 18 GHz) and beyond. Sapphire is an excellent substrate for high frequency SOC designs because it supports excellent both active and passive RF device performance, as well as low-power digital operations. We are developing high electron mobility SiGe/Si transistor structures on r-plane sapphire, using either in-situ grown n-MODFET structures or ion-implanted high electron mobility transistor (HEMT) structures. Advantages of the MODFET structures include high electron mobilities at all temperatures (relative to ion-implanted HEMT structures), with mobility continuously improving to cryogenic temperatures. We have measured electron mobilities over 1,200 and 13,000 sq cm/V-sec at room temperature and 0.25 K, respectively in MODFET structures. The electron carrier densities were 1.6 and 1.33 x 10(exp 12)/sq cm at room and liquid helium temperature, respectively, denoting excellent carrier confinement. Using this technique, we have observed electron mobilities as high as 900 sq cm/V-sec at room temperature at a carrier density of 1.3 x 10(exp 12)/sq cm. The temperature dependence of mobility for both the MODFET and HEMT structures provides insights into the mechanisms that allow for enhanced electron mobility as well as the processes that limit mobility, and will be presented.

Mueller, Carl↗
NASA NTRS2006

Time of flight system on a chip

A CMOS time-of-flight TOF system-on-a-chip SoC for precise time interval measurement with low power consumption and high counting rate has been developed. The analog and digital TOF chip may include two Constant Fraction Discriminators CFDs and a Time-to-Digital Converter TDC. The CFDs can interface to start and stop anodes through two preamplifiers and perform signal processing for time walk compensation (110). The TDC digitizes the time difference with reference to an off-chip precise external clock (114). One TOF output is an 11-bit digital word and a valid event trigger output indicating a valid event on the 11-bit output bus (116).

Paschalidis, Nicholas P.↗
NASA NTRS2014

A 0.18 micrometer CMOS Thermopile Readout ASIC Immune to 50 MRAD Total Ionizing Dose (SI) and Single Event Latchup to 174MeV-cm(exp 2)/mg

Radiation hardened by design (RHBD) techniques allow commercial CMOS circuits to operate in high total ionizing dose and particle fluence environments. Our radiation hard multi-channel digitizer (MCD) ASIC (Figure 1) is a versatile analog system on a chip (SoC) fabricated in 180nm CMOS. It provides 18 chopper stabilized amplifier channels, a 16- bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The MCD was evaluated at Goddard Space Flight Center and Texas A&M University's radiation effects facilities and found to be immune to single event latchup (SEL) and total ionizing dose (TID) at 174 MeV-cm(exp 2)/mg and 50 Mrad (Si) respectively.

radiation hardened by design↗
NASA NTRS2015

Preliminary Radiation Testing of a State-of-the-Art Commercial 14nm CMOS Processor - System-on-a-Chip

Hardness assurance test results of Intel state-of-the-art 14nm Broadwell U-series processor System-on-a-Chip (SoC) for total dose are presented, along with first-look exploratory results from trials at a medical proton facility. Test method builds upon previous efforts by utilizing commercial laptop motherboards and software stress applications as opposed to more traditional automated test equipment (ATE).

14nm↗
NASA NTRS2015

Preliminary Radiation Testing of a State-of-the-Art Commercial 14nm CMOS Processor/System-on-a-Chip

Hardness assurance test results of Intel state-of-the-art 14nm “Broadwell” U-series processor / System-on-a-Chip (SoC) for total ionizing dose (TID) are presented, along with exploratory results from trials at a medical proton facility. Test method builds upon previous efforts [1] by utilizing commercial laptop motherboards and software stress applications as opposed to more traditional automated test equipment (ATE).

microprocessor↗
NASA NTRS2015

Reconfigurable Very Long Instruction Word (VLIW) Processor

Future NASA missions will depend on radiation-hardened, power-efficient processing systems-on-a-chip (SOCs) that consist of a range of processor cores custom tailored for space applications. Aries Design Automation, LLC, has developed a processing SOC that is optimized for software-defined radio (SDR) uses. The innovation implements the Institute of Electrical and Electronics Engineers (IEEE) RazorII voltage management technique, a microarchitectural mechanism that allows processor cores to self-monitor, self-analyze, and selfheal after timing errors, regardless of their cause (e.g., radiation; chip aging; variations in the voltage, frequency, temperature, or manufacturing process). This highly automated SOC can also execute legacy PowerPC 750 binary code instruction set architecture (ISA), which is used in the flight-control computers of many previous NASA space missions. In developing this innovation, Aries Design Automation has made significant contributions to the fields of formal verification of complex pipelined microprocessors and Boolean satisfiability (SAT) and has developed highly efficient electronic design automation tools that hold promise for future developments.

Velev, Miroslav N.↗
DOE OSTI2026

The future of subsurface monitoring: AEC’s breakthroughs in CCS technology

Carbon capture and storage (CCS) has emerged as a key solution in the fight against climate change. However, for CCS to succeed, it is crucial to ensure that the sequestered CO2 stays safely trapped underground. The U.S. Department of Energy (DOE) has emphasized the need for advancements in subsurface monitoring, measurement, reporting, and verification. Aside from caprock integrity failure, the other primary failure points usually involve defective cement in the casing annulus of wellbores or plugged and abandoned wells. In addition, many energy producers (e.g., oil and gas, geothermal) and storage and disposal operators (e.g., H2 and water) must deal with the same issue. Poorly placed or degraded cement can create pathways for gas or fluid to escape from casing annuli and in plugged and abandoned or orphan wells, posing environmental risks. Yet, a reliable and cost-effective way to monitor cement and well integrity over multiple decades is still unavailable. Traditional geophysical methods like 4D seismic imaging and surface-based electromagnetic monitoring lack the resolution and accuracy for detecting these types of failures (Vasco et al., 2022; Fawad and Mondol, 2021). Wireline logging is expensive to run continuously and is obtrusive to the operation. While fiber optics can potentially be a solution, its bulkiness can significantly compromise the cement's integrity. To address these challenges, the Advanced Energy Consortium (AEC) at The University of Texas at Austin’s Bureau of Economic Geology (the Bureau) has been pioneering research in subsurface monitoring using its portfolio of distributed autonomous microfabricated sensors for harsh subsurface environments since 2008. A class of these microsensors [System on a Chip (SoC)] can be mixed in cement and permanently placed without compromising the cement column; the sensors would then communicate with each other or a data acquisition (DAQ) master node. Another class of the AEC microsensors can be fully autonomous, with rechargeable micro-batteries capable of exceeding 100°C, flash memory, and, currently, a pressure and temperature sensor. They are designed to circulate in mud, geothermal fluids, U-loops, or pipelines. They can log data into memory and are unobtrusive to operations. Our team has been working on a multi-year DOE-funded project (DE-FE0031856)—supported by $2.95M in federal funding and $0.75M in cost-matching from the AEC—to demonstrate SoC sensor utility for CO2 leakage monitoring in CCS applications. This multi-institutional collaboration developed a novel sensing architecture utilizing radiofrequency (RF) microsensors embedded within the cement sheath. These sensors detect CO2 migration and are interrogated via a Smart Casing Collar (SCC).

58 GEOSCIENCES↗
DOE OSTI2020

Software-Defined Ultrasonic Communication System Based on Time-reversal Signal Processing

Ultrasonic communication through solid channels suffers from channel dispersion, attenuation, and multipath effect. For example, in elbow shape pipes or complex structures, the elastic waves are reflected and reverberated in multipath resulting in a major dispersion of the signals. In solid channels such as flat bar, multipath propagation is the main reason for bit-wavelet spreading and intersymbol interference (ISI). The conventional modulation method like OOK (on-off-keying) or PSK (phase-shift-keying) fails to provide a useful Signal-to-Noise Ratio (SNR). Time-reversal (TR) signal processing method is a promising technique that can compress the spreading of the bit-wavelet and strengthen the peak signal energy on the receiver. In this study, Finite Element Analysis (FEA) using ABAQUS software tools is used to characterize the bit-wavelet spreading effect caused by dispersive communication channels. Also, this study presents the impact of TR ultrasonic communication as a function of excitation pulse width, channel length, and carrier frequency through a flat-bar channel. A Software-Defined System-on-Chip (SD-SoC) platform is examined as a viable solution for the low-complexity and energy-efficient ultrasonic communication system. The proposed TR based SD-SoC ultrasonic communication system can make full use of signal dispersion for peak performance by minimizing the ISI within a dispersive and reverberant metal channel.

FEM simulation↗
DOE OSTI2025

Radio Frequency Field Programable Gate Array Implementation of Reflectometry Cable Monitoring

This document describes the development of a field programable gate array (FPGA) radio frequency system on a chip (RF SoC) adaptation and evaluation of the single-board device to perform both Frequency Domain Reflectometry (FDR) and Spread Spectrum Time Domain Reflectometry (SSTDR) for offline and online cable testing. The work builds on and leverages the work of Pacific Northwest National Laboratory (PNNL) in airport millimeter wave technology by using the same development hardware employed in that program. The work is performed under sponsorship from the U.S. Department of Energy (DOE) Light Water Reactor Sustainability (LWRS) program and the task objective is to confirm and demonstrate feasibility to adapt FPGA technology for a cost-effective multiplexed single-board electronic module to perform cable tests that are equivalent to commercial and laboratory test instruments for FDR and SSTDR cable tests. The developed 2-channel (extendable to 7 channels) system was compared to dedicated and proven test instruments and shown to produce equivalent results on a range of cables and with a range of damage types. The FPGA reflectometry test board is one of several technologies that could facilitate implementation of online monitoring of safety critical cable systems.

42 ENGINEERING↗
DOE OSTI2025

Passband Signal Detection at the Edge

Algorithms for radio frequency (RF) spectrum awareness need to be compatible with edge hardware to be practical for many applications. We developed a signal detection and classification model for the ZCU111 RF System-on-a-Chip (RFSoC) that operates on the fast Fourier transform of passband RF data. The system can detect and classify multiple signals of interest and display the predictions in real-time. The model consists of a modified ConvNeXt backbone and YOLOv3 head to operate on the Deep Learning Processing Unit on the RFSoC. We gathered datasets for training and testing by using a software defined radio to transmit example signals of Wi-Fi 802.11 b/g, Wi-Fi 802.11 n, FM Radio, LTE and LTE-M. By leveraging multiple inputs on the RFSoC frontend, the datasets span up to 4 GHz of bandwidth. The models showed high performance in classification accuracy, center frequency error, bandwidth error, and detection accuracy for both single and multi-signal datasets.

42 ENGINEERING↗
NASA NTRS2019

Proton Testing of AMD Ryzen 3 1200 Microprocessors

Single-Event Effects (SEE) testing was conducted on the AMD Ryzen 3 1200 microprocessor. Testing was conducted at Massachusetts General Hospital's (MGH) Francis H. Burr Proton Therapy Center on June 2nd, 2019.

single event functional interrupt (SEFI)↗
NASA NTRS2019

Proton Testing of AMD Ryzen 3 2200G Microprocessors

Single-Event Effects (SEE) testing was conducted on the AMD Ryzen 3 2200G microprocessor with integrated graphics. Testing was conducted at Massachusetts General Hospital's (MGH) Francis H. Burr Proton Therapy Center on June 2nd, 2019.

radiation tesing↗