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At least 55 records · Page 3

On the error statistics of Viterbi decoding and the performance of concatenated codes

Computer simulation results are presented on the performance of convolutional codes of constraint lengths 7 and 10 concatenated with the (255, 223) Reed-Solomon code (a proposed NASA standard). These results indicate that as much as 0.8 dB can be gained by concatenating this Reed-Solomon code with a (10, 1/3) convolutional code, instead of the (7, 1/2) code currently used by the DSN. A mathematical model of Viterbi decoder burst-error statistics is developed and is validated through additional computer simulations.

Miller, R. L.↗

The effects of Viterbi decoder node synchronization losses on the telemetry receiving system

The Viterbi decoders currently used by the Deep space Network (DSN) use an algorithm for maintaining node synchronization that breaks down at bit signal-to-noise ratios (SNRs) of about 2.0 dB. It is shown that this can become an important consideration when the effects of noisy carrier referencing are combined with the lower SNRs that are expected at Voyager 2 Uranus and Neptune encounters. Depending on the available carrier power, node synchronization losses of between 0.85 and 1.25 dB can be expected in addition to the radio loss.

Deutsch, L. J.↗

Improving the performance of soft decision Viterbi decoding in a non-Gaussian environment through non-linear quantization

The performance of Viterbi decoding in a non-Gaussian environment is investigated using a nonlinear quantization strategy. The channel model consists of a convolutionally encoded BPSK signal transmitted to a satellite where it is corrupted with additive white Gaussian noise and pulsed radio frequency interference (RFI). The resultant signal is then passed through a satellite nonlinearity and transmitted to a ground station where it is coherently detected. Interleaving is assumed in order to make the channel memoryless. The presence of RFI makes the channel statistics non-Gaussian, leading to a nonlinear log-likelihood function. A near optimum quantization scheme is found by maximizing a channel parameter, or by matching the quantizer to the log-likelihood function in a mean square error sense. Bit error rate performance improvement is achieved by using such nonlinear quantization.

Mcgregor, D. N.↗

Viterbi decoder node synchronization losses in the Reed-Solomon/Veterbi concatenated channel

The Viterbi decoders currently used by the Deep Space Network (DSN) employ an algorithm for maintaining node synchronization that significantly degrades at bit signal-to-noise ratios (SNRs) of below 2.0 dB. In a recent report by the authors, it was shown that the telemetry receiving system, which uses a convolutionally encoded downlink, will suffer losses of 0.85 dB and 1.25 dB respectively at Voyager 2 Uranus and Neptune encounters. This report extends the results of that study to a concatenated (255,223) Reed-Solomon/(7, 1/2) convolutionally coded channel, by developing a new radio loss model for the concatenated channel. It is shown here that losses due to improper node synchronization of 0.57 dB at Uranus and 1.0 dB at Neptune can be expected if concatenated coding is used along with an array of one 64-meter and three 34-meter antennas.

Deutsch, L. J.↗

Node Synchronization for the Viterbi Decoder

At very low signal to noise ratios such as those that Voyager 2 will encounter at Uranus, the performance of the Reed-Solomon/Viterbi concatenated coding system could be seriously degraded by loss of node synchronization by the Viterbi decoder. This problem is described and now it can be almost completely avoided with a simple outboard hardware ""node synchronizer''. This device makes statistical decisions about node sync based on the hard quantized undecoded data stream. In a worst case Voyager-like environment, our method will detect and correct a true loss of node sync (thought to be a very rate event) within several hundred bits; many of these false alarms for our technique is on the order several years.

Lorden, G.↗

Performance Simulation for Unit-memory Convolutional Codes with Byte-oriented Viterbi Decoding Algorithm

A software package developed to simulate the performance of the byte-oriented Viterbi decoding algorithm for unit-memory (UM) codes on both 3-bit and 4-bit quantized AWGN channels is described. The simulation is shown to require negligible memory and less time than that for the RTMBEP algorith, although they both provide similar performance in terms of symbol-error probability. This makes it possible to compute the symbol-error probability of large codes and to determine the signal-to-noise ratio required to achieve a bit error rate (BER) of 0.000001 for corresponding concatenated systems. A (7, 10/48) UM code, 10-bit Reed-Solomon code combination achieves the required BER at 1.08 dB for a 3-bit quantized channel and at 0.91 dB for a 4-bit quantized channel.

Vo, Q. D.↗

Node synchronization for the Viterbi decoder

At very low signal to noise ratios such as those that Voyager 2 will encounter at Uranus, the performance of the Reed-Solomon/Viterbi concatenated coding system could be seriously degraded by loss of node synchronization by the Viterbi decoder. This problem is described and now it can be almost completely avoided with a simple outboard hardware 'node synchronizer'. This device makes statistical decisions about node sync based on the hard quantized undecoded data stream. In a worst case Voyager-like environment, our method will detect and correct a true loss of node sync (thought to be a very rare event) within several hundred bits; many of these false alarms for our technique is on the order several years. Previously announced in STAR as N83-28028

Lorden, G.↗

Effects of ISI and satellite channel nonlinearity on Viterbi demodulation/decoding

It is shown that, for convolutionally coded transmission over bandwidth-constrained channels, a mere reversal of the switching direction at the encoder output produces a change in the system bit error probability performance. This change is significant when the Viterbi demodulator/decoder is matched to the total channel memory and is more significant for linear channels than for nonlinear ones. The reversal of switching direction is a simple demonstration of the fact that the well-known optimum codes for the linear AGWN channel are no longer necessarily optimum for a bandwidth-constrained channel with or without the addition of channel nonlinearity. It is concluded that potentially significant performance improvement can be obtained by matching the encoder (through the appropriate choice of tap weights and modulo-2 summers) to the channel in addition to matching the demodulator/decoder to the channel for a given encoder.

Divsalar, D.↗

A Very Efficient Transfer Function Bounding Technique on Bit Error Rate for Viterbi Decoded, Rate 1/N Convolutional Codes

For rate 1/N convolutional codes, a recursive algorithm for finding the transfer function bound on bit error rate (BER) at the output of a Viterbi decoder is described. This technique is very fast and requires very little storage since all the unnecessary operations are eliminated. Using this technique, we find and plot bounds on the BER performance of known codes of rate 1/2 with K 18, rate 1/3 with K 14. When more than one reported code with the same parameter is known, we select the code that minimizes the required signal to noise ratio for a desired bit error rate of 0.000001. This criterion of determining goodness of a code had previously been found to be more useful than the maximum free distance criterion and was used in the code search procedures of very short constraint length codes. This very efficient technique can also be used for searches of longer constraint length codes.

Lee, P. J.↗

Novel applications of the NASA/GSFC Viterbi decoder hardware simulator

The NASA/GSFC developed an all digital, real time, programmable Viterbi decoder simulator operating at rates up to 6 Msps. With this simulator, the bit error rate (BER) performance of convolutionally encoded/Viterbi decoded Shuttle-TDRSS return link channels under pulsed radio frequency interference (RFI) conditions has been predicted. The principles of the simulator are described with special emphasis on the channel simulator and the essential interaction between CLASS software and the simulator. The sensitivity of coded BER as function of several illustrative RFI parameters is discussed for two typical Shuttle-TDRSS return link configurations.

Walvis, D. J. M.↗

Choosing channel quantization levels and viterbi decoding for space diversity reception over the additive white Guassian noise channel

Previous work in the area of choosing channel quantization levels for a additive white Gaussian noise channel composed of one receiver-demodulator is reviewed, and how this applies to the Deep Space Network composed of several receiver-demodulators (space diversity reception) is shown. Viterbi decoding for the resulting quantized channel is discussed.

Kalson, S.↗

Erasure declaring Viterbi decoders

Several methods for realizing erasure declaring Viterbi decoders for the (7,1/2) NASA code are discussed. Only bit oriented algorithms are considered. When such decoders are used in a concatenated system with a (255,223) Reed-Solomon decoder, improvements on the probability of word error of at most 0.1 dB were obtained.

Pollara, F.↗

A software simulation study of the long constraint length VLSI Viterbi decoder

A software simulation of long constraint length Viterbi decoders was developed. This software closely follows the hardware architecture that was chosen for the Very Large Scale Integration implementation. The program is used to validate the design of the decoder and to generate test vectors for the VLSI circuits.

Arnold, S.↗

Test aspects of the JPL Viterbi decoder

The generation of test vectors and design-for-test aspects of the Jet Propulsion Laboratory (JPL) Very Large Scale Integration (VLSI) Viterbi decoder chip is discussed. Each processor integrated circuit (IC) contains over 20,000 gates. To achieve a high degree of testability, a scan architecture is employed. The logic has been partitioned so that very few test vectors are required to test the entire chip. In addition, since several blocks of logic are replicated numerous times on this chip, test vectors need only be generated for each block, rather than for the entire circuit. These unique blocks of logic have been identified and test sets generated for them. The approach employed for testing was to use pseudo-exhaustive test vectors whenever feasible. That is, each cone of logid is tested exhaustively. Using this approach, no detailed logic design or fault model is required. All faults which modify the function of a block of combinational logic are detected, such as all irredundant single and multiple stuck-at faults.

Breuer, M. A.↗

On testing VLSI chips for the big Viterbi decoder

A general technique that can be used in testing very large scale integrated (VLSI) chips for the Big Viterbi Decoder (BVD) system is described. The test technique is divided into functional testing and fault-coverage testing. The purpose of functional testing is to verify that the design works functionally. Functional test vectors are converted from outputs of software simulations which simulate the BVD functionally. Fault-coverage testing is used to detect and, in some cases, to locate faulty components caused by bad fabrication. This type of testing is useful in screening out bad chips. Finally, design for testability, which is included in the BVD VLSI chip design, is described in considerable detail. Both the observability and controllability of a VLSI chip are greatly enhanced by including the design for the testability feature.

Hsu, I. S.↗

A long constraint length VLSI Viterbi decoder for the DSN

A Viterbi decoder, capable of decoding convolutional codes with constraint lengths up to 15, is under development for the Deep Space Network (DSN). The objective is to complete a prototype of this decoder by late 1990, and demonstrate its performance using the (15, 1/4) encoder in Galileo. The decoder is expected to provide 1 to 2 dB improvement in bit SNR, compared to the present (7, 1/2) code and existing Maximum Likelihood Convolutional Decoder (MCD). The decoder will be fully programmable for any code up to constraint length 15, and code rate 1/2 to 1/6. The decoder architecture and top-level design are described.

Statman, J. I.↗

Large-Constraint-Length, Fast Viterbi Decoder

Scheme for efficient interconnection makes VLSI design feasible. Concept for fast Viterbi decoder provides for processing of convolutional codes of constraint length K up to 15 and rates of 1/2 to 1/6. Fully parallel (but bit-serial) architecture developed for decoder of K = 7 implemented in single dedicated VLSI circuit chip. Contains six major functional blocks. VLSI circuits perform branch metric computations, add-compare-select operations, and then store decisions in traceback memory. Traceback processor reads appropriate memory locations and puts out decoded bits. Used as building block for decoders of larger K.

Collins, O.↗

Memory management in traceback Viterbi decoders

The new Viterbi decoder for long constraint length codes, under development for the Deep Space Network, stores path information according to an algorithm called traceback. The details of a particular implementation of this algorithm, based on three memory buffers, are described. The penalties in increased storage requirement and longer decoding delay are offset by the reduced amount of data that needs to be exchanged between processors, in a parallel architecture decoder.

Collins, O.↗