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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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44 records · Page 3
All sourcesNASA NTRSDOE OSTI
NASA NTRS2007

Design and Fabrication of High-Efficiency CMOS/CCD Imagers

An architecture for back-illuminated complementary metal oxide/semiconductor (CMOS) and charge-coupled-device (CCD) ultraviolet/visible/near infrared- light image sensors, and a method of fabrication to implement the architecture, are undergoing development. The architecture and method are expected to enable realization of the full potential of back-illuminated CMOS/CCD imagers to perform with high efficiency, high sensitivity, excellent angular response, and in-pixel signal processing. The architecture and method are compatible with next-generation CMOS dielectric-forming and metallization techniques, and the process flow of the method is compatible with process flows typical of the manufacture of very-large-scale integrated (VLSI) circuits. The architecture and method overcome all obstacles that have hitherto prevented high-yield, low-cost fabrication of back-illuminated CMOS/CCD imagers by use of standard VLSI fabrication tools and techniques. It is not possible to discuss the obstacles in detail within the space available for this article. Briefly, the obstacles are posed by the problems of generating light-absorbing layers having desired uniform and accurate thicknesses, passivation of surfaces, forming structures for efficient collection of charge carriers, and wafer-scale thinning (in contradistinction to diescale thinning). A basic element of the present architecture and method - the element that, more than any other, makes it possible to overcome the obstacles - is the use of an alternative starting material: Instead of starting with a conventional bulk-CMOS wafer that consists of a p-doped epitaxial silicon layer grown on a heavily-p-doped silicon substrate, one starts with a special silicon-on-insulator (SOI) wafer that consists of a thermal oxide buried between a lightly p- or n-doped, thick silicon layer and a device silicon layer of appropriate thickness and doping. The thick silicon layer is used as a handle: that is, as a mechanical support for the device silicon layer during micro-fabrication.

Pain, Bedabrata↗
NASA NTRS2013

Planar Superconducting Millimeter-Wave/Terahertz Channelizing Filter

This innovation is a compact, superconducting, channelizing bandpass filter on a single-crystal (0.45 m thick) silicon substrate, which operates from 300 to 600 GHz. This device consists of four channels with center frequencies of 310, 380, 460, and 550 GHz, with approximately 50-GHz bandwidth per channel. The filter concept is inspired by the mammalian cochlea, which is a channelizing filter that covers three decades of bandwidth and 3,000 channels in a very small physical space. By using a simplified physical cochlear model, and its electrical analog of a channelizing filter covering multiple octaves bandwidth, a large number of output channels with high inter-channel isolation and high-order upper stopband response can be designed. A channelizing filter is a critical component used in spectrometer instruments that measure the intensity of light at various frequencies. This embodiment was designed for MicroSpec in order to increase the resolution of the instrument (with four channels, the resolution will be increased by a factor of four). MicroSpec is a revolutionary wafer-scale spectrometer that is intended for the SPICA (Space Infrared Telescope for Cosmology and Astrophysics) Mission. In addition to being a vital component of MicroSpec, the channelizing filter itself is a low-resolution spectrometer when integrated with only an antenna at its input, and a detector at each channel s output. During the design process for this filter, the available characteristic impedances, possible lumped element ranges, and fabrication tolerances were identified for design on a very thin silicon substrate. Iterations between full-wave and lumped-element circuit simulations were performed. Each channel s circuit was designed based on the availability of characteristic impedances and lumped element ranges. This design was based on a tabular type bandpass filter with no spurious harmonic response. Extensive electromagnetic modeling for each channel was performed. Four channels, with 50-GHz bandwidth, were designed, each using multiple transmission line media such as microstrip, coplanar waveguide, and quasi-lumped components on 0.45- m thick silicon. In the design process, modeling issues had to be overcome. Due to the extremely high frequencies, very thin Si substrate, and the superconducting metal layers, most commercially available software fails in various ways. These issues were mitigated by using alternative software that was capable of handling them at the expense of greater simulation time. The design of on-chip components for the filter characterization, such as a broadband antenna, Wilkinson power dividers, attenuators, detectors, and transitions has been completed.

Ehsan, Negar↗
NASA NTRS2011

High-Throughput Processes and Structural Characterization of Single-Nanotube Based Devices for 3D Electronics

We have developed manufacturable approaches to form single, vertically aligned carbon nanotubes, where the tubes are centered precisely, and placed within a few hundred nm of 1-1.5 micron deep trenches. These wafer-scale approaches were enabled by chemically amplified resists and inductively coupled Cryo-etchers to form the 3D nanoscale architectures. The tube growth was performed using dc plasmaenhanced chemical vapor deposition (PECVD), and the materials used for the pre-fabricated 3D architectures were chemically and structurally compatible with the high temperature (700 C) PECVD synthesis of our tubes, in an ammonia and acetylene ambient. The TEM analysis of our tubes revealed graphitic basal planes inclined to the central or fiber axis, with cone angles up to 30 deg. for the particular growth conditions used. In addition, bending tests performed using a custom nanoindentor, suggest that the tubes are well adhered to the Si substrate. Tube characteristics were also engineered to some extent, by adjusting growth parameters, such as Ni catalyst thickness, pressure and plasma power during growth.

top-down fabrication↗
NASA NTRS2009

High-Throughput Top-Down and Bottom-Up Processes for Forming Single-Nanotube Based Architectures for 3D Electronics

We have developed manufacturable approaches to form single, vertically aligned carbon nanotubes, where the tubes are centered precisely, and placed within a few hundred nm of 1-1.5 micron deep trenches. These wafer-scale approaches were enabled by chemically amplified resists and inductively coupled Cryo-etchers for forming the 3D nanoscale architectures. The tube growth was performed using dc plasma-enhanced chemical vapor deposition (PECVD), and the materials used for the pre-fabricated 3D architectures were chemically and structurally compatible with the high temperature (700 C) PECVD synthesis of our tubes, in an ammonia and acetylene ambient. Tube characteristics were also engineered to some extent, by adjusting growth parameters, such as Ni catalyst thickness, pressure and plasma power during growth. Such scalable, high throughput top-down fabrication techniques, combined with bottom-up tube synthesis, should accelerate the development of PECVD tubes for applications such as interconnects, nano-electromechanical (NEMS), sensors or 3D electronics in general.

plasma-enhanced chemical vapor deposition (PECVD),↗
NASA NTRS2016

Key Elements of a Low Voltage, Ultracompact Plasma Spectrometer

Taking advantage of technological developments in wafer-scale processing over the past two decades, such as deep etching, 3-D chip stacking, and double-sided lithography, we have designed and fabricated the key elements of an ultracompact 1.5cm (exp 3)plasma spectrometer that requires only low-voltage power supplies, has no microchannel plates, and has a high aperture area to instrument volume ratio. The initial design of the instrument targets the measurement of charged particles in the 3-20keV range with a highly directional field of view and a 100 duty cycle; i.e., the entire energy range Is continuously measured. In addition to reducing mass, size, and voltage requirements, the new design will affect the manufacturing process of plasma spectrometers, enabling large quantities of identical instruments to be manufactured at low individual unit cost. Such a plasma spectrometer is ideal for heliophysics plasma investigations, particularly for small satellite and multispacecraft missions. Two key elements of the instrument have been fabricated: the collimator and the energy analyzer. An initial collimator transparency of 20 with 3deg x 3deg angular resolution was achieved. The targeted 40 collimator transparency appears readily achievable. The targeted energy analyzer scaling factor of 1875 was achieved; i.e.20 keV electrons were selected for only a 10.7V bias voltage in the energy analyzer.

Scime, E. E.↗
NASA NTRS2016

Electron-Beam Deposition of Superconducting Molybdenum Thin Films for the Development of Mo/Au TES X-Ray Microcalorimeter

We are exploring the properties of electron-beam evaporated molybdenum thin films on silicon nitride coated silicon wafers at substrate temperatures between room temperature and 650 C. The temperature dependence of film stress, transition temperature, and electrical properties are presented. X-ray diffraction measurements are performed to gain information on molybdenum crystallite size and growth. Results show the dominant influence of the crystallite size on the intrinsic properties of our films. Wafer-scale uniformity, wafer yield, and optimal thermal bias regime for TES fabrication are discussed.

Microcalorimeter↗
DOE OSTI2024

Spatially Precise Light‐Activated Dedoping in Wafer‐Scale MoS 2 Films

2D materials, particularly transition metal dichalcogenides (TMDCs), have shown great potential for microelectronics and optoelectronics. However, a major challenge in commercializing these materials is the inability to control their doping at a wafer scale with high spatial fidelity. Interface chemistry is used with the underlying substrate oxide and concomitant exposure to visible light in ambient conditions for photo-dedoping wafer scale MoS 2 . It is hypothesized that the oxide layer traps photoexcited holes, leaving behind long-lived electrons that become available for surface reactions with ambient air at sulfur vacancies (defect sites) resulting in dedoping. Additionally, high fidelity spatial control is showcased over the dedoping process, by laser writing, and fine control achieved over the degree of doping by modulating the illumination time and power density. This localized change in MoS 2 doping density is very stable (at least 7 days) and robust to processing conditions like high temperature and vacuum. The scalability and ease of implementation of this approach can address one of the major issues preventing the “Lab to Fab” transition of 2D materials and facilitate its seamless integration for commercial applications in multi-logic devices, inverters, and other optoelectronic devices.

14 SOLAR ENERGY↗