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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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DOE OSTI2024

An Open-Source Framework for Rapid Validation of Scientific ASICs

Spacely is an open-source framework for the post-silicon validation of analog, digital, and mixed-signal ASICs (Application-Specific Integrated Circuits) which maximizes the reuse of hardware and software, reducing the time taken to achieve meaningful test results. Spacely specifically addresses the needs of small, flexible ASIC design teams commonly found in academia or research institutions which benefit most from sharing the overhead of test stand creation between many unique ASIC designs. Spacely is a set of software, firmware, and design practices. It targets two primary hardware platforms (NI-PXI and Caribou) as well as offering extensible support for bench instruments. Spacely provides a high-level Python interface to all test hardware for accessibility, while also giving more sophisticated teams the opportunity to integrate custom test firmware. The design principles of Spacely are presented, along with a demonstrative example of using Spacely to test a pixel detector readout ASIC.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2025

hls4ml: A Flexible, Open-Source Platform for Deep Learning Acceleration on Reconfigurable Hardware

We present hls4ml, a free and open-source platform that translates machine learning (ML) models from modern deep learning frameworks into high-level synthesis (HLS) code that can be integrated into full designs for field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs). With its flexible and modular design, hls4ml supports a large number of deep learning frameworks and can target HLS compilers from several vendors, including Vitis HLS, Intel oneAPI and Catapult HLS. Together with a wider eco-system for software-hardware co-design, hls4ml has enabled the acceleration of ML inference in a wide range of commercial and scientific applications where low latency, resource usage, and power consumption are critical. In this paper, we describe the structure and functionality of the hls4ml platform. The overarching design considerations for the generated HLS code are discussed, together with selected performance results.

Schulte, Jan-Frederik [Purdue U.] (ORCID:000000034↗
DOE OSTI2025

Automating Testing of DUNE Electronics via a Finite State Machine

The Deep Underground Neutrino Experiment (DUNE) is a flagship international collaboration designed to study neutrinos—tiny, nearly massless particles that may hold answers to fundamental questions about the Universe. Fermilab’s Robotic Test Stand (RTS) plays a critical role in ensuring the quality of approximately 50,000 Application-Specific Integrated Circuit (ASIC) chips that will be used in DUNE’s massive liquid argon detectors. These electronics will be inside the cryostat; therefore, they will need to have a high yield of working chips and low noise. To improve the automation and reliability of the RTS, this project focused on designing and implementing a Python-based finite state machine (FSM) to manage chip handling workflows. The FSM was developed as a modular software framework to coordinate robotic arm movements, manage chip tray positions, and monitor system states during testing. Key features include robust error handling routines, a pause/resume system for safe mid-cycle interruptions, and a simulation mode for iterative testing without hardware dependencies. The system was designed to prepare for seamless integration with RTS hardware components such as the robotic arm and vision system. This integration will streamline collaboration and enable efficient deployment of updates across the six institutions performing testing. The outcomes of this internship contribute to Fermilab’s mission to advance high-energy physics and support the DOE’s national goals by directly improving the testing of equipment to be used in DUNE. The project also provided valuable experience in software design and contributing to the success of DUNE.

Kang, Caleb [Fermilab]↗
DOE OSTI2026

Graphical User Interface for a Biasing Board for the PSEC6

The PSEC6 is an application-specific integrated circuit (ASIC) designed for a readout system for a large area picosecond photodetector (LAPPD). The PSEC6 is currently in fabrication and pending testing. The testing system for the PSEC5, the previous iteration of the ASIC, required expensive and non-portable equipment, because the ASIC needs twelve adjustable reference voltages. The new testing system consists of an low-cost, open-source, cross-platform graphical user interface (GUI), a digital system, and a biasing board. The digital system is the interface between the GUI and biasing board, and can be implemented on a microcontroller or field-programmable gate array (FPGA). The biasing board contains twelve digital-to-analog converters (DACs) that are configurable via the GUI, which gives users the ability to write voltage values to all or specific DACs. The GUI was developed in C on Linux using the widget library GTK4 and cross-compiled for Windows compatibility. I2C and SPI protocols were implemented on an Adafruit Feather ESP32-S3 microcontroller to write commands to the DACs and PSEC6. A hardware implementation of the I2C protocol is in development on an FPGA. Since LAPPDs will be used by the Accelerator Neutrino Neutron Interaction Experiment (ANNIE) at Fermilab, the PSEC6 testing system in this internship project can potentially benefit future neutrino research. The project is relevant to the Department of Energy’s microelectronics mission, because the PSEC6 is an ASIC that will handle fast time signals arriving from the detector for readout. It also provided experience with building a cross-platform user interface, practicing digital design and implementation in hardware description language (HDL), and using simulations to inform new design iterations.

Guerrero, Sasha Camila [North Central Coll.]↗
DOE OSTI2022

Cryogenic electronics for noble liquid neutrino detectors

In this paper we present the general features of cryogenic (or “cold”) electronics for noble liquid time projection chambers, with design principles and details for neutrino physics, a brief history of the technology and details of recent research and development that is driving the design of the detectors under construction. Finally, some comments on future R&D envisioned and the impact of this work on other fields is described. “Cold” in the context of this work applies to CMOS devices operated at 77 K and above, at liquids temperatures of LAr (89 K), LKr (125 K) and LXe (165 K), with most of the tests performed in, or at LN 2 (77 K). Additionally, the paper is concentrated on the design of cold electronics for large liquid argon TPCs, those that have been successfully operated, MicroBooNE and ProtoDUNE, and those designed or under construction, such as SBND and DUNE first and second 10 kton modules. The high performance achieved with MicroBooNE and ProtoDUNE – a high signal-to-noise ratio combined with high stability of response – is mainly due to the integral approach to design and construction of sensing electrodes with cold readout electronics in a modular approach with the cryostat signal feed-throughs incorporating warm interface electronics into a Faraday cage with the cryostat. The integral concept is described in some detail in this paper.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2020

Integrated Circuit Design for Radiation-Hardened Charge-Sensitive Amplifier Survived up to 2 Mrad

According to the continuous development of metal-oxide semiconductor (MOS) fabrication technology, transistors have naturally become more radiation-tolerant through steadily decreasing gate-oxide thickness, increasing the tunneling probability between gate-oxide and channel. Unfortunately, despite this radiation-hardened property of developed transistors, the field of nuclear power plants (NPPs) requires even higher radiation hardness levels. Particularly, total ionizing dose (TID) of approximately 1 Mrad could be required for readout circuitry under severe accident conditions with 100 Mrad around a reactor in-core required. In harsh radiating environments such as NPPs, sensors such as micro-pocket-fission detectors (MPFD) would be a promising technology to be operated for detecting neutrons in reactor cores. For those sensors, readout circuits should be fundamentally placed close to sensing devices for minimizing signal interferences and white noise. Therefore, radiation hardening ability is necessary for the circuits under high radiation environments. This paper presents various integrated circuit designs for a radiation hardened charge-sensitive amplifier (CSA) by using SiGe 130 nm and Si 180 nm fabrication processes with different channel widths and transistor types of complementary metal-oxide-semiconductor (CMOS) and bipolar CMOS (BiCMOS). These circuits were tested under γ–ray environment with Cobalt-60 of high level activity: 490 kCi. The experiment results indicate amplitude degradation of 2.85%–34.3%, fall time increase of 201–1730 ns, as well as a signal-to-noise ratio (SNR) of 0.07–11.6 dB decrease with irradiation dose increase. These results can provide design guidelines for radiation hardening operational amplifiers in terms of transistor sizes and structures.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗