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N-consecutive-phase encoder (NCPE) is conceptual encoder for generating alphabet of N consecutive full-response continuous-phase-modulation (CPM) signals. Enables use of binary preencoder of higher rate than used with simple continuous-phase encoder (CPE). NCPE makes possible to achieve power efficiencies and bandwidth efficiencies greater than conventional trellis coders with continuous-phase frequency-shift keying (CPFSK).
During the period June 1, 1986 through November 30, 1986, progress was made in the following areas: undetected error probability and throughput analysis of a concatenated coding scheme; capacity and cutoff rate analysis of concatenated codes; concatenated codes using bandwidth efficient trellis inner codes; bounds on the minimum free Euclidean distance of bandwidth efficient trellis codes; and construction of multidimensional bandwidth efficient trellis codes for use as inner codes in a concatenated coding system.
Progress made in the following areas is discussed: concatenated codes using bandwidth efficient Trellis inner codes; bounds on the minimum free Euclidean distance of bandwidth efficient Trellis inner codes; performance analysis of bandwidth Trellis codes on channels with phase jitter; construction of bandwidth efficient Trellis codes; and parity retransmission hybrid ARQ using convolutional codes.
Ford Aerospace has developed a proof-of-concept satellite 8 phase shift keying (PSK) modulation and coding system operating in the Time Division Multiple Access (TDMA) mode at a data range of 200 Mbps using rate 5/6 forward error correction coding. The 80 Msps 8 PSK modem was developed in a mostly digital form and is amenable to an ASIC realization in the next phase of development. The codec was developed as a paper design only. The power efficiency goal was to be within 2 dB of theoretical at a bit error rate (BER) of 5x10(exp 7) while the measured implementation loss was 4.5 dB. The bandwidth efficiency goal was 2 bits/sec/Hz while the realized bandwidth efficiency was 1.8 bits/sec/Hz. The burst format used a preamble of only 40 8 PSK symbol times including 32 symbols of all zeros and an eight symbol unique word. The modem and associated special test equipment (STE) were fabricated mostly on a specially designed stitch-weld board although a few of the highest rate circuits were built on printed circuit cards. All the digital circuits were ECL to support the clock rates of from 80 MHz to 360 MHz. The transmitter and receiver matched filters were square-root Nyquist bandpass filters realized at the 3.37 GHz i.f. The modem operated as a coherent system although no analog phase locked (PLL) loop was employed. Within the budgetary constraints of the program, the approach to the demodulator has been proven and is eligible to proceed to the next phase of development of a satellite demodulator engineering model. This would entail the development of an ASIC version of the digital portion of the demodulator, and MMIC version of the quadrature detector, and SAW Nyquist filters to realize the bandwidth efficiency.
Research activities related to error control techniques for satellite and space communication are reported. Specific areas of research include: coding gains for bandwidth efficient codes, hardware implementation of a bandwidth efficient coding scheme for the Hubble Space Telescope, construction of long trellis codes for use with sequential decoding, performance analysis of multilevel trellis codes, and M-algorithm decoding of trellis codes. Each topic is discussed in a corresponding paper that appears in the appendices.
As the National Aeronautics and Space Administration moves into the 21st century with programs like Space Station Freedom, a manned mission to Mars, and the new Landsat mission, transmission demands on the Tracking and Data Relay Satellite System (TDRSS) will very likely exceed the available bandwidth. The Manual Lujan, Jr. Center for Space Telemetering and Telecommunications Systems (CSTTS) at New Mexico State University (NMSU) is studying techniques for increasing the data rate capabilities of TDRSS. These techniques include the use of advanced bandwidth efficient modulation formats to increase the data rate that can be sustained in a TDRSS transponder and the use of lossless bandwidth compression of the data to be transmitted to lower the data rate required from the user spacecraft. Based upon current technology the most promising bandwidth efficient modulation technique is Trellis Coded Modulation (TCM) operating with Octal Phase shift Keying (8PSK). Trellis Coded Modulation coding with 8PSK carrier modulation has the capability to increase the data rate which can be transmitted through the TDRSS spacecraft by a factor of 2 to 2.5 times that available with todays coded QPSK systems with only a small penalty in link performance relative to the existing systems. However, before NASA can safely employ TCM coding it is necessary to prove that this complex format can perform on the real TDRSS link as it does in labs and simulation studies. This proof-of-concept test over a live satellite channel was the objective of the construction and testing performed under this task of the NMSU NASA grant referenced above. In conjunction with NASA, NMSU's CSTTS has constructed a system to test a new candidate TDRSS modulation scheme, TCM 8PSK, that can enhance the information throughput of the TDRSS spacecraft. The test system for this project which was constructed over a period of 18 months by NMSU consisted of two racks of commercial and univeristy-designed and -built equipment. This project has included modifications of an existing White Sands Ground Terminal (WSGT) High Rate QPSK Demodulator to demodulate 8PSK as well as the construction of other support hardware. Also, two TCM codecs (coder/decoders) have been constructed to implement two levels of bandwidth efficiency. One was designed and built by the research team at NMSU while the other was created by the University of Notre Dame with the University of South Australia. The NMSU codec achieves a 2-to-1 increase in data rate per unit bandwidth with a coding gain relative to QPSK of about 3dB. The Notre Dame/South Australia codec achieves a 2.5-to-1 increase in data rate per unit of occupied bandwidth and a coding gain of about 2dB.
A proof-of-concept demodulator for TDMA applications requiring high total data rates composed of many low data rate users is proposed. High-spectrum efficiency is obtained via a bandwidth efficient combined modulation and coding system, and low TDMA overhead is obtained via a fast acquiring digital phase lock loop. The system employs a data rate of 200 Mb/s with a bit error rate of better than 5 x 10 to the -7th in the presence of adjacent channel interference 20 dB above the weakest user. The 8-PSK modulation combined with the rate 5/6 forward error correction coding results in a bandwidth efficiency of better than 2 bits/second per Hz.
In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing, a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study, which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating, and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these sub-trellises.
In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.
In his research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RNI subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a hi ch data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these sub-trellises.
In his research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second(Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high- speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.
The (64, 40, 8) subcode of the third-order Reed-Muller (RM) code for high-speed satellite communications is proposed. The RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. The progress made toward achieving the goal of implementing a decoder system based upon this code is summarized. The development of the integrated circuit prototype sub-trellis IC, particularly focusing on the design methodology, is addressed.
Currently proposed mobile satellite communications systems require a high degree of flexibility in assignment of spectral capacity to different geographic locations. Conventionally this results in poor spectral efficiency which may be overcome by the use of bandwidth switchable filtering. Surface acoustic wave (SAW) technology makes it possible to provide banks of filters whose responses may be contiguously combined to form variable bandwidth filters with constant amplitude and phase responses across the entire band. The high selectivity possible with SAW filters, combined with the variable bandwidth capability, makes it possible to achieve spectral efficiencies over the allocated bandwidths of greater than 90 percent, while retaining full system flexibility. Bandwidth switchable SAW filtering (BSSF) achieves these gains with a negligible increase in hardware complexity.
Satellite-based telecommunication services are challenged by the need to generate down-link power levels adequate to support high quality (BER approx. equals 10(exp 12)) links required for modem broadband data services. Bandwidth-efficient Nyquist signaling, using low values of excess bandwidth (alpha), can exhibit large peak-to-average-power ratio (PAPR) values. High PAPR values necessitate high-power amplifier (HPA) backoff greater than the PAPR, resulting in unacceptably low HPA efficiency. Given the high cost of on-board prime power, this inefficiency represents both an economical burden, and a constraint on the rates and quality of data services supportable from satellite platforms. Constant-envelope signals offer improved power-efficiency, but only by imposing a severe bandwidth-efficiency penalty. This paper describes a radiation- hardened modulator which can improve satellite-based broadband data services by combining the bandwidth-efficiency of low-alpha Nyquist signals with high power-efficiency (negligible HPA backoff).
This report presents a comparative study on Enhanced Feher's Quadrature Phase Shift Keying (EFQPSK) and Constrained Envelope Root Nyquist (CERN) techniques. These two techniques have been developed in recent times to provide high spectral and power efficiencies under nonlinear amplifier environment. The purpose of this study is to gain insights into these techniques and to help system planners and designers with an appropriate set of guidelines for using these techniques. The comparative study presented in this report relies on effective simulation models and procedures. Therefore, a significant part of this report is devoted to understanding the mathematical and simulation models of the techniques and their set-up procedures. In particular, mathematical models of EFQPSK and CERN, effects of the sampling rate in discrete time signal representation, and modeling of nonlinear amplifiers and predistorters have been considered in detail. The results of this study show that both EFQPSK and CERN signals provide spectrally efficient communications compared to filtered conventional linear modulation techniques when a nonlinear power amplifier is used. However, there are important differences. The spectral efficiency of CERN signals, with a small amount of input backoff, is significantly better than that of EFQPSK signals if the nonlinear amplifier is an ideal clipper. However, to achieve such spectral efficiencies with a practical nonlinear amplifier, CERN processing requires a predistorter which effectively translates the amplifier's characteristics close to those of an ideal clipper. Thus, the spectral performance of CERN signals strongly depends on the predistorter. EFQPSK signals, on the other hand, do not need such predistorters since their spectra are almost unaffected by the nonlinear amplifier, Ibis report discusses several receiver structures for EFQPSK signals. It is observed that optimal receiver structures can be realized for both coded and uncoded EFQPSK signals with not too much increase in computational complexity. When a nonlinear amplifier is used, the bit error rate (BER) performance of the CERN signals with a matched filter receiver is found to be more than one decibel (dB) worse compared to the bit error performance of EFQPSK signals. Although channel coding is found to provide BER performance improvement for both EFQPSK and CERN signals, the performance of EFQPSK signals remains better than that of CERN. Optimal receiver structures for CERN signals with nonlinear equalization is left as a possible future work. Based on the numerical results, it is concluded that, in nonlinear channels, CERN processing leads towards better bandwidth efficiency with a compromise in power efficiency. Hence for bandwidth efficient communications needs, CERN is a good solution provided effective adaptive predistorters can be realized. On the other hand, EFQPSK signals provide a good power efficient solution with a compromise in band width efficiency.
Space agencies are under pressure to utilize better bandwidth-efficient communication methods due to the actual allocated frequency bands becoming more congested. Also budget reductions is another problem that the space agencies must deal with. This budget constraint results in simpler spacecraft carrying less communication capabilities and also the reduction in staff to capture data in the earth stations. It is then imperative that the most bandwidth efficient communication methods be utilized. This thesis presents a study of 8-ary Phase Shift Keying (8PSK) modulation with respect to bandwidth, power efficiency, spurious emissions and interference susceptibility over a non-linear satellite channel.
Four probe antennas transfer signals from waveguide to microstrip lines. The probes not only provide broadband impedance matching, but also thermally isolate waveguide and detector. In addition, we developed a new photonic waveguide choke joint design, with four-fold symmetry, to suppress power leakage at the interface. We have developed facilities to test superconducting circuit elements using a cryogenic microwave probe station, and more complete systems in waveguide. We used the ring resonator shown below to measure a dielectric loss tangent < 7x10(exp -4) over 10 - 45 GHz. We have combined component simulations to predict the overall coupling from waveguide modes to bolometers. The result below shows the planar circuit and waveguide interface can utilize the high beam symmetry of HE11 circular feedhorns with > 99% coupling efficiency over 30% fractional bandwidth.
In the late seventies and early eighties a technique known as Trellis Coded Modulation (TCM) was developed for providing spectrally efficient error correction coding. Instead of adding redundant information in the form of parity bits, redundancy is added at the modulation stage thereby increasing bandwidth efficiency. A digital communications system can be designed to use bandwidth-efficient multilevel/phase modulation such as Amplitude Shift Keying (ASK), Phase Shift Keying (PSK), Differential Phase Shift Keying (DPSK) or Quadrature Amplitude Modulation (QAM). Performance gain can be achieved by increasing the number of signals over the corresponding uncoded system to compensate for the redundancy introduced by the code. A considerable amount of research and development has been devoted toward developing good TCM codes for severely bandlimited applications. More recently, the use of TCM for satellite and deep space communications applications has received increased attention. This report describes the general approach of using a concatenated coding scheme that features TCM and RS coding. Results have indicated that substantial (6-10 dB) performance gains can be achieved with this approach with comparatively little bandwidth expansion. Since all of the bandwidth expansion is due to the RS code we see that TCM based concatenated coding results in roughly 10-50% bandwidth expansion compared to 70-150% expansion for similar concatenated scheme which use convolution code. We stress that combined coding and modulation optimization is important for achieving performance gains while maintaining spectral efficiency.