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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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NASA NTRS1972

Inexpensive programmable clock for a 12-bit computer

An inexpensive programmable clock was built for a digital PDP-12 computer. The instruction list includes skip on flag; clear the flag, clear the clock, and stop the clock; and preset the counter with the contents of the accumulator and start the clock. The clock counts at a rate determined by an external oscillator and causes an interrupt and sets a flag when a 12-bit overflow occurs. An overflow can occur after 1 to 4096 counts. The clock can be built for a total parts cost of less than $100 including power supply and I/O connector. Slight modification can be made to permit its use on larger machines (16 bit, 24 bit, etc.) and logic level shifting can be made to make it compatible with any computer.

Vrancik, J. E.↗

NASA NTRS1972

Conceptual design and feasibility evaluation model of a 10 to the 8th power bit oligatomic mass memory. Volume 1: Conceptual design

The oligatomic (mirror) thin film memory technology is a suitable candidate for general purpose spaceborne applications in the post-1975 time frame. Capacities of around 10 to the 8th power bits can be reliably implemented with systems designed around a 335 million bit module. The recommended mode was determined following an investigation of implementation sizes ranging from an 8,000,000 to 100,000,000 bits per module. Cost, power, weight, volume, reliability, maintainability and speed were investigated. The memory includes random access, NDRO, SEC-DED, nonvolatility, and dual interface characteristics. The applications most suitable for the technology are those involving a large capacity with high speed (no latency), nonvolatility, and random accessing.

Recksiedler, A. L.↗

NASA NTRS1974

Carrier tracking, bit synchronization, and coding for S-band communications links

This paper presents the results of a study of the performance of Viterbi-decoded convolutional codes in the presence of nonideal carrier tracking and bit synchronization. A constraint length 7, rate 1/3 convolutional code and parameters suitable for the space shuttle coded communications links are used. Mathematical models are developed and theoretical and simulation results are obtained to determine the tracking and acquisition performance of the system. It is shown that the combined energy-to-noise degradation due to nonideal carrier tracking and bit synchronization over that required for the ideal tracking case can be held to less than 1.5 dB and that combined carrier tracking and bit timing can be acquired in only a few seconds for the parameters and operating ranges of the space shuttle coded communications links.

Odenwalder, J. P.↗

NASA NTRS1979

Digital PSK to BiO-L demodulator for 2 sup nx(bit rate) carrier

A phase shift key (PSK) to BiO-L demodulator which uses standard digital integrated circuits is discussed. The demodulator produces NRZ-L, bit clock, and BiO-L outputs from digital PSK input signals for which the carrier is a 2 to the Nth multiple of the bit rate. Various bit and carrier rates which are accommodated by changing various component values within the demodulator are described. The use of the unit for sinusoidal inputs as well as digital inputs is discussed.

Shull, T. A.↗

NASA NTRS1979

The 10 to the 8th power bit solid state spacecraft data recorder

The results are summarized of a program to demonstrate the feasibility of Bubble Domain Memory Technology as a mass memory medium for spacecraft applications. The design, fabrication and test of a partially populated 10 to the 8th power Bit Data Recorder using 100 Kbit serial bubble memory chips is described. Design tradeoffs, design approach and performance are discussed. This effort resulted in a 10 to the 8th power bit recorder with a volume of 858.6 cu in and a weight of 47.2 pounds. The recorder is plug reconfigurable, having the capability of operating as one, two or four independent serial channel recorders or as a single sixteen bit byte parallel input recorder. Data rates up to 1.2 Mb/s in a serial mode and 2.4 Mb/s in a parallel mode may be supported. Fabrication and test of the recorder demonstrated the basic feasibility of Bubble Domain Memory technology for such applications. Test results indicate the need for improvement in memory element operating temperature range and detector performance.

Murray, G. W.↗

NASA NTRS1981

A bit transition density encoder for the Space Shuttle 2 MHz data channel

As a result of several unique factors, the 2 MHz data channel which carries science data from the various experiments aboard the Space Shuttle through the Tracking and Data Relay Satellite System (TDRSS) lacks sufficient bit transition density to satisfy the bit synchronizer requirements at the ground station. It is noted that six encoding techniques were examined, and all but one, a PN cover sequence (Reset Bit Scrambler) were dismissed because of incompatibility with system constraints. The rationale behind the particular PN sequence chosen, the way it was truncated, and the new sequence properties are presented. The properties of the raw data stream are analyzed, as are the encoded sequence properties, including transition density. Diagrams of the encoder and decoder are included.

Schoggen, W. O.↗

NASA NTRS1981

A study of high density bit transition requirements versus the effects on BCH error correcting coding

Several methods for increasing bit transition densities in a data stream are summarized, discussed in detail, and compared against constraints imposed by the 2 MHz data link of the space shuttle high rate multiplexer unit. These methods include use of alternate pulse code modulation waveforms, data stream modification by insertion, alternate bit inversion, differential encoding, error encoding, and use of bit scramblers. The psuedo-random cover sequence generator was chosen for application to the 2 MHz data link of the space shuttle high rate multiplexer unit. This method is fully analyzed and a design implementation proposed.

Ingels, F.↗

NASA NTRS1981

Bit error rate performance of Image Processing Facility high density tape recorders

The Image Processing Facility at the NASA/Goddard Space Flight Center uses High Density Tape Recorders (HDTR's) to transfer high volume image data and ancillary information from one system to another. For ancillary information, it is required that very low bit error rates (BER's) accompany the transfers. The facility processes about 10 to the 11th bits of image data per day from many sensors, involving 15 independent processing systems requiring the use of HDTR's. When acquired, the 16 HDTR's offered state-of-the-art performance of 1 x 10 to the -6th BER as specified. The BER requirement was later upgraded in two steps: (1) incorporating data randomizing circuitry to yield a BER of 2 x 10 to the -7th and (2) further modifying to include a bit error correction capability to attain a BER of 2 x 10 to the -9th. The total improvement factor was 500 to 1. Attention is given here to the background, technical approach, and final results of these modifications. Also discussed are the format of the data recorded by the HDTR, the magnetic tape format, the magnetic tape dropout characteristics as experienced in the Image Processing Facility, the head life history, and the reliability of the HDTR's.

Heffner, P.↗

NASA NTRS1989

Using Bit Errors To Diagnose Fiber-Optic Links

Technique for diagnosis of fiber-optic digital communication link in local-area network of computers based on measurement of bit-error rates. Variable optical attenuator inserted in optical fiber to vary power of received signal. Bit-error rate depends on ratio of peak signal power to root-mean-square noise in receiver. For optimum measurements, one selects bit-error rate between 10 to negative 8th power and 10 to negative 4th power. Greater rates result in low accuracy in determination of signal-to-noise ratios, while lesser rates require impractically long measurement times.

Bergman, L. A.↗

NASA NTRS1988

Efficient use of bit planes in the generation of motion stimuli

The production of animated motion sequences on computer-controlled display systems presents a technical problem because large images cannot be transferred from disk storage to image memory at conventional frame rates. A technique is described in which a single base image can be used to generate a broad class of motion stimuli without the need for such memory transfers. This technique was applied to the generation of drifting sine-wave gratings (and by extension, sine wave plaids). For each drifting grating, sine and cosine spatial phase components are first reduced to 1 bit/pixel using a digital halftoning technique. The resulting pairs of 1-bit images are then loaded into pairs of bit planes of the display memory. To animate the patterns, the display hardware's color lookup table is modified on a frame-by-frame basis; for each frame the lookup table is set to display a weighted sum of the spatial sine and cosine phase components. Because the contrasts and temporal frequencies of the various components are mutually independent in each frame, the sine and cosine components can be counterphase modulated in temporal quadrature, yielding a single drifting grating. Using additional bit planes, multiple drifting gratings can be combined to form sine-wave plaid patterns. A large number of resultant plaid motions can be produced from a single image file because the temporal frequencies of all the components can be varied independently. For a graphics device having 8 bits/pixel, up to four drifting gratings may be combined, each having independently variable contrast and speed.

Mulligan, Jeffrey B.↗

NASA NTRS1989

Single chip fixed frequency bit synchronizer

A single chip, fixed frequency suboptimum bit synchronizer design which was implemented utilizing a programmable logic device is described. The bit synchronizer is modeled after a digital transition tracking loop for symbol estimation and employs a first-order incremental phase modulator for closed-loop symbol synchronization. The BER and tracking performance is modeled and compared to optimum designs. The bit synchronizer was developed for the Space Shuttle.

Butler, Madeline J.↗

NASA NTRS1991

The simulation of composite color imagery on 8-bit display devices

A transformation method has been developed that is very successful in simulating composite imagery and shows that, in general, 8-bit simulated composite images are almost indistinguishable from true composite imagery. This technique was designed to facilitate the display and interpretation of composite satellite imagery on display devices with only 256 displayable colors. The method is suitable for the combination of two 8-bit images into a single 8-bit composite image.

Thomason, Larry W.↗

NASA NTRS1992

Least reliable bits coding (LRBC) for high data rate satellite communications

LRBC, a bandwidth efficient multilevel/multistage block-coded modulation technique, is analyzed. LRBC uses simple multilevel component codes that provide increased error protection on increasingly unreliable modulated bits in order to maintain an overall high code rate that increases spectral efficiency. Soft-decision multistage decoding is used to make decisions on unprotected bits through corrections made on more protected bits. Analytical expressions and tight performance bounds are used to show that LRBC can achieve increased spectral efficiency and maintain equivalent or better power efficiency compared to that of BPSK. The relative simplicity of Galois field algebra vs the Viterbi algorithm and the availability of high-speed commercial VLSI for block codes indicates that LRBC using block codes is a desirable method for high data rate implementations.

Vanderaar, Mark↗

NASA NTRS1992

Applying an 8-bit multispectral color-composite image simulation technique to operational real-time AVHRR data

The Geophysics Directorate's 8-bit multispectral color-composite image display technique has been installed on the Satellite Data Processing System at the German Military Geophysical Office in Traben-Trarbach, Germany. The technique simulates 24-bit full-color composites on 8-bit color workstations, combining image data from the NOAA multispectral Advanced Very High Resolution Radiometer. The real-time application of this technique to operational satellite data is discussed.

Klaes, K. D.↗

NASA NTRS1992

Bit-parallel arithmetic in a massively-parallel associative processor

A simple but powerful new architecture based on a classical associative processor model is presented. Algorithms for performing the four basic arithmetic operations both for integer and floating point operands are described. For m-bit operands, the proposed architecture makes it possible to execute complex operations in O(m) cycles as opposed to O(m exp 2) for bit-serial machines. A word-parallel, bit-parallel, massively-parallel computing system can be constructed using this architecture with VLSI technology. The operation of this system is demonstrated for the fast Fourier transform and matrix multiplication.

Scherson, Isaac D.↗

NASA NTRS1990

A bit serial sequential circuit

Normally a sequential circuit with n state variables consists of n unique hardware realizations, one for each state variable. All variables are processed in parallel. This paper introduces a new sequential circuit architecture that allows the state variables to be realized in a serial manner using only one next state logic circuit. The action of processing the state variables in a serial manner has never been addressed before. This paper presents a general design procedure for circuit construction and initialization. Utilizing pass transistors to form the combinational next state forming logic in synchronous sequential machines, a bit serial state machine can be realized with a single NMOS pass transistor network connected to shift registers. The bit serial state machine occupies less area than other realizations which perform parallel operations. Moreover, the logical circuit of the bit serial state machine can be modified by simply changing the circuit input matrix to develop an adaptive state machine.

Hu, S.↗

NASA NTRS1984

NSC 800, 8-bit CMOS microprocessor

The NSC 800 is an 8-bit CMOS microprocessor manufactured by National Semiconductor Corp., Santa Clara, California. The 8-bit microprocessor chip with 40-pad pin-terminals has eight address buffers (A8-A15), eight data address -- I/O buffers (AD(sub 0)-AD(sub 7)), six interrupt controls and sixteen timing controls with a chip clock generator and an 8-bit dynamic RAM refresh circuit. The 22 internal registers have the capability of addressing 64K bytes of memory and 256 I/O devices. The chip is fabricated on N-type (100) silicon using self-aligned polysilicon gates and local oxidation process technology. The chip interconnect consists of four levels: Aluminum, Polysi 2, Polysi 1, and P(+) and N(+) diffusions. The four levels, except for contact interface, are isolated by interlevel oxide. The chip is packaged in a 40-pin dual-in-line (DIP), side brazed, hermetically sealed, ceramic package with a metal lid. The operating voltage for the device is 5 V. It is available in three operating temperature ranges: 0 to +70 C, -40 to +85 C, and -55 to +125 C. Two devices were submitted for product evaluation by F. Stott, MTS, JPL Microprocessor Specialist. The devices were pencil-marked and photographed for identification.

Suszko, S. F.↗

NASA NTRS1998

Characterization of a 16-bit Digitizer System for Lidar Data Acquisition

A new 16-bit 6-MHz compact, lightweight waveform digitizer module has been tested using actual 300-nm lidar atmospheric returns. The noise level of this digitizer was tested and found to be substantially below the ozone number density to be measured. The digitizer is inexpensive and compact enough to be deployed in UAV aircraft and spacecraft environments. With 16-bit digitizers a resolution of 0.046 mV/step can be achieved, substantially improving resolution over 12-bit systems. This digitizer will find widespread use in future DIAL receiver systems.

Williamson, Cynthia K.↗