SEARCH · Search NASA

Results for “chip”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

SourceResearch connectionFrom yearThrough year

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 55 records · Page 3

All sources NASA NTRS DOE OSTI

DOE OSTI2015

Consumption study and identification of methyl salicylate in spicy cassava chips

Spicy cassava chips is a popular snack. However, some news in electronic media reported addition of balsam which is a banned food additives in that product to give extra spicy flavor. This study aimed to determine ITB students’ pattern of consumption, health problems caused by spicy chips consumption, and knowledge about illicit use of food additives in that product, and identify the main content of balsam namely methyl salicylate in 10 samples of spicy cassava chips taken from inside and outside about ITB campus. A total of 300 questionnaires distributed to ITB students then data processing was performed. Spicy cassava chips sample macerated in 50 mL of methanol for 24 hours at room temperature, filtered and analyzed using gas chromatography capillary column with OV-1, nitrogen carrier gas and flame ionization detector. Based on questionnaires, 292 (97%) of 300 respondents had consumed spicy chips. A total of 247 (85%) from 292 respondents spicy chips consumed less than 3 times a week. A total of 195 respondents (67%) had experienced health problems after eating spicy chips. There were 137 (47%) of the 292 respondents who knew about the illicit addition of food additives into spicy chips; only 35 respondents (12%) who knew about balsam’s addition. There were 126 respondents (43%) who did not pay attention to their health because they will keep eating spicy chips despite the addition of banned food additives. Through the verification of the standard addition method in gas chromatography system with a hydrogen pressure of 1.5 bar, injector temperature 200 °C, detector temperature 230 °C, oven temperature 60 °C for 2 minutes and then increased to 230 °C with rate 6 °C/menit; linearity, limit of detection, limit of quantitation, accuracy, precision, and specificity parameters met the acceptance limits. From 10 spicy cassava chips samples which were analyzed, they did not reveal any content of methyl salicylate. Methyl salicylate contained in the positive control was 1.273 mg/mL.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗

DOE OSTI2018

Shifting Sands: Modulating Interactions and Outputs of the CHIP‐Hsp70/HOP‐Hsp70 Protein Quality Control Complexes

The 70‐kilodalton heat shock protein (Hsp70) interacts with tetratricopeptide repeat (TPR) domains of CHIP (C‐terminus of Hsp70 Interacting Protein) and HOP (Hsp Organizing Protein) using a two‐carboxylate clamp binding mechanism. Differential affinity for the TPR domains of CHIP and HOP are achieved through interactions with the six residues preceding the carboxy‐terminal Asp 641 of Hsp70. In particular, phosphorylation of Hsp70 Thr 636 produces a dramatic swing in binding affinities that shift preferential formation of CHIP/Hsp70 complexes to preferential formation of HOP/Hsp70 complexes. Given that CHIP‐Hsp70 complexes promote ubiquitin‐mediated degradation of Hsp70‐chaperoned clients while HOP‐Hsp70 complexes promote refolding of Hsp70‐chaperoned clients, phosphorylation of Hsp70 Thr 636 acts as a switch that directs the output and function of cellular protein quality control. Herein, through biophysical assays and new structures of CHIP‐Hsp70 and Hop‐Hsp70 we identify the molecular mechanism that enables phosphorylation‐driven switching that directs interactions within the CHIP‐Hsp70/HOP‐Hsp70 protein quality control complexes. We also present a structure‐guided mutation of Hsp70 that bypasses Thr 636 phosphorylation‐driven switching by recovering affinity of CHIP for phosphorylated Hsp70, thereby redirecting Hsp70 to preferentially bind to CHIP. This structure‐guided mutation corrects a binding defect present in wild type CHIP and provides a system for studying the effect of shifting output of the CHIP‐Hsp70/HOP‐Hsp70 protein quality control complexes toward chaperoned ubiquitination via the CHIP‐Hsp70 complex. Support or Funding Information The authors acknowledge financial support from the US National Science Foundation (Award No. MCB 1552113 to RCP), the American Heart Association (Award No. 16SDG26960000 to RCP), the Burroughs Wellcome Fund (Award No. 1014031 to RCP), and institutional support from Miami University through the Robert H. and Nancy J. Blayney Professorship (to RCP). The Advanced Light Source is supported by the US Department of Energy under contract number DE‐AC03‐76SF00098 at Lawrence Berkeley National Laboratory.

Page, Richard C.↗

NASA NTRS2010

Advanced Flip Chips in Extreme Temperature Environments

The use of underfill materials is necessary with flip-chip interconnect technology to redistribute stresses due to mismatching coefficients of thermal expansion (CTEs) between dissimilar materials in the overall assembly. Underfills are formulated using organic polymers and possibly inorganic filler materials. There are a few ways to apply the underfills with flip-chip technology. Traditional capillary-flow underfill materials now possess high flow speed and reduced time to cure, but they still require additional processing steps beyond the typical surface-mount technology (SMT) assembly process. Studies were conducted using underfills in a temperature range of -190 to 85 C, which resulted in an increase of reliability by one to two orders of magnitude. Thermal shock of the flip-chip test articles was designed to induce failures at the interconnect sites (-40 to 100 C). The study on the reliability of flip chips using underfills in the extreme temperature region is of significant value for space applications. This technology is considered as an enabling technology for future space missions. Flip-chip interconnect technology is an advanced electrical interconnection approach where the silicon die or chip is electrically connected, face down, to the substrate by reflowing solder bumps on area-array metallized terminals on the die to matching footprints of solder-wettable pads on the chosen substrate. This advanced flip-chip interconnect technology will significantly improve the performance of high-speed systems, productivity enhancement over manual wire bonding, self-alignment during die joining, low lead inductances, and reduced need for attachment of precious metals. The use of commercially developed no-flow fluxing underfills provides a means of reducing the processing steps employed in the traditional capillary flow methods to enhance SMT compatibility. Reliability of flip chips may be significantly increased by matching/tailoring the CTEs of the substrate material and the silicon die or chip, and also the underfill materials. Advanced packaging interconnects technology such as flip-chip interconnect test boards have been subjected to various extreme temperature ranges that cover military specifications and extreme Mars and asteroid environments. The eventual goal of each process step and the entire process is to produce components with 100 percent interconnect and satisfy the reliability requirements. Underfill materials, in general, may possibly meet demanding end use requirements such as low warpage, low stress, fine pitch, high reliability, and high adhesion.

Ramesham, Rajeshuni↗

DOE OSTI2023

Microfluidic systems, pumps, valves, fluidic chips thereof, and applications of same

Microfluidic systems, pumps, valves and applications of the same are provided. The microfluidic system may be a pump or a valve having a fluidic chip and an actuator controlling the opening and closing of the fluidic channel in the fluidic chip. The actuator may be disposed to tilt from the fluidic chip, forming a tilted-rotor peristaltic pump. Alternatively, the actuator may be a rolling ball actuator, and different fluidic chips may be used in different applications. For example, the fluidic chip may be a spiral pump chip having spiral channels, a rotary peristaltic pump chip having multiple output channels, or a multi-port valve chip having one port interconnected with multiple different ports. An analytical valve chip may switchably interconnect bioreactor and rinse/calibration input channels to sensor and waste output channels. The actuator of a random-access valve can move from one valve position to another without opening or closing intermediate ones.

Reiserer, Ronald S.↗

DOE OSTI2023

Microfluidic systems, pumps, valves, fluidic chips thereof, and applications of same

Reiserer, Ronald S.↗

DOE OSTI2016

Numerical investigation of thermal performance of a water-cooled mini-channel heat sink for different chip arrangement

Heat transfer from electronic chip is always challenging and very crucial for electronic industry. Electronic chips are assembled in various manners according to the design conditions and limitationsand thus the influence of chip assembly on the overall thermal performance needs to be understand for the efficient design of electronic cooling system. Due to shrinkage of the dimension of channel and continuous increment of thermal load, conventional heat extraction techniques sometimes become inadequate. Due to high surface area to volume ratio, mini-channel have the natural advantage to enhance convective heat transfer and thus to play a vital role in the advanced heat transfer devices with limited surface area and high heat flux. In this paper, a water cooled mini-channel heat sink was considered for electronic chip cooling and five different chip arrangements were designed and studied, namely: the diagonal arrangement, parallel arrangement, stacked arrangement, longitudinal arrangement and sandwiched arrangement. Temperature distribution on the chip surfaces was presented and the thermal performance of the heat sink in terms of overall thermal resistance was also compared. It is found that the sandwiched arrangement of chip provides better thermal performance compared to conventional in line chip arrangement.

42 ENGINEERING↗

DOE OSTI2019

Simple non-galvanic flip-chip integration method for hybrid quantum systems

A challenge faced by experimenters exploring hybrid quantum systems is how to integrate and interconnect different materials and different substrates in a quantum-coherent fashion. Here, we present a simple and inexpensive flip-chip bonding process, suitable for integrating hybrid quantum devices on chips from different substrates. The process only requires equipment and materials used routinely for contact photolithography, and it is possible to undo the bonding and reuse the chips. The technique requires minimal compressive force, so it is compatible with a wide range of different substrates. Unlike indium-based bonding, this process does not establish a galvanic connection between the two chips, but as we show, in some situations this is not necessary. We demonstrate the technique using lithographically patterned quarter-wave coplanar waveguide resonators, fabricated on one chip, and couple these inductively to a transmission line patterned lithographically on a separate chip. The two chips have a vertical interchip gap of about 7 μm, and we can repeatedly achieve lateral alignments of better than 2μm. We measure electromagnetic resonances with low-power (similar to ~1 photon) internal quality factors Q i around 5 x 10 5 , comparable to single-chip performances, with as-designed coupling quality factors Q c ranging from 2 x 10 2 to 5 x 10 5 .

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

NASA NTRS1993

Ignition propagation and heat effects of propellant chips embedded in castable inhibitor using a laser flux test bomb

A castable inhibitor is applied to the aft face of the Space Shuttle Redesigned Solid Rocket Motor (RSRM) forward segment propellant grain to control propellant surface burn area. During fabrication, the propellant surface is trimmed prior to the inhibitor application. This produces a potential for small propellant chips to remain undetected on the propellant surface and contaminate the inhibitor during application. The concern was that undetected propellant chips in the inhibitor might provide a fuse path for premature propellant ignition underneath the inhibitor. To evaluate the fuse path potential, testing was performed on inhibitor samples with embedded propellant. The internal motor environment was simulated with a calibrated CO2 laser beam directed onto a sample which was placed in a 4100 kPa (600 psi) nitrogen pressurized bomb (laser bomb). The testing showed definitive results pertaining to fuse path formation. Embedded propellant chips did not autoignite until the receding heat affected inhibitor surface reached, or passed, the propellant chip. Samples with embedded propellant chips in alignment did not propagate ignition from one chip to another with separation distances as small as 0.010 cm(0.004 inc) and some as little as 0.0051 cm (0.002 in). Propellant chips with volumes approximately less than 0.025 cu cm (0.0015 cu in) (which did not propagate ignition) did not increase the inhibitor material decomposition depth more than the resulting void cavity of the burned out propellant chip. In addition, the depth of this void cavity did not increase until it was overtaken by the surrounding material decomposition depth. This was due, in part, to the retention of the protective inhibitor char layer. Samples with embedded propellant strings, whose thicknesses were below 0.023 cm (0.009 in), did not propagate ignition. Propellant string thicknesses above 0.038 cm (0.015 in) did propagate ignition. Test sample char and heat affected layer measurements and observations compared well with those from the Space Shuttle Solid Rocket Motor (SRM) Technical Evaluation Motor no. 9(TEM-9).

Bolton, Douglas E., Jr.↗

NASA NTRS2003

Experiences with Lab-on-a-chip Technology in Support of NASA Supported Research

Under the auspices of the Microgravity Sciences and Application Department at Marshall Space Flight Center, we have custom designed and fabricated a lab-on-a-chip (LOC) device, along with Caliper Technologies, for macromolecular crystal growth. The chip has been designed to deliver specified proportions of up-to five various constituents to one of two growth wells (on-chip) for crystal growth. To date, we have grown crystals of thaumatin, glucose isomerase and appoferitin on the chip. The LOC approach offered many advantages that rendered it highly suitable for space based hardware to perform crystal growth on the International Space Station. The same hardware that was utilized for the crystal growth investigations, has also been used by researchers at Glenn Research Center to investigate aspects of microfluidic phenomenon associated with two-phase flow. Additionally, our LOCAD (Lab-on-a-chip Application Development) team has lent its support to Johnson Space Center s Modular Assay for Solar System Exploration project. At present, the LOCAD team is working on the design and build of a unique lab-on-a-chip breadboard control unit whose function is not commercially available. The breadboard can be used as a test bed for the development of chip size labs for environmental monitoring, crew health monitoring assays, extended flight pharmacological preparations, and many more areas. This unique control unit will be configured for local use and/or remote operation, via the Internet, by other NASA centers. The lab-on-a-chip control unit is being developed with the primary goal of meeting Agency level strategic goals.

Monaco, Lisa↗

DOE OSTI2015

Ground-referenced single-ended signaling connected graphics processing unit multi-chip module

A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a graphics processing cluster (GPC) chip, and an MCM package configured to include the first processor chip, the GPC chip, and an interconnect circuit. The first processor chip is configured to include a first ground-referenced single-ended signaling interface circuit. A first set of electrical traces fabricated within the MCM package and configured to couple the first single-ended signaling interface circuit to the interconnect circuit. The GPC chip is configured to include a second single-ended signaling interface circuit and to execute shader programs. A second set of electrical traces fabricated within the MCM package and configured to couple the second single-ended signaling interface circuit to the interconnect circuit. In one embodiment, each single-ended signaling interface advantageously implements ground-referenced single-ended signaling.

Dally, William J.↗

DOE OSTI2015

Ground-referenced single-ended signaling connected graphics processing unit multi-chip module

A system of interconnected chips comprising a multi-chip module (MCM) includes a processor chip, a system functions chip, and an MCM package configured to include the processor chip, the system functions chip, and an interconnect circuit. The processor chip is configured to include a first ground-referenced single-ended signaling interface circuit. A first set of electrical traces manufactured within the MCM package and configured to couple the first single-ended signaling interface circuit to the interconnect circuit. The system functions chip is configured to include a second single-ended signaling interface circuit and a host interface. A second set of electrical traces manufactured within the MCM package and configured to couple the host interface to at least one external pin of the MCM package. In one embodiment, each single-ended signaling interface advantageously implements ground-referenced single-ended signaling.

Dally, William J.↗

DOE OSTI2015

How chip size impacts steam pretreatment effectiveness for biological conversion of poplar wood into fermentable sugars

We report that woody biomass is highly recalcitrant to enzymatic sugar release and often requires significant size reduction and severe pretreatments to achieve economically viable sugar yields in biological production of sustainable fuels and chemicals. However, because mechanical size reduction of woody biomass can consume significant amounts of energy, it is desirable to minimize size reduction and instead pretreat larger wood chips prior to biological conversion. To date, however, most laboratory research has been performed on materials that are significantly smaller than applicable in a commercial setting. As a result, there is a limited understanding of the effects that larger biomass particle size has on the effectiveness of steam explosion pretreatment and subsequent enzymatic hydrolysis of wood chips. To address these concerns, novel downscaled analysis and high throughput pretreatment and hydrolysis (HTPH) were applied to examine whether differences exist in the composition and digestibility within a single pretreated wood chip due to heterogeneous pretreatment across its thickness. Heat transfer modeling, Simons’ stain testing, magnetic resonance imaging (MRI), and scanning electron microscopy (SEM) were applied to probe the effects of pretreatment within and between pretreated wood samples to shed light on potential causes of variation, pointing to enzyme accessibility (i.e., pore size) distribution being a key factor dictating enzyme digestibility in these samples. Application of these techniques demonstrated that the effectiveness of pretreatment of Populus tremuloides can vary substantially over the chip thickness at short pretreatment times, resulting in spatial digestibility effects and overall lower sugar yields in subsequent enzymatic hydrolysis. Finally, these results indicate that rapid decompression pretreatments (e.g., steam explosion) that specifically alter accessibility at lower temperature conditions are well suited for larger wood chips due to the non-uniformity in temperature and digestibility profiles that can result from high temperature and short pretreatment times. Furthermore, this study also demonstrated that wood chips were hydrated primarily through the natural pore structure during pretreatment, suggesting that preserving the natural grain and transport systems in wood during storage and chipping processes could likely promote pretreatment efficacy and uniformity.

09 BIOMASS FUELS↗

DOE OSTI2016

Pyrolysis of ground pine chip and ground pellet particles

In addition to particle size, biomass density influences heat and mass transfer rates during the thermal treatment processes. In this research, thermal behaviour of ground pine chip particles and ground pine pellet particles in the range of 0.25–5 mm was investigated. A single particle from ground pellets was almost 3 to 4 times denser than a single particle from ground chips at a similar size and volume of particle. Temperature was ramped up from room temperature (~25 °C) to 600 °C with heating rates of 10, 20, 30, and 50 °C/min. Pellet particles took 25–88 % longer time to dry than the chip particles. Microscopic examination of 3 mm and larger chip particles showed cracks during drying. No cracks were observed for pellet particles. The mass loss due to treatment at temperatures higher than 200 °C was about 80% both for chip and pellet particles. It took 4 min for chip and pellet particles to lose roughly 63% of their dry mass at a heating rate of 50 °C/min. The SEM structural analysis showed enlarged pores and cracks in cell walls of the pyrolyzed wood chips. As a result, these pores were not observed in pyrolyzed pellet particles.

09 BIOMASS FUELS↗

DOE OSTI2018

Correlation between failure and local material property in chopped carbon fiber chip-reinforced sheet molding compound composites under tensile load

To develop further understanding towards the role of a heterogeneous microstructure on tensile crack initiation and failure behavior in chopped carbon fiber chip-reinforced composites, uni-axial tensile tests are performed on coupons cut from compression molded plaque with varying directions. Our experimental results indicate that failure initiation is relevant to the strain localization, and a new criterion with the nominal modulus to predict the failure location is proposed based on the strain analysis. Furthermore, optical microscopic images show that the nominal modulus is determined by the chip orientation distribution. At the area with low nominal modulus, it is found that chips are mostly aligning along directions transverse to loading direction and/or less concentrated, while at the area with high nominal modulus, more chips are aligning to tensile direction. On the basis of failure mechanism analysis, it is concluded that transversely-oriented chips or resin-rich regions are easier for damage initiation, while longitudinally-oriented chips postpone the fracture. Good agreement is found among failure mechanism, strain localization and chip orientation distribution.

36 MATERIALS SCIENCE↗

NASA NTRS1988

Programmable synaptic chip for electronic neural networks

A binary synaptic matrix chip has been developed for electronic neural networks. The matrix chip contains a programmable 32X32 array of 'long channel' NMOSFET binary connection elements implemented in a 3-micron bulk CMOS process. Since the neurons are kept off-chip, the synaptic chip serves as a 'cascadable' building block for a multi-chip synaptic network as large as 512X512 in size. As an alternative to the programmable NMOSFET (long channel) connection elements, tailored thin film resistors are deposited, in series with FET switches, on some CMOS test chips, to obtain the weak synaptic connections. Although deposition and patterning of the resistors require additional processing steps, they promise substantial savings in silicon area. The performance of synaptic chip in a 32-neuron breadboard system in an associative memory test application is discussed.

Moopenn, A.↗

NASA NTRS1992

Design and qualification of the SEU/TD Radiation Monitor chip

This report describes the design, fabrication, and testing of the Single-Event Upset/Total Dose (SEU/TD) Radiation Monitor chip. The Radiation Monitor is scheduled to fly on the Mid-Course Space Experiment Satellite (MSX). The Radiation Monitor chip consists of a custom-designed 4-bit SRAM for heavy ion detection and three MOSFET's for monitoring total dose. In addition the Radiation Monitor chip was tested along with three diagnostic chips: the processor monitor and the reliability and fault chips. These chips revealed the quality of the CMOS fabrication process. The SEU/TD Radiation Monitor chip had an initial functional yield of 94.6 percent. Forty-three (43) SEU SRAM's and 14 Total Dose MOSFET's passed the hermeticity and final electrical tests and were delivered to LL.

Buehler, Martin G.↗

NASA NTRS2001

Chip packaging technique

A hermetically sealed package for at least one semiconductor chip is provided which is formed of a substrate having electrical interconnects thereon to which the semiconductor chips are selectively bonded, and a lid which preferably functions as a heat sink, with a hermetic seal being formed around the chips between the substrate and the heat sink. The substrate is either formed of or includes a layer of a thermoplastic material having low moisture permeability which material is preferably a liquid crystal polymer (LCP) and is a multiaxially oriented LCP material for preferred embodiments. Where the lid is a heat sink, the heat sink is formed of a material having high thermal conductivity and preferably a coefficient of thermal expansion which substantially matches that of the chip. A hermetic bond is formed between the side of each chip opposite that connected to the substrate and the heat sink. The thermal bond between the substrate and the lid/heat sink may be a pinched seal or may be provided, for example by an LCP frame which is hermetically bonded or sealed on one side to the substrate and on the other side to the lid/heat sink. The chips may operate in the RF or microwave bands with suitable interconnects on the substrate and the chips may also include optical components with optical fibers being sealed into the substrate and aligned with corresponding optical components to transmit light in at least one direction. A plurality of packages may be physically and electrically connected together in a stack to form a 3D array.

Jayaraj, Kumaraswamy↗

NASA NTRS2006

Single-Chip T/R Module for 1.2 GHz

A single-chip CMOS-based (complementary-metal-oxide-semiconductorbased) transmit/receive (T/R) module is being developed for L-band radar systems. Previous T/R module implementations required multiple chips employing different technologies (GaAs, Si, and others) combined with off-chip transmission lines and discrete components including circulators. The new design eliminates the bulky circulator, significantly reducing the size and mass of the T/R module. Compared to multi-chip designs, the single-chip CMOS can be implemented with lower cost. These innovations enable cost-effective realization of advanced phased array and synthetic aperture radar systems that require integration of thousands of T/R modules. The circulator is a ferromagnetic device that directs the flow of the RF (radio frequency) power during transmission and reception. During transmission, the circulator delivers the transmitted power from the amplifier to the antenna, while preventing it from damaging the sensitive receiver circuitry. During reception, the circulator directs the energy from the antenna to the low-noise amplifier (LNA) while isolating the output of the power amplifier (PA). In principle, a circulator could be replaced by series transistors acting as electronic switches. However, in practice, the integration of conventional series transistors into a T/R chip introduces significant losses and noise. The prototype single-chip T/R module contains integrated transistor switches, but not connected in series; instead, they are connected in a shunt configuration with resonant circuits (see figure). The shunt/resonant circuit topology not only reduces the losses associated with conventional semiconductor switches but also provides beneficial transformation of impedances for the PA and the LNA. It provides full singlepole/ double-throw switching for the antenna, isolating the LNA from the transmitted signal and isolating the PA from the received signal. During reception, the voltage on control line RX/TX (raised bar) is high, causing the field-effect transistor (FET) switch S1 to be closed, forming a parallel resonant tank circuit L1||C1. This circuit presents high impedance to the left of the antenna, so that the received signal is coupled to the LNA. At the same time, FET switches S2 and S3 are open, so that C2 is removed from the circuit (except for a small parasitic capacitance). The combination of L2 and C3 forms a matching network that transforms the antenna impedance of 50 ohms to a higher value from the perspective of the LNA input terminal. This transformation of impedance improves LNA noise figure by increasing the received voltage delivered to the input transistor. This allows lower transconductance and therefore a smaller transistor, which makes it possible to design the CMOS LNA for low power consumption. During transmission, the voltage on control line RX/TX (raised bar) is low, causing switch S1 to be open. In this configuration, the combination of L1 and C1 transforms the antenna impedance to a lower value from the perspective of the PA. This low impedance is helpful in producing a relatively high output power compatible with the low CMOS operating potential. At the same time, switches S2 and S3 are closed, forming the parallel resonant tank circuit L2||C2. This circuit presents high impedance to the right of the antenna, directing the PA output signal to the antenna and away from the LNA. During this time, S3 presents a short circuit across the LNA input terminals to guarantee that the voltage seen by the LNA is small enough to prevent damage.

Moussessian, Alina↗