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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

Integrated Circuit Design for Radiation-Hardened Charge-Sensitive Amplifier Survived up to 2 Mrad

According to the continuous development of metal-oxide semiconductor (MOS) fabrication technology, transistors have naturally become more radiation-tolerant through steadily decreasing gate-oxide thickness, increasing the tunneling probability between gate-oxide and channel. Unfortunately, despite this radiation-hardened property of developed transistors, the field of nuclear power plants (NPPs) requires even higher radiation hardness levels. Particularly, total ionizing dose (TID) of approximately 1 Mrad could be required for readout circuitry under severe accident conditions with 100 Mrad around a reactor in-core required. In harsh radiating environments such as NPPs, sensors such as micro-pocket-fission detectors (MPFD) would be a promising technology to be operated for detecting neutrons in reactor cores. For those sensors, readout circuits should be fundamentally placed close to sensing devices for minimizing signal interferences and white noise. Therefore, radiation hardening ability is necessary for the circuits under high radiation environments. This paper presents various integrated circuit designs for a radiation hardened charge-sensitive amplifier (CSA) by using SiGe 130 nm and Si 180 nm fabrication processes with different channel widths and transistor types of complementary metal-oxide-semiconductor (CMOS) and bipolar CMOS (BiCMOS). These circuits were tested under γ–ray environment with Cobalt-60 of high level activity: 490 kCi. The experiment results indicate amplitude degradation of 2.85%–34.3%, fall time increase of 201–1730 ns, as well as a signal-to-noise ratio (SNR) of 0.07–11.6 dB decrease with irradiation dose increase. These results can provide design guidelines for radiation hardening operational amplifiers in terms of transistor sizes and structures.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗
NASA NTRS1983

Source circuit design considerations

The cost of several circuit configurations for large (5MW) array fields were investigated to assess the relative costs of high and low voltage configurations. Three source circuit NOC voltages were evaluated: 400V (ungrounded), 800V (+ or 400V center grounded), and 2000V (+ or - 1000V center grounded). Four source circuit configurations were considered for each of the three NOC voltages. The configurations correspond to source circuit currents of 15, 30, 45, and 60 amperes, respectively. Conceptual layouts for 5MW building blocks for each of the above configurations were developed. The designs were optimized to minimize BOS electrical and structural costs. Only the BOS electrical costs were evaluated. The designs were broken down into the following elements for cost: (1) basic source circuit intermodule wiring, bypass diodes and associated hardware, source circuit to J-Box wiring, etc; (2) J-Box blocking diodes, varistors, heat sinks, and housing; (3) disconnects source circuit disconnects, fuses, and housing; (4) bus cabling J-Box to PCU interface wiring, and trenching; (5) interface bus bar, group disconnects, and fuses; and (6) fault detection shunts, signal wire, electronics, and alarm. It is concluded that high voltage low current circuits are not economical, at higher currents high and low voltage circuit costs approach each other, high voltage circuits are not likely to offer near term advantage, and development work/manufacturer stimulation is needed to develop low cost high voltage hardware.

Noel, G. T.↗
NASA NTRS2001

A High Efficiency, Miniaturized Ka Band Traveling Wave Tube Based on a Novel Finned Ladder RF Circuit Design

Space communications architectures are being planned to meet the high rate data distribution requirements of future NASA Enterprise missions. These will require the use of traveling wave tube amplifiers (TWTAs) to provide the high frequency, RF (radio frequency) power and efficiency needed for many of the communications links. A program addressing these requirements is currently underway at NASA Glenn Research Center (GRC) for the development of a high efficiency, 20 watt, 32 GHz TWT of reduced size and weight that is based on a novel high gain n circuit design, termed the 'finned ladder'.

Wintucky, E. G.↗
NASA NTRS1992

Circuit design tool. User's manual, revision 2

The CAM chip design was produced in a UNIX software environment using a design tool that supports definition of digital electronic modules, composition of these modules into higher level circuits, and event-driven simulation of these circuits. Our design tool provides an interface whose goals include straightforward but flexible primitive module definition and circuit composition, efficient simulation, and a debugging environment that facilitates design verification and alteration. The tool provides a set of primitive modules which can be composed into higher level circuits. Each module is a C-language subroutine that uses a set of interface protocols understood by the design tool. Primitives can be altered simply by recoding their C-code image; in addition new primitives can be added allowing higher level circuits to be described in C-code rather than as a composition of primitive modules--this feature can greatly enhance the speed of simulation.

Miyake, Keith M.↗
NASA NTRS1973

Binary selectable detector holdoff circuit: Design, testing, and application

A very high speed switching circuit, part of a laser radar data acquisition system, has been designed and tested. The primary function of this circuit was to provide computer controlled switching of photodiode detector preamplifier power supply voltages, typically less than plus or minus 20 volts, in approximately 10 nanoseconds. Thus, in actual use, detector and/or detector preamplifier damage can be avoided as a result of sudden extremely large values of backscattered radiation being detected, such as might be due to short range, very thin atmospheric dust layers. Switching of the power supply voltages was chosen over direct switching the photodiode detector input to the preamplifier, based on system noise considerations. Also, the circuit provides a synchronized trigger pulse output for triggering devices such as the Biomation Model 8100 100 MHz analog to digital converter.

Kadrmas, K. A.↗
NASA NTRS1995

Ring-plane traveling-wave tube slow-wave circuit design simulations at V-Band frequencies

The V-Band frequency range of 59-64 GHz is a region of the millimeter-wave spectrum that has been designated for intersatellite communications. As a first effort to develop a high-efficiency V-band TWT, variations on a ring-plane slow-wave circuit were computationally investigated to develop an alternative to the more conventional ferruled coupled-cavity circuit. The ring-plane circuit was chosen because of its high interaction impedance, large beam aperture, and excellent thermal dissipation properties. Despite the high-power capabilities of the ring-plane TWT, disadvantages of low bandwidth and high voltage requirements have until now prevented its acceptance outside the laboratory. In this paper, we use the three-dimensional electromagnetic simulation code MAFIA to investigate methods of increasing the bandwidth and lowering the operating voltage. Dispersion, impedance, and attenuation calculations for various geometric variations and loading distributions were performed. Based on the results of the variations, a circuit termed the finned-ladder TWT slowwave circuit was designed and is compared here to the scaled ring-plane prototype and the conventional ferruled coupled-cavity TWT circuit over the V-band frequency range.

Kory, Carol L.↗
NASA NTRS1994

Novel high-gain, improved-bandwidth, finned-ladder V-band Traveling-Wave Tube slow-wave circuit design

The V-band frequency range of 59-64 GHz is a region of the millimeter-wave spectrum that has been designated for inter-satellite communications. As a first effort to develop a high-efficiency V-band Traveling-Wave Tube (TWT), variations on a ring-plane slow-wave circuit were computationally investigated to develop an alternative to the more conventional ferruled coupled-cavity circuit. The ring-plane circuit was chosen because of its high interaction impedance, large beam aperture, and excellent thermal dissipation properties. Despite these advantages, however, low bandwidth and high voltage requirements have, until now, prevented its acceptance outside the laboratory. In this paper, the three-dimensional electrodynamic simulation code MAFIA (solution of MAxwell's Equation by the Finite-Integration-Algorithm) is used to investigate methods of increasing the bandwidth and lowering the operating voltage of the ring-plane circuit. Calculations of frequency-phase dispersion, beam on-axis interaction impedance, attenuation and small-signal gain per wavelength were performed for various geometric variations and loading distributions of the ring-plane TWT slow-wave circuit. Based on the results of the variations, a circuit termed the finned-ladder TWT slow-wave circuit was designed and is compared here to the scaled prototype ring-plane and a conventional ferruled coupled-cavity TWT circuit over the V-band frequency range. The simulation results indicate that this circuit has a much higher gain, significantly wider bandwidth, and a much lower voltage requirement than the scaled ring-plane prototype circuit, while retaining its excellent thermal dissipation properties. The finned-ladder circuit has a much larger small-signal gain per wavelength than the ferruled coupled-cavity circuit, but with a moderate sacrifice in bandwidth.

Kory, Carol L.↗
NASA NTRS1990

Implications of Tracey's theorem to asynchronous sequential circuit design

Tracey's Theorem has long been recognized as essential in generating state assignments for asynchronous sequential circuits. This paper shows that Tracey's Theorem also has a significant impact in generating the design equations. Moreover, this theorem is important to the fundamental understanding of asynchronous sequential operation. The results of this work simplify asynchronous logic design. Moreover, detection of safe circuits is made easier.

Gopalakrishnan, S.↗
NASA NTRS1996

System Guidelines for EMC Safety-Critical Circuits: Design, Selection, and Margin Demonstration

Demonstration of required safety margins on critical electrical/electronic circuits in large complex systems has become an implementation and cost problem. These margins are the difference between the activation level of the circuit and the electrical noise on the circuit in the actual operating environment. This document discusses the origin of the requirement and gives a detailed process flow for the identification of the system electromagnetic compatibility (EMC) critical circuit list. The process flow discusses the roles of engineering disciplines such as systems engineering, safety, and EMC. Design and analysis guidelines are provided to assist the designer in assuring the system design has a high probability of meeting the margin requirements. Examples of approaches used on actual programs (Skylab and Space Shuttle Solid Rocket Booster) are provided to show how variations of the approach can be used successfully.

Lawton, R. M.↗
NASA NTRS1996

System Guidelines for EMC Safety-Critical Circuits: Design, Selection, and Margin Demonstration

Demonstration of safety margins for critical points (circuits) has traditionally been required since it first became a part of systems-level Electromagnetic Compatibility (EMC) requirements of MIL-E-6051C. The goal of this document is to present cost-effective guidelines for ensuring adequate Electromagnetic Effects (EME) safety margins on spacecraft critical circuits. It is for the use of NASA and other government agencies and their contractors to prevent loss of life, loss of spacecraft, or unacceptable degradation. This document provides practical definition and treatment guidance to contain costs within affordable limits.

Lawton, R. M.↗
DOE OSTI2025

Harnessing ionic complexity: A modeling approach for hierarchical ionic circuit design

Since the 1950s, soft ionic devices have evolved from individual components to an expanding library of sensors, actuators, signal transmitters, and processors. However, integrating these components into complex, multifunctional systems remains challenging due to the nonintuitive and nonlinear interactions between ionic elements. In this work, we address these fundamental challenges by developing a lumped element model that enables interrogation of the physics that governs ionic circuits, as well as rapid design and optimization. Our model captures features specific to ionic charge carriers, while preserving the hierarchical design flexibility and computational efficiency of traditional circuit modeling. We demonstrate that our model can not only fit individual device behavior but also accurately predict the behavior of larger circuits formed by combining those devices. Additionally, we show how our tool utilizes the intrinsic nonlinearities of ionic systems to enable extended functionality, revealing how factors such as ion enrichment, ion leakage, and polymer charge density influence performance. Lastly, we present a fully ionic power supply, sensor, control system, and actuator for a soft robot that adapts its motion in response to environmental salt, illustrating the tool’s potential to accelerate advancements in chemical sensing, biointerfacing, biomimetic systems, and adaptive materials.

42 ENGINEERING↗
NASA NTRS1991

Asynchronous sequential circuit design using pass transistor iterative logic arrays

The iterative logic array (ILA) is introduced as a new architecture for asynchronous sequential circuits. This is the first ILA architecture for sequential circuits reported in the literature. The ILA architecture produces a very regular circuit structure. Moreover, it is immune to both 1-1 and 0-0 crossovers and is free of hazards. This paper also presents a new critical race free STT state assignment which produces a simple form of design equations that greatly simplifies the ILA realizations.

Liu, M. N.↗