SEARCH · Search NASA
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.
Single-event effects testing (heavy-ion and proton) is presented for 96- and 176-layer commercially-available 3D NAND flash memory, with emphasis on SEFI detection and recovery.
Single-event effects testing (heavy-ion and proton) is presented for 96- and 176-layer commercially-available 3D NAND flash memory, with emphasis on SEFI detection and recovery.
A data device includes a memory having a plurality of memory cells configured to store data values in accordance with a predetermined rank modulation scheme that is optional and a memory controller that receives a current error count from an error decoder of the data device for one or more data operations of the flash memory device and selects an operating mode for data scrubbing in accordance with the received error count and a program cycles count.
Progress on NASA’s Safe and Precise Landing Integrated Capabilities Evolution (SPLICE)project continues, specifically with this development of the Descent and Landing Computer(DLC). One of the DLC’s primary contributions as a SPLICE technology is its implementationof algorithms and operation of sensors to autonomously guide a spacecraft in performing moreprecise and safer landings on celestial bodies such as the Moon and Mars. The second iterationof the DLC is known as the Engineering Test Unit (ETU) and one of its desired functionalitiesis the ability to preserve the fidelity of the system’s boot file through the use of memoryscrubbing. The ETU has two primary boards, one for housing a Multi-Processor System ona Chip (MPSoC) and the other for housing a Xilinx Kintex Ultrascale FPGA3. To emulate amemory scrubbing function implemented on the ETU’s FPGA board, the design and testingof a software application was performed on a Xilinx KCU105 FPGA evaluation board. Thememory scrubbing application had to meet certain key criteria such as (1) properly utilize withthe flash memory’s Serial Peripheral Interface (SPI) to read, write, and erase flash memoryproperly, (2) be able to detect arbitrarily large or small amounts of bit-errors, (3) be able tocorrect all detected errors, and (4) perform memory scrubbing indefinitely and autonomously.A prototype implementation was constructed and tested, demonstrating successful detectionand correction of bit errors in multiple configurations. In the form of burst errors or singularbit flips, and in amounts of errors ranging from one to fifteen (per 256 Bytes), the applicationwas successful in preserving memory fidelity.
A recent model provides risk estimates for the deprogramming, of initially programmed floating gates, via prompt charge loss produced by an ionizing radiation environment. The environment can be a mixture of electrons, protons, and heavy ions. The model requires several input parameters. Parameters intended to produce conservative risk estimates for the Samsung 8 Gb SLC NAND flash memory are given, subject to some qualifications.
Explore the source record for details and available documents.
We evaluated the effects of heavy ion and proton irradiation for a 3D NAND flash. The 3D NAND showed similar single-event upset (SEU) sensitivity to a planar NAND of identical density in the multiple-cell level (MLC) storage mode. The 3D NAND showed significantly reduced SEU susceptibility in single-level-cell (SLC) storage mode. Additionally, the 3D NAND showed less multiple-bit upset susceptibility than the planar NAND, with fewer number of upset bits per byte and smaller cross sections overall. However, the 3D architecture exhibited angular sensitivities for both base and face angles, reflecting the anisotropic nature of the SEU vulnerability in space. Furthermore, the SEU cross section decreased with increasing fluence for both the 3D NAND and the Micron 16 nm planar NAND, which suggests that typical heavy ion test fluences will underestimate the upset rate during a space mission. These unique characteristics introduce complexity to traditional ground irradiation test procedures.
We investigated the single-event effect (SEE) susceptibility of the Micron 16 nm NAND flash, and found that the single-event upset (SEU) cross section varied inversely with cumulative fluence. We attribute the effect to the variable upset sensitivities of the memory cells. Furthermore, the effect impacts only single cell upsets in general. The rate of multiple-bit upsets remained relatively constant with fluence. The current test standards and procedures assume that SEU follow a Poisson process and do not take into account the variability in the error rate with fluence. Therefore, traditional SEE testing techniques may underestimate the on-orbit event rate for a device with variable upset sensitivity.
We evaluated the heavy ion and proton-induced single-event effects (SEE) for a 3D NAND flash. The 3D NAND showed similar single-event upset (SEU) sensitivity to a planar NAND of similar density and performance in the multiple-cell level (MLC) storage mode. However, the single-level-cell (SLC) storage mode of the 3D NAND showed significantly reduced SEU susceptibility. Additionally, the 3D NAND showed less MBU susceptibility than the planar NAND, with reduced number of upset bits per byte and reduced cross sections overall. However, the 3D architecture exhibited angular sensitivities for both base and face angles, reflecting the anisotropic nature of the SEU vulnerability in space. Furthermore, the SEU cross section decreased with increasing fluence for both the 3D NAND and the latest generation planar NAND, indicating a variable upset rate for a space mission. These unique characteristics introduce complexity to traditional ground irradiation test procedures.
We investigated the single-event effect (SEE) susceptibility of the Micron 16 nm NAND flash, and found the single-event upset (SEU) cross section varied inversely with fluence. The SEU cross section decreased with increasing fluence. We attribute the effect to the variable upset sensitivities of the memory cells. The current test standards and procedures assume that SEU follow a Poisson process and do not take into account the variability in the error rate with fluence. Therefore, heavy ion irradiation of devices with variable upset sensitivity distribution using typical fluence levels may underestimate the cross section and on-orbit event rate.
The purpose of this test was to characterize the Micron MT29F128G08AJAAAs parameter degradation for total dose response and to evaluate and compare lot date codes for sensitivity. In the test, the device was exposed to both low dose and high dose rate (HDR) irradiations using gamma radiation. Device parameters such as leakage currents, quantity of upset bits and overall chip and die health were investigated to determine which lot is more robust.
Explore the source record for details and available documents.
Explore the source record for details and available documents.
Explore the source record for details and available documents.
No abstract available
Explore the source record for details and available documents.
Explore the source record for details and available documents.