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The current program status reviewed by this viewgraph presentation includes: 1) New Evaluation Results; 2) Algorithm Improvement Investigations; 3) Electronic Hardware Design; 4) Software Hardware Interface Design.
The Architecture for Survivable System Processing (ASSP) Program is a multi-phase effort to implement Department of Defense (DOD) and commercially developed high-tech hardware, software, and architectures for reliable space avionics and ground based systems. System configuration options provide processing capabilities to address Time Dependent Processing (TDP), Object Dependent Processing (ODP), and Mission Dependent Processing (MDP) requirements through Open System Architecture (OSA) alternatives that allow for the enhancement, incorporation, and capitalization of a broad range of development assets. High technology developments in hardware, software, and networking models, address technology challenges of long processor life times, fault tolerance, reliability, throughput, memories, radiation hardening, size, weight, power (SWAP) and security. Hardware and software design, development, and implementation focus on the interconnectivity/interoperability of an open system architecture and is being developed to apply new technology into practical OSA components. To insure for widely acceptable architecture capable of interfacing with various commercial and military components, this program provides for regular interactions with standardization working groups (e.g.) the International Standards Organization (ISO), American National Standards Institute (ANSI), Society of Automotive Engineers (SAE), and Institute of Electrical and Electronic Engineers (IEEE). Selection of a viable open architecture is based on the widely accepted standards that implement the ISO/OSI Reference Model.
Integrated vehicle testing will be critical to ensuring proper vehicle integration of the Ares I crew launch vehicle and Ares V cargo launch vehicle. The Ares Projects, based at Marshall Space Flight Center in Alabama, created the Flight and Integrated Test Office (FITO) as a separate team to ensure that testing is an integral part of the vehicle development process. As its name indicates, FITO is responsible for managing flight testing for the Ares vehicles. FITO personnel are well on the way toward assembling and flying the first flight test vehicle of Ares I, th Ares I-X. This suborbital development flight will evaluate the performance of Ares I from liftoff to first stage separation, testing flight control algorithms, vehicle roll control, separation and recovery systems, and ground operations. Ares I-X is now scheduled to fly in summer 2009. The follow-on flight, Ares I-Y, will test a full five-segment first stage booster and will include cryogenic propellants in the upper stage, an upper stage engine simulator, and an active launch abort system. The following flight, Orion 1, will be the first flight of an active upper stage and upper stage engine, as well as the first uncrewed flight of an Orion spacecraft into orbit. The Ares Projects are using an incremental buildup of flight capabilities prior to the first operational crewed flight of Ares I and the Orion crew exploration vehicle in 2015. In addition to flight testing, the FITO team will be responsible for conducting hardware, software, and ground vibration tests of the integrated launch vehicle. These efforts will include verifying hardware, software, and grou handling interfaces. Through flight and integrated testing, the Ares Projects will identify and mitigate risks early the United States prepares to take its next giant leaps to the Moon and beyond.
Integrated vehicle testing will be critical to ensuring proper vehicle integration of the Ares I crew launch vehicle and Ares V cargo launch vehicle. The Ares Projects, based at Marshall Space Flight Center in Alabama, created the Flight and Integrated Test Office (FITO) as a separate team to ensure that testing is an integral part of the vehicle development process. As its name indicates, FITO is responsible for managing flight testing for the Ares vehicles. FITO personnel are well on the way toward assembling and flying the first flight test vehicle of Ares I, the Ares I-X. This suborbital development flight will evaluate the performance of Ares I from liftoff to first stage separation, testing flight control algorithms, vehicle roll control, separation and recovery systems, and ground operations. Ares I-X is now scheduled to fly in summer 2009. The follow-on flight, Ares I-Y, will test a full five-segment first stage booster and will include cryogenic propellants in the upper stage, an upper stage engine simulator, and an active launch abort system. The following flight, Orion 1, will be the first flight of an active upper stage and upper stage engine, as well as the first uncrewed flight of an Orion spacecraft into orbit. The Ares Projects are using an incremental buildup of flight capabilities prior to the first operational crewed flight of Ares I and the Orion crew exploration vehicle in 2015. In addition to flight testing, the FITO team will be responsible for conducting hardware, software, and ground vibration tests of the integrated launch vehicle. These efforts will include verifying hardware, software, and ground handling interfaces. Through flight and integrated testing, the Ares Projects will identify and mitigate risks early as the United States prepares to take its next giant leaps to the Moon and beyond.
Spacecraft telemetry rates have steadily increased over the last decade presenting a problem for real-time processing by ground facilities. This paper proposes a solution to a related problem for the Geostationary Operational Environmental Spacecraft (GOES-8) image processing application. Although large super-computer facilities are the obvious heritage solution, they are very costly, making it imperative to seek a feasible alternative engineering solution at a fraction of the cost. The solution is based on a Personal Computer (PC) platform and synergy of optimized software algorithms and re-configurable computing hardware technologies, such as Field Programmable Gate Arrays (FPGA) and Digital Signal Processing (DSP). It has been shown in [1] and [2] that this configuration can provide superior inexpensive performance for a chosen application on the ground station or on-board a spacecraft. However, since this technology is still maturing, intensive pre-hardware steps are necessary to achieve the benefits of hardware implementation. This paper describes these steps for the GOES-8 application, a software project developed using Interactive Data Language (IDL) (Trademark of Research Systems, Inc.) on a Workstation/UNIX platform. The solution involves converting the application to a PC/Windows/RC platform, selected mainly by the availability of low cost, adaptable high-speed RC hardware. In order for the hybrid system to run, the IDL software was modified to account for platform differences. It was interesting to examine the gains and losses in performance on the new platform, as well as unexpected observations before implementing hardware. After substantial pre-hardware optimization steps, the necessity of hardware implementation for bottleneck code in the PC environment became evident and solvable beginning with the methodology described in [1], [2], and implementing a novel methodology for this specific application [6]. The PC-RC interface bandwidth problem for the class of applications with moderate input-output data rates but large intermediate multi-thread data streams has been addressed and mitigated. This opens a new class of satellite image processing applications for bottleneck problems solution using RC technologies. The issue of a science algorithm level of abstraction necessary for RC hardware implementation is also described. Selected Matlab functions already implemented in hardware were investigated for their direct applicability to the GOES-8 application with the intent to create a library of Matlab and IDL RC functions for ongoing work. A complete class of spacecraft image processing applications using embedded re-configurable computing technology to meet real-time requirements, including performance results and comparison with the existing system, is described in this paper.
Space Station issues in fault management are discussed. The system background is described with attention given to design guidelines and power hardware. A contractually developed fault management system, FRAMES, is integrated with the energy management functions, the control switchgear, and the scheduling and operations management functions. The constraints that shaped the FRAMES system and its implementation are considered.
The goal of this project is to demonstrate and support the overall vision of NASA's Rocket University (RocketU) through the design of an electrical power system (EPS) monitor for implementation on RUBICS (Rocket University Broad Initiatives CubeSat), through the support for the CHREC (Center for High-Performance Reconfigurable Computing) Space Processor, and through FPGA (Field Programmable Gate Array) design. RocketU will continue to provide low-cost innovations even with continuous cuts to the budget.
Hazard analysis addresses hazards that arise in the design, development, manufacturing, construction, facilities, transportation, operations and disposal activities associated with hardware, software, maintenance, operations and environments. An integrated hazard is an event or condition that is caused by or controlled by multiple systems, elements, or subsystems. Integrated hazard analysis (IHA) is especially daunting and ambitious for large, complex systems such as NASA s Constellation program which incorporates program, systems and element components that impact others (International Space Station, public, International Partners, etc.). An appropriate IHA should identify all hazards, causes, controls and verifications used to mitigate the risk of catastrophic loss of crew, vehicle and/or mission. Unfortunately, in the current age of increased technology dependence, there is the tendency to sometimes overlook the necessary and sufficient qualifications of the integrator, that is, the person/team that identifies the parts, analyzes the architectural structure, aligns the analysis with the program plan and then communicates/coordinates with large and small components, each contributing necessary hardware, software and/or information to prevent catastrophic loss. As viewed from both Challenger and Columbia accidents, lack of appropriate communication, management errors and lack of resources dedicated to safety were cited as major contributors to these fatalities. From the accident reports, it would appear that the organizational impact of managers, integrators and safety personnel contributes more significantly to mission success and mission failure than purely technological components. If this is so, then organizations who sincerely desire mission success must put as much effort in selecting managers and integrators as they do when designing the hardware, writing the software code and analyzing competitive proposals. This paper will discuss the necessary and sufficient requirements of one of the significant contributors to mission success, the IHA integrator. Discussions will be provided to describe both the mindset required as well as deleterious assumptions/behaviors to avoid when integrating within a large scale system.
The Mir Cooperative Solar Array (MCSA) was developed jointly by the United States (US) and Russia to provide approximately 6 kW of photovoltaic power to the Russian space station Mir. After final assembly in Russia, the MCSA was shipped to the NASA Kennedy Space Center (KSC) in the summer of 1995 and launched to Mir in November 1995. Program managers were concerned of the potential for MCSA damage during the transatlantic shipment and the associated handling operations. To address this concern, NASA Lewis Research Center (LERC) developed an innovative dark-forward electrical test program to assess the gross electrical condition of each generator following shipment from Russia. The use of dark test techniques, which allow the array to remain in the stowed configuration, greatly simplifies the checkout of large area solar arrays. MCSA dark electrical testing was successfully performed at KSC in July 1995 following transatlantic shipment. Data from this testing enabled engineers to quantify the effects of potential MCSA physical damage that would degrade on-orbit electrical performance. In this paper, an overview of the principles and heritage of photovoltaic array dark testing is given. The specific MCSA dark test program is also described including the hardware, software, testing procedures and test results. The current-voltage (4) response of both solar cell circuitry and by-pass diode circuitry was obtained. To guide the development of dark test hardware, software and procedures, a dedicated FORTRAN computer code was developed to predict the dark 4 responses of generators with a variety of feasible damage modes. By comparing the actual test data with the predictions, the physical condition of the generator could be inferred. Based on this data analysis, no electrical short-circuits or open-circuits were detected. This suggested the MCSA did not sustain physical damage that affected electrical performance during handling and shipment from Russia to the US. Good agreement between the test data and computational predictions indicated MCSA electrical performance was amenable to accurate analysis and was well understood.
In this report, I will discuss the tasks and projects I have completed while working as an electrical engineering intern during the spring semester of 2016 at NASA Kennedy Space Center. In the field of software development, I completed tasks for the G-O Caching Mobile App and the Asbestos Management Information System (AMIS) Web App. The G-O Caching Mobile App was written in HTML, CSS, and JavaScript on the Cordova framework, while the AMIS Web App is written in HTML, CSS, JavaScript, and C# on the AngularJS framework. My goals and objectives on these two projects were to produce an app with an eye-catching and intuitive User Interface (UI), which will attract more employees to participate; to produce a fully-tested, fully functional app which supports workforce engagement and exploration; to produce a fully-tested, fully functional web app that assists technicians working in asbestos management. I also worked in hardware development on the Integrated Display and Environmental Awareness System (IDEAS) wearable technology project. My tasks on this project were focused in PCB design and camera integration. My goals and objectives for this project were to successfully integrate fully functioning custom hardware extenders on the wearable technology headset to minimize the size of hardware on the smart glasses headset for maximum user comfort; to successfully integrate fully functioning camera onto the headset. By the end of this semester, I was able to successfully develop four extender boards to minimize hardware on the headset, and assisted in integrating a fully-functioning camera into the system.
The Onboard Navigation rendezvous expert system is designed to aid the ground flight controller in monitoring the shuttle onboard navigation system. The system is designed to keep track of the navigation sensors and relative state vectors. In addition, the system also keeps an event log and fills out forms usually handled by the flight controller. This expert system is one of the few rendezvous specific systems being developed for the Mission Control Center. The expert system has been in development for six years. Through these years the system has seen hardware, software, and personnel changes. Initial development was done by the Information Systems Directorate (ISD) and Mission Operations Directorate (MOD) at Johnson Space Center. As of October 1, 1991 the system has been turned over to MOD. The system is completely developed except for some minor adjustments to the user interface. The rule base is in the verification stage with total certification of the system due to be completed by May 1992. Test cases for verification are obtained by saving data used for flight controller integrated simulations. The actual data comes from both the shuttle mission simulator and the Mission Control Center Computer. So far no actual flight data has been available. This paper covers all aspects of the system from the development history to the current hardware, software, and use of the system.
This project involves the development of more economical ways of integrating and interfacing new storage devices and data processing programs into a computer system. It involves developing interface standards and a software/hardware architecture which will make it possible to develop machine independent devices and programs. These will interface with the machine dependent operating systems of particular computers. The development project will not be to develop the software which would ordinarily be the responsibility of the manufacturer to supply, but to develop the standards with which that software is expected to confirm in providing an interface with the user or storage system.
The Mark 3 correlator system is described in some detail. The correlator system is based on a modular philosophy. Each correlator module independently processes the data from one track pair. Therefore, 28 modules are necessary to complete a full one baseline processor and 84 modules for a full 3 baseline processor. Each correlator module has two interfaces: (1) data and clock from each of the two tracks to be correlated and (2) Computer Automated Measurement and Control (CAMAC) dataway interface to the computer. The processor is organized around the IEEE CAMAC standard architecture, housing 15 correlator modules in each of 6 crates. This allows one pass processing of a full 3 baseline 28 track observation or a 6 baseline (4 station) 14 track observation. The correlator architecture allows easy expansion for up to 8 stations. The computer system is an HP 1000 system utilizing a 16 bit minicomputer with disc and tape peripherals. The processing software is also organized in a modular fashion with many independent but cooperative programs controlling the operation of the Mark 3 processor. Processing time through the correlator is normally real time or faster, with graphics displays providing real time monitor and control of the processing operation.
JPL image processing applications are examined, considering future trends in fields such as planetary exploration, electronics, astronomy, computers, and Landsat. Attention is given to adaptive search and interrogation of large image data bases, the display of multispectral imagery recorded in many spectral channels, merging data acquired by a variety of sensors, and developing custom large scale integrated chips for high speed intelligent image processing user stations and future pipeline production processors.
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Presentations of a conference on the use of ruggedized minicomputers are summarized. The following topics are discussed: (1) the role of minicomputers in the development and/or certification of commercial or military airplanes in both the United States and Europe; (2) generalized software error detection techniques; (3) real time software development tools; (4) a redundancy management research tool for aircraft navigation/flight control sensors; (5) extended memory management techniques using a high order language; and (6) some comments on establishing a system maintenance scheme. Copies of presentation slides are also included.
A reader system for the detection of cascade showers via luminescence induced by heating sensitive material (BaSO4:Eu) is developed. The reader system is composed of following six instruments: (1) heater, (2) light guide, (3) image intensifier, (4) CCD camera, (5) image processor, (6) microcomputer. The efficiency of these apparatuses and software application for image analysis is reported.
It was long a truism in computer systems design that balanced systems achieve the best performance. Message passing parallel processors are no different. To quantify the balance of a hypercube design, an experimental methodology was developed and the associated suite of benchmarks was applied to several existing hypercubes. The benchmark suite includes tests of both processor speed in the absence of internode communication and message transmission speed as a function of communication patterns.