Feasibility study and analysis of the use of computers to prepare monolithic integrated circuits for GSE Final report
Computerized design of photographic masks for integrated circuit fabrication
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Testing and Qualifying Linear Integrated Circuits for Radiation Degradation in Space
This paper discusses mechanisms and circuit-related factors that affect the degradation of linear integrated circuits from radiation in space. For some circuits there is sufficient degradation to affect performance at total dose levels below 4 krad(Si) because the circuit design techniques require higher gain for the pnp transistors that are the most sensitive to radiation. Qualification methods are recommended that include displacement damage as well as ionization damage.
integrated circuit testing↗
Development of beam lead RF integrated circuits
This paper describes the design and development of a set of multifunction VHF/UHF integrated circuits aimed at providing a major improvement in spacecraft radio reliability through low stress operation and the processing of these circuits in beam-lead form. The methods evolved for the high frequency characterization of the devices are discussed together with the design of suitable test fixtures. Typical test results and the distribution of test parameters are presented. A unique carrier for beam-lead devices is described, and the need for such a device is discussed. The application of the carrier to device screening, burn-in and drift measurements is discussed together with the incentives for providing these capabilities. An overview of the integration of the devices into the spacecraft radio is given and candidate assembly processes are discussed. The technology impact of this approach upon future spacecraft radio systems is qualitatively examined.
Kline, A. J.↗
The 1991 3rd NASA Symposium on VLSI Design
Papers from the symposium are presented from the following sessions: (1) featured presentations 1; (2) very large scale integration (VLSI) circuit design; (3) VLSI architecture 1; (4) featured presentations 2; (5) neural networks; (6) VLSI architectures 2; (7) featured presentations 3; (8) verification 1; (9) analog design; (10) verification 2; (11) design innovations 1; (12) asynchronous design; and (13) design innovations 2.
Maki, Gary K.↗
Digital design using selection operations
A digital integrated circuit chip is designed by identifying a logical structure to be implemented. This logical structure is represented in terms of a logical operations, at least 5% of which include selection operations. A determination is made of logic cells that correspond to an implementation of these logical operations.
Whitaker, Sterling R.↗
Continuous-Integration Laser Energy Lidar Monitor
This circuit design implements an integrator intended to allow digitization of the energy output of a pulsed laser, or the energy of a received pulse of laser light. It integrates the output of a detector upon which the laser light is incident. The integration is performed constantly, either by means of an active integrator, or by passive components.
Karsh, Jeremy↗
A Framework for Robust Multivariable Optimization of Integrated Circuits in Space Applications
Application Specific Integrated Circuit (ASIC) design for space applications involves multiple challenges of maximizing performance, minimizing power and ensuring reliable operation in extreme environments. This is a complex multidimensional optimization problem which must be solved early in the development cycle of a system due to the time required for testing and qualification severely limiting opportunities to modify and iterate. Manual design techniques which generally involve simulation at one or a small number of corners with a very limited set of simultaneously variable parameters in order to make the problem tractable are inefficient and not guaranteed to achieve the best possible results within the performance envelope defined by the process and environmental requirements. What is required is a means to automate design parameter variation, allow the designer to specify operational constraints and performance goals, and to analyze the results in a way which facilitates identifying the tradeoffs defining the performance envelope over the full set of process and environmental corner cases. The system developed by the Mixed Signal ASIC Group (MSAG) at the Goddard Space Flight Center is implemented as framework of software modules, templates and function libraries. It integrates CAD tools and a mathematical computing environment, and can be customized for new circuit designs with only a modest amount of effort as most common tasks are already encapsulated. Customization is required for simulation test benches to determine performance metrics and for cost function computation. Templates provide a starting point for both while toolbox functions minimize the code required. Once a test bench has been coded to optimize a particular circuit, it is also used to verify the final design. The combination of test bench and cost function can then serve as a template for similar circuits or be re-used to migrate the design to different processes by re-running it with the new process specific device models. The system has been used in the design of time to digital converters for laser ranging and time-of-flight mass spectrometry to optimize analog, mixed signal and digital circuits such as charge sensitive amplifiers, comparators, delay elements, radiation tolerant dual interlocked (DICE) flip-flops and two of three voter gates.
DuMonthier, Jeffrey↗
Assessment of Durable SiC JFET Technology for +600 C to -125 C Integrated Circuit Operation
Electrical characteristics and circuit design considerations for prototype 6H-SiC JFET integrated circuits (ICs) operating over the broad temperature range of -125 C to +600 C are described. Strategic implementation of circuits with transistors and resistors in the same 6H-SiC n-channel layer enabled ICs with nearly temperature-independent functionality to be achieved. The frequency performance of the circuits declined at temperatures increasingly below or above room temperature, roughly corresponding to the change in 6H-SiC n-channel resistance arising from incomplete carrier ionization at low temperature and decreased electron mobility at high temperature. In addition to very broad temperature functionality, these simple digital and analog demonstration integrated circuits successfully operated with little change in functional characteristics over the course of thousands of hours at 500 C before experiencing interconnect-related failures. With appropriate further development, these initial results establish a new technology foundation for realizing durable 500 C ICs for combustion engine sensing and control, deep-well drilling, and other harsh-environment applications.
Neudeck, P. G.↗
High-Voltage-Input Level Translator Using Standard CMOS
proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, "low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure. Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need. In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors, which, by virtue of being identical to the input transistors, would reproduce the input differential potential at the output
Yager, Jeremy A.↗
Electrical Performance of a High Temperature 32-I/O HTCC Alumina Package
A high temperature co-fired ceramic (HTCC) alumina material was previously electrically tested at temperatures up to 550 C, and demonstrated improved dielectric performance at high temperatures compared with the 96% alumina substrate that we used before, suggesting its potential use for high temperature packaging applications. This paper introduces a prototype 32-I/O (input/output) HTCC alumina package with platinum conductor for 500 C low-power silicon carbide (SiC) integrated circuits. The design and electrical performance of this package including parasitic capacitance and parallel conductance of neighboring I/Os from 100 Hz to 1 MHz in a temperature range from room temperature to 550 C are discussed in detail. The parasitic capacitance and parallel conductance of this package in the entire frequency and temperature ranges measured does not exceed 1.5 pF and 0.05 microsiemens, respectively. SiC integrated circuits using this package and compatible printed circuit board have been successfully tested at 500 C for over 3736 hours continuously, and at 700 C for over 140 hours. Some test examples of SiC integrated circuits with this packaging system are presented. This package is the key to prolonged T greater than or equal to 500 C operational testing of the new generation of SiC high temperature integrated circuits and other devices currently under development at NASA Glenn Research Center.
dielectric performance↗
An investigation for the development of an integrated optical data preprocessor
The successful fabrication and demonstration of an integrated optical circuit designed to perform a parallel processing operation by utilizing holographic subtraction to simultaneously compare N analog signal voltages with N predetermined reference voltages is summarized. The device alleviates transmission, storage and processing loads of satellite data systems by performing, at the sensor site, some preprocessing of data taken by remote sensors. Major accomplishments in the fabrication of integrated optics components include: (1) fabrication of the first LiNbO3 waveguide geodesic lens; (2) development of techniques for polishing TIR mirrors on LiNbO3 waveguides; (3) fabrication of high efficiency metal-over-photoresist gratings for waveguide beam splitters; (4) demonstration of high S/N holographic subtraction using waveguide holograms; and (5) development of alignment techniques for fabrication of integrated optics circuits. Important developments made in integrated optics are the discovery and suggested use of holographic self-subtraction in LiNbO3, development of a mathematical description of the operating modes of the preprocessor, and the development of theories for diffraction efficiency and beam quality of two dimensional beam defined gratings.
Verber, C. M.↗
Estimating Rates Of Single-Event Upsets
Mathematical model yields estimates of upper and lower bounds on rates of single-event upsets (SEU's) in logic circuits. SEU's are reversible changes in logic states, caused by single high-energy ions. Energetic ions passed through device along tracks perpendicular to surface, to determine parameters of model. Used to estimate rates caused by ions of various energies incident at arbitrary angles. Useful in design of integrated circuits as high-density memories for minimal susceptibility to bit errors.
Zoutendyk, John A.↗
A new RF package suitable for aeronautical commercial and DSCS satellite applications
Higher levels of integration through the use of GaAs and silicon MMIC devices, a die-cast housing, and the reduction of the number of subassemblies has enabled a large reduction of the size and weight of the electronics package for commercial and military satellite communications. This paper presents an electronics architecture and hardware that utilizes many new integrated circuits and design techniques, and allows flexibility for future satellite frequency changes and expansion. Key features of the radio are extended C-band, InSat, Defense Satellite Communications System (DSCS), and Ku-band coverage options; 70 (or 140) MHz transponder bandwidth or L-band block bandwidth IFs; integrated RS-232 control through local handheld terminal or remote computer; remote control of crystal reference oscillator for aging and temperature compensation; integrated 2 or 5 watt solid-state power amplifiers (SSPA); optional integrated solid-state booster amplifiers to 40 watts; optional external amplifiers to 100 watts; integral beacon tracking with second integrated downcoverter for antenna positioning; radio, including low-noise block converter (LNB) and SSPA, weighs 8.5 kg and measures 32 x 23 x 16.5 cm; environmentally ruggedized for -40 to +60 C; O-ring sealed for waterproofing; passive (convection) cooling; and simple cabling and installation, with a single cable between radio and LNB, and two cables between radio and IF interface. The small size and light weight of the radio make it ideal for mounting on stabilized antenna platforms (gyroscopic or servo). Several input power options (110 or 220 VAC; +48, +12, or -24 VDC) facilitate operation on multiple platforms.
Hamilton, Robert J., Jr.↗
The role of power integrated circuits in lightweight spacecraft
This paper will present definitions for smart power and power integrated circuits and show how, for a typical planetary spacecraft power system, a 37 percent reduction in mass, 89 percent reduction in parts and a 50 percent reduction in volume can be attained. Also discussed are the technology needs for isolation, monolithic current sensing, and high efficiency switching necessary to enable monolithic power structures, as well as various applications of power integrated circuits. A specific example will verify the projected reductions expected when power integrated circuits are implemented in future spacecraft designs. In conclusion, power-integrated circuits can impact the overall design of the spacecraft in all subsystems, not just the power sybsystem.
Klein, John W.↗
HYMOSS signal processing for pushbroom spectral imaging
The objective of the Pushbroom Spectral Imaging Program was to develop on-focal plane electronics which compensate for detector array non-uniformities. The approach taken was to implement a simple two point calibration algorithm on focal plane which allows for offset and linear gain correction. The key on focal plane features which made this technique feasible was the use of a high quality transimpedance amplifier (TIA) and an analog-to-digital converter for each detector channel. Gain compensation is accomplished by varying the feedback capacitance of the integrate and dump TIA. Offset correction is performed by storing offsets in a special on focal plane offset register and digitally subtracting the offsets from the readout data during the multiplexing operation. A custom integrated circuit was designed, fabricated, and tested on this program which proved that nonuniformity compensated, analog-to-digital converting circuits may be used to read out infrared detectors. Irvine Sensors Corporation (ISC) successfully demonstrated the following innovative on-focal-plane functions that allow for correction of detector non-uniformities. Most of the circuit functions demonstrated on this program are finding their way onto future IC's because of their impact on reduced downstream processing, increased focal plane performance, simplified focal plane control, reduced number of dewar connections, as well as the noise immunity of a digital interface dewar. The potential commercial applications for this integrated circuit are primarily in imaging systems. These imaging systems may be used for: security monitoring systems, manufacturing process monitoring, robotics, and for spectral imaging when used in analytical instrumentation.
Ludwig, David E.↗
A 94 GHz RF Electronics Subsystem for the CloudSat Cloud Profiling Radar
The CloudSat spacecraft, scheduled for launch in 2004, will carry the 94 GHz Cloud Profiling Radar (CPR) instrument. The design, assembly and test of the flight Radio Frequency Electronics Subsystem (RFES) for this instrument has been completed and is presented here. The RFES consists of an Upconverter (which includes an Exciter and two Drive Amplifiers (DA's)), a Receiver, and a Transmitter Calibrator assembly. Some key performance parameters of the RFES are as follows: dual 100 mW pulse-modulated drive outputs at 94 GHz, overall Receiver noise figure < 5.0 dB, a highly stable W-band noise source to provide knowledge accuracy of Receiver gain of < 0.4 dB over the 2 year mission life, and a W-band peak power detector to monitor the transmitter output power to within 0.5 dB over life. Some recent monolithic microwave integrated circuit (MMIC) designs were utilized which implement the DA's in 0.1 micron GaAs high electron-mobility transistor (HEMT) technology and the Receiver low-noise amplifier (LNA) in 0.1 micron InP HEMT technology.
radio frequency electronics subsystem (RFES)↗
Automating analog design: Taming the shrew
The pace of progress in the design of integrated circuits continues to amaze observers inside and outside of the industry. Three decades ago, a 50 transistor chip was a technological wonder. Fifteen year later, a 5000 transistor device would 'wow' the crowds. Today, 50,000 transistor chips will earn a 'not too bad' assessment, but it takes 500,000 to really leave an impression. In 1975 a typical ASIC device had 1000 transistors, took one year to first samples (and two years to production) and sold for about 5 cents per transistor. Today's 50,000 transistor gate array takes about 4 months from spec to silicon, works the first time, and sells for about 0.02 cents per transistor. Fifteen years ago, the single most laborious and error prone step in IC design was the physical layout. Today, most IC's never see the hand of a layout designer: and automatic place and route tool converts the engineer's computer captured schematic to a complete physical design using a gate array or a library of standard cells also created by software rather than by designers. CAD has also been a generous benefactor to the digital design process. The architect of today's digital systems creates the design using an RTL or other high level simulator. Then the designer pushes a button to invoke the logic synthesizer-optimizer tool. A fault analyzer checks the result for testability and suggests where scan based cells will improve test coverage. One obstinate holdout amidst this parade of progress is the automation of analog design and its reduction to semi-custom techniques. This paper investigates the application of CAD techniques to analog design.
Barlow, A.↗
Statistical circuit design for yield improvement in CMOS circuits
This paper addresses the statistical design of CMOS integrated circuits for improved parametric yield. The work uses the Monte Carlo technique of circuit simulation to obtain an unbiased estimation of the yield. A simple graphical analysis tool, the yield factor histogram, is presented. The yield factor histograms are generated by a new computer program called SPICENTER. Using the yield factor histograms, the most sensitive circuit parameters are noted, and their nominal values are changed to improve the yield. Two basic CMOS example circuits, one analog and one digital, are chosen and their designs are 'centered' to illustrate the use of the yield factor histograms for statistical circuit design.
Kamath, H. J.↗