Results for “non-blocking” — Page 3

DOE OSTI2022

UPC++ v1.0 Specification, Revision 2023.3.0

UPC++ is a C++ library providing classes and functions that support Partitioned Global Address Space (PGAS) programming. The key communication facilities in UPC++ are one-sided Remote Memory Access (RMA) and Remote Procedure Call (RPC). All communication operations are syntactically explicit and default to non-blocking; asynchrony is managed through the use of futures, promises and continuation callbacks, enabling the programmer to construct a graph of operations to execute asynchronously as high-latency dependencies are satisfied. A global pointer abstraction provides system-wide addressability of shared memory, including host and accelerator memories. The parallelism model is primarily process-based, but the interface is thread-safe and designed to allow efficient and expressive use in multi-threaded applications. The interface is designed for extreme scalability throughout, and deliberately avoids design features that could inhibit scalability.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2021

UPC++ v1.0 Specification (Revision 2021.3.0)

UPC++ is a C++11 library providing classes and functions that support Partitioned Global Address Space (PGAS) programming. The key communication facilities in UPC++ are one-sided Remote Memory Access (RMA) and Remote Procedure Call (RPC). All communication operations are syntactically explicit and default to non-blocking; asynchrony is managed through the use of futures, promises and continuation callbacks, enabling the programmer to construct a graph of operations to execute asynchronously as high-latency dependencies are satisfied. A global pointer abstraction provides system-wide addressability of shared memory, including host and accelerator memories. The parallelism model is primarily process-based, but the interface is thread-safe and designed to allow efficient and expressive use in multi-threaded applications. The interface is designed for extreme scalability throughout, and deliberately avoids design features that could inhibit scalability.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2022

UPC++ v1.0 Specification, Revision 2022.9.0

UPC++ is a C++ library providing classes and functions that support Partitioned Global Address Space (PGAS) programming. The key communication facilities in UPC++ are one-sided Remote Memory Access (RMA) and Remote Procedure Call (RPC). All communication operations are syntactically explicit and default to non-blocking; asynchrony is managed through the use of futures, promises and continuation callbacks, enabling the programmer to construct a graph of operations to execute asynchronously as high-latency dependencies are satisfied. A global pointer abstraction provides system-wide addressability of shared memory, including host and accelerator memories. The parallelism model is primarily process-based, but the interface is thread-safe and designed to allow efficient and expressive use in multi-threaded applications. The interface is designed for extreme scalability throughout, and deliberately avoids design features that could inhibit scalability.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2020

UPC++ v1.0 Specification, Revision 2020.3.0

UPC++ is a C++11 library providing classes and functions that support Partitioned Global Address Space (PGAS) programming. The key communication facilities in UPC++ are one-sided Remote Memory Access (RMA) and Remote Procedure Call (RPC). All communication operations are syntactically explicit and default to non-blocking; asynchrony is managed through the use of futures, promises and continuation callbacks, enabling the programmer to construct a graph of operations to execute asynchronously as high-latency dependencies are satisfied. A global pointer abstraction provides system-wide addressability of shared memory, including host and accelerator memories. The parallelism model is primarily process-based, but the interface is thread-safe and designed to allow efficient and expressive use in multi-threaded applications. The interface is designed for extreme scalability throughout, and deliberately avoids design features that could inhibit scalability.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2016

Asynchronous communication in spectral-element and discontinuous Galerkin methods for atmospheric dynamics – a case study using the High-Order Methods Modeling Environment (HOMME-homme_dg_branch)

The scalability of computational applications on current and next-generation supercomputers is increasingly limited by the cost of inter-process communication. We implement non-blocking asynchronous communication in the High-Order Methods Modeling Environment for the time integration of the hydrostatic fluid equations using both the spectral-element and discontinuous Galerkin methods. This allows the overlap of computation with communication, effectively hiding some of the costs of communication. A novel detail about our approach is that it provides some data movement to be performed during the asynchronous communication even in the absence of other computations. This method produces significant performance and scalability gains in large-scale simulations.

58 GEOSCIENCES↗

NASA NTRS1988

An intelligent allocation algorithm for parallel processing

The problem of allocating nodes of a program graph to processors in a parallel processing architecture is considered. The algorithm is based on critical path analysis, some allocation heuristics, and the execution granularity of nodes in a program graph. These factors, and the structure of interprocessor communication network, influence the allocation. To achieve realistic estimations of the executive durations of allocations, the algorithm considers the fact that nodes in a program graph have to communicate through varying numbers of tokens. Coarse and fine granularities have been implemented, with interprocessor token-communication duration, varying from zero up to values comparable to the execution durations of individual nodes. The effect on allocation of communication network structures is demonstrated by performing allocations for crossbar (non-blocking) and star (blocking) networks. The algorithm assumes the availability of as many processors as it needs for the optimal allocation of any program graph. Hence, the focus of allocation has been on varying token-communication durations rather than varying the number of processors. The algorithm always utilizes as many processors as necessary for the optimal allocation of any program graph, depending upon granularity and characteristics of the interprocessor communication network.

Carroll, Chester C.↗

NASA NTRS1997

Scalable Wrap-Around Shuffle Exchange Network with Deflection Routing

The invention in one embodiment is a communication network including plural non-blocking crossbar nodes, first apparatus for connecting the nodes in a first layer of connecting links, and second apparatus for connecting links independent of the first layer, whereby each layer is connected to the other layer at each point of the nodes. Preferably, each one of the layers of connecting links corresponds to one recirculating network topology that closes in on itself.

Monacos, Steve P.↗

NASA NTRS2001

Application of a Scalable, Parallel, Unstructured-Grid-Based Navier-Stokes Solver

A parallel version of an unstructured-grid based Navier-Stokes solver, USM3Dns, previously developed for efficient operation on a variety of parallel computers, has been enhanced to incorporate upgrades made to the serial version. The resultant parallel code has been extensively tested on a variety of problems of aerospace interest and on two sets of parallel computers to understand and document its characteristics. An innovative grid renumbering construct and use of non-blocking communication are shown to produce superlinear computing performance. Preliminary results from parallelization of a recently introduced "porous surface" boundary condition are also presented.

Parikh, Paresh↗

NASA NTRS2004

[PVFS 2000: An operational parallel file system for Beowulf]

The approach has been to develop Parallel Virtual File System version 2 (PVFS2) , retaining the basic philosophy of the original file system but completely rewriting the code. It shows the architecture of the server and client components. BMI - BMI is the network abstraction layer. It is designed with a common driver and modules for each protocol supported. The interface is non-blocking, and provides mechanisms for optimizations including pinning user buffers. Currently TCP/IP and GM(Myrinet) modules have been implemented. Trove -Trove is the storage abstraction layer. It provides for storing both data spaces and name/value pairs. Trove can also be implemented using different underlying storage mechanisms including native files, raw disk partitions, SQL and other databases. The current implementation uses native files for data spaces and Berkeley db for name/value pairs.

Ligon, Walt↗

NASA NTRS1994

A Permutation Engine Switching Node

We describe an asynchronous, strictly non-blocking crossbar node topology and distributed routing algorithm that is particularly suited to optoelectronic implementation.

Permutation engine permutation node topology routi↗

NASA NTRS2014

Launch Lock Assemblies Including Axial Gap Amplification Devices and Spacecraft Isolation Systems Including the Same

Embodiments of a launch lock assembly are provided, as are embodiments of a spacecraft isolation system including one or more launch lock assemblies. In one embodiment, the launch lock assembly includes first and second mount pieces, a releasable clamp device, and an axial gap amplification device. The releasable clamp device normally maintains the first and second mount pieces in clamped engagement; and, when actuated, releases the first and second mount pieces from clamped engagement to allow relative axial motion there between. The axial gap amplification device normally residing in a blocking position wherein the gap amplification device obstructs relative axial motion between the first and second mount pieces. The axial gap amplification device moves into a non-blocking position when the first and second mount pieces are released from clamped engagement to increase the range of axial motion between the first and second mount pieces.

Barber, Tim Daniel↗

NASA NTRS2024

Exploring New Frontiers in Space Communications: Enhancing Delay Tolerant Networking through Cloud and Containerization

The High-rate Delay Tolerant Networking (HDTN) project at NASA Glenn Research Center has developed software that enables more flexible, reliable, and efficient space internetworking by using modern computing techniques such as cloud services, microservices, network function virtualization, software defined networking, and a distributed architecture. HDTN is built upon the Bundle Protocol and related convergence layers which have been developed to mitigate the challenges of the space networking environment including long delays, asymmetric data rates, and intermittent connectivity. The HDTN implementation employs asynchronous message processing tasks which allow for non-blocking operations as well as deployment in both centralized and distributed architectures. This paper investigates deploying HDTN in a containerized approach on the NASA Goddard’s Mission Cloud Platform using Amazon Web Services Elastic Compute Cloud (EC2). Commercial cloud computing will lower operating costs, provide flexible resource allocation, and allow for interconnectivity between multiple NASA centers as well as external partners. Containerization using Docker will enable greater portability and scalability for HDTN to be deployed into a variety of environments. We discuss possible NASA missions and use-cases such as the Laser Communications Relay Demonstration (LCRD) where the services provided by HDTN (reliable transport, high-rate message processing, and store-and-forward capabilities) will be enhanced through cloud computing and containerization. In addition, we describe the HDTN architecture and possible microservice-based networking approaches that can be obtained via HDTN’s configuration capabilities. Finally, we detail the EC2 specifications needed to achieve data rates greater than 1 Gbps to support optical communication missions such as LCRD.

Blake LaFuente↗

DOE OSTI2016

Announcing Supercomputer Summit

Summit is the next leap in leadership-class computing systems for open science. With Summit we will be able to address, with greater complexity and higher fidelity, questions concerning who we are, our place on earth, and in our universe. Summit will deliver more than five times the computational performance of Titan’s 18,688 nodes, using only approximately 3,400 nodes when it arrives in 2017. Like Titan, Summit will have a hybrid architecture, and each node will contain multiple IBM POWER9 CPUs and NVIDIA Volta GPUs all connected together with NVIDIA’s high-speed NVLink. Each node will have over half a terabyte of coherent memory (high bandwidth memory + DDR4) addressable by all CPUs and GPUs plus 800GB of non-volatile RAM that can be used as a burst buffer or as extended memory. To provide a high rate of I/O throughput, the nodes will be connected in a non-blocking fat-tree using a dual-rail Mellanox EDR InfiniBand interconnect. Upon completion, Summit will allow researchers in all fields of science unprecedented access to solving some of the world’s most pressing challenges.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2018

Asynchronous cache flushing

Proactive flush logic in a computing system is configured to perform a proactive flush operation to flush data from a first memory in a first computing device to a second memory in response to execution of a non-blocking flush instruction. Reactive flush logic in the computing system is configured to, in response to a memory request issued prior to completion of the proactive flush operation, interrupt the proactive flush operation and perform a reactive flush operation to flush requested data from the first memory to the second memory.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2019

Technologies for increasing bandwidth in partitioned hierarchical networks

Technologies for increasing the bandwidth of partitioned hierarchical networks is disclosed. If each partition of network groups of a computer network are isolated, then the connections between the network groups of different partitions may go unused. However, careful selection of the network connections between partitions of different network groups may allow for a pseudo-direct connection between two network groups of the same partition using a single non-blocking switch in a network group of a different partition. Such a configuration can increase the effective bandwidth available within a partition without affecting the bandwidth available in another partition.

Flajslik, Mario↗

DOE OSTI2021

Solar collector installation design system including exceptional condition management and display

Embodiments may include systems and methods to create and edit a representation of a worksite, to create various data objects, to classify such objects as various types of pre-defined “features” with attendant properties and layout constraints. As part of or in addition to classification, an embodiment may include systems and methods to create, associate, and edit intrinsic and extrinsic properties to these objects. A design engine may apply of design rules to the features described above to generate one or more solar collectors installation design alternatives, including generation of on-screen and/or paper representations of the physical layout or arrangement of the one or more design alternatives. In some embodiments, metadata about the design process, including the process of classifying features and providing user input, generating layouts, and then modifying those layouts, may be generated. The metadata may include information about exceptional conditions in the project state information or design. A list of exceptions corresponding to exceptional conditions may be generated, and the designer may interact with these exceptions in a variety of ways, such as by complying with rules to remove an item from the exceptions list or overriding the application of the rules. The exceptions may be non-blocking relative to other user actions.

Wayne, Gary↗

DOE OSTI2022

Beam-steering system based on a MEMS-actuated vertical-coupler array

An integrated-optics MEMS-actuated beam-steering system is disclosed, wherein the beam-steering system includes a lens and a programmable vertical coupler array having a switching network and an array of vertical couplers, where the switching network can energize of the vertical couplers such that it efficiently emits the light into free-space. The lens collimates the light received from the energized vertical coupler and directs the output beam along a propagation direction determined by the position of the energized vertical coupler within the vertical-coupler array. In some embodiments, the vertical coupler is configured to correct an aberration of the lens. In some embodiments, more than one vertical coupler can be energized to enable steering of multiple output beams. In some embodiments, the switching network is non-blocking.

42 ENGINEERING↗

DOE OSTI2023

Beam-steering system based on a MEMS-actuated vertical-coupler array

An integrated-optics MEMS-actuated beam-steering system is disclosed, wherein the beam-steering system includes a lens and a programmable vertical coupler array having a switching network and an array of vertical couplers, where the switching network can energize of the vertical couplers such that it efficiently emits the light into free-space. The lens collimates the light received from the energized vertical coupler and directs the output beam along a propagation direction determined by the position of the energized vertical coupler within the vertical-coupler array. In some embodiments, the vertical coupler is configured to correct an aberration of the lens. In some embodiments, more than one vertical coupler can be energized to enable steering of multiple output beams. In some embodiments, the switching network is non-blocking.

Zhang, Xiaosheng↗