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At least 55 records · Page 3

Frequency and Phase-lock Control of a 3 THz Quantum Cascade Laser

We have locked the frequency of a 3 THz quantum cascade laser (QCL) to that of a far-infrared gas laser with a tunable microwave offset frequency. The locked QCL line shape is essentially Gaussian, with linewidths of 65 and 141 kHz at the -3 and -10 dB levels, respectively. The lock condition can be maintained indefinitely, without requiring temperature or bias current regulation of the QCL other than that provided by the lock error signal. The result demonstrates that a terahertz QCL can be frequency controlled with l-part-in-lO(exp 8) accuracy, which is a factor of 100 better than that needed for a local oscillator in a heterodyne receiver for atmospheric and astronomic spectroscopy.

Betz, A. L.↗

Frequency-Tuneable Pre-Stabilized Lasers for LISA via Sideband Locking

Laser frequency noise mitigation is one of the most challenging aspects of the LISA interferometric measurement system. The unstabilized frequency fluctuations must be suppressed by roughly twelve orders of magnitude in order to achieve a stability sufficient for gravitational wave detection. This enormous suppression will be achieved through a combination of stabilization and common-mode rejection. The stabilization component will itself be achieved in two stages: pre-stabilization to a local optical cavity followed by arm-locking to some combination of the inter-spacecraft distances. In order for these two stabilization stages to work simultaneously, the lock-point of the pre-stabilization loop must be frequency tunable. The current baseline stabilization technique, locking to an optical cavity, does not provide tunability between cavity resonance, which are typically spaced by 100s of MHz. Here we present a modification to the traditional Pound-Drever-Hall cavity locking technique that allows the laser to be locked to a cavity resonance with an adjustable frequency offset. This technique requires no modifications to the optical cavity itself, thus preserving the stability of the frequency reference. We present measurements of the system stability, demonstrating that the pre-stabilization level satisfies LISA requirements. We also present a demonstration of a phase-lock loop which utilizes the tunable sideband locking technique as a pre-stabilizations tage. The performance of the pre-stabilized phase-lock-loop indicates that the tunable sideband technique will meet the requirements as an actuator for arm-locking in LISA.

Thorpe, James Ira↗

Q-Band (37 to 41 GHz) Satellite Beacon Architecture for RF Propagation Experiments

In this paper, the design of a beacon transmitter that will be flown as a hosted payload on a geostationary satellite to enable propagation experiments at Q-band (37 to 41 GHz) frequencies is presented. The beacon uses a phased locked loop stabilized dielectric resonator oscillator and a solid-state power amplifier to achieve the desired output power. The satellite beacon antenna is configured as an offset-fed cutparaboloidal reflector.

Simons, Rainee N.↗

Q-Band (37-41 GHz) Satellite Beacon Architecture for RF Propagation Experiments

In this paper, the design of a beacon transmitter that will be flown as a hosted payload on a geostationary satellite to enable propagation experiments at Q-band (37-41 GHz) frequencies is presented. The beacon uses a phased locked loop stabilized dielectric resonator oscillator and a solid-state power amplifier to achieve the desired output power. The satellite beacon antenna is configured as an offset-fed cut-paraboloidal reflector.

Simmons, Rainee N.↗

A 24-Channel Digitizer With a JESD204B-Compliant Serial Interface for High-Speed Detectors

In this report a 24-channel application-specific integrated circuit (ASIC) for the readout of high-speed CMOS active pixel sensors for charged particle detection is presented. The chip comprises 24 preamplifiers, 24 distinct 12-bit, 25 MSPS Pipelined analog-to-digital converters (ADCs) with self-calibration, an internal phase-locked loop (PLL), and a 3 Gbps serial interface that conforms to the JESD204B standard. To simplify interfacing with a variety of sensors, the ASIC also includes an automatic offset calibration loop. The high level of integration of the ASIC reduces overall system cost and area, and exploiting the signal characteristics of the image sensor allows the ADC to be optimized for reduced power dissipation. The use of an integrated serializer and an industry standard protocol simplifies integration of the ASIC into a complete camera system. The ASIC, called the High-Speed Image Preprocessor Targeted for Electron Readout, or HIPSTER, with a die area of 64.26 mm 2 , is packaged in a 480-ball grid array (BGA) and is fabricated in 180-nm CMOS technology. HIPSTER achieves typical differential nonlinearity (DNL) < 0.55 LSB, input-referred thermal noise of $114.5 μV-rms, and a bit error rate (BER) of better than 10-14. The power dissipation is 98 mW/channel.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Block 4 receiver tracking loop performance in the presence of a CW RFI

A model that allows one to predict the tracking performance of the Block 4 receiver in the presence of a continuous wave radio frequency interference is discussed. Experimental and analytical results are provided for a typical Deep Space Network operational mode. Simulation and experimental results show good agreement with theoretical prediction for the static phase error and out-of-lock values. Predicted phase jitter is consistently lower than the experimental and simulated results by a factor of one-half for small interference to signal ratio (ISR) when the offset frequency is small. For large ISR, good agreement is observed. The analytical model assumes a noiseless condition, which is valid only when the loop is operated at strong signal levels. Experimental data indicate, however, that even at the minimum operating signal level of 10-dB carrier margin, reasonably good prediction can still be obtained. A curve of protection criteria that extends the current recommendation is also presented.

Sue, M. K.↗

Programmable, secondary frequency standard based infrared synthesizer using tunable lead-salt diode lasers

Quantum phase noise limited Lorentzian power spectral densities were achieved with tunable lead-salt diode lasers. Linewidths as narrow as 22 kHz were observed. A truly programmable infrared synthesizer was produced by frequency-offset-locking the tunable diode lasers to the combination of a stable CO2 (or CO) reference laser and a programmable microwave frequency synthesizer. Absolute frequency accuracy and reproducibility of about + or - 30 kHz (0.000001 kaysers) relative to the primary Cs frequency standard may now be obtained with this technique.

Freed, C.↗

Photoelectron spectrometer with means for stabilizing sample surface potential

An improved X-ray photoelectron spectrometer is disclosed, which includes circuit means to determine the surface potential of a sample, e.g., an insulator. The circuit means comprise an electron gun, whose potential is modulated at a preselected frequency above and below a selected potential with respect to the spectrometer common potential, e.g., ground. The beam of electrons is directed to the sample surface. The sample's surface potential is offset by an offset power supply with respect to the spectrometer common potential until the ac current which flows through the sample reaches a peak amplitude. A lock-in amplifier is included to measure the ac current in phase with the modulating frequency.

Grunthaner, F. J.↗

Loran digital phase-locked loop and RF front-end system error analysis

An analysis of the system performance of the digital phase locked loops (DPLL) and RF front end that are implemented in the MINI-L4 Loran receiver is presented. Three of the four experiments deal with the performance of the digital phase locked loops. The other experiment deals with the RF front end and DPLL system error which arise in the front end due to poor signal to noise ratios. The ability of the DPLLs to track the offsets is studied.

Mccall, D. L.↗

Method of recertifying a loaded bearing member

A method is described of recertifying a loaded bearing member using ultrasound testing to compensate for different equipment configurations and temperature conditions. The standard frequency F1 of a reference block is determined via an ultrasonic tone burst generated by a first pulsed phased locked loop (P2L2) equipment configuration. Once a lock point number S is determined for F1, the reference frequency F1a of the reference block is determined at this lock point number via a second P2L2 equipment configuration to permit an equipment offset compensation factor Fo1=((F1-F1a)/F1)(1000000) to be determined. Next, a reference frequency F2 of the unloaded bearing member is determined using a second P2L2 equipment configuration and is then compensated for equipment offset errors via the relationship F2+F2(Fo1)/1000000. A lock point number b is also determined for F2. A resonant frequency F3 is determined for the reference block using a third P2L2 equipment configuration to determine a second offset compensation factor F02=((F1-F3)/F1) 1000000. Next the resonant frequency F4 of the loaded bearing member is measured at lock point number b via the third P2L2 equipment configuration and the bolt load determined by the relationship (-1000000)CI(((F2-F4)/F2)-Fo2), wherein CI is a factor correlating measured frequency shift to the applied load. Temperature compensation is also performed at each point in the process.

Allison, Sidney G.↗

Performance evaluation of digital phase-locked loops for advanced deep space transponders

The performances of the digital phase-locked loops (DPLL's) for the advanced deep-space transponders (ADT's) are investigated. DPLL's considered in this article are derived from the analog phase-locked loop, which is currently employed by the NASA standard deep space transponder, using S-domain to Z-domain mapping techniques. Three mappings are used to develop digital approximations of the standard deep space analog phase-locked loop, namely the bilinear transformation (BT), impulse invariant transformation (IIT), and step invariant transformation (SIT) techniques. The performance in terms of the closed loop phase and magnitude responses, carrier tracking jitter, and response of the loop to the phase offset (the difference between in incoming phase and reference phase) is evaluated for each digital approximation. Theoretical results of the carrier tracking jitter for command-on and command-off cases are then validated by computer simulation. Both theoretical and computer simulation results show that at high sampling frequency, the DPLL's approximated by all three transformations have the same tracking jitter. However, at low sampling frequency, the digital approximation using BT outperforms the others. The minimum sampling frequency for adequate tracking performance is determined for each digital approximation of the analog loop. In addition, computer simulation shows that the DPLL developed by BT provides faster response to the phase offset than IIT and SIT.

Nguyen, T. M.↗

Detection of signals by weighted integrate-and-dump filter

A Weighted Integrate and Dump Filter (WIDF) is presented that results in reducing those losses in telemetry symbol signal to noise ratio (SNR) which occur in digital Integrate and Dump Filters (IDFs) when the samples are not phase locked to the input data symbol clock. The Minimum Mean Square Error (MMSE) criterion is used to derive a set of weights for approximating the analog integrate and dump filter, which is the matched filter for detection of signals in additive white Gaussian noise. This new digital matched filter results in considerable performance improvement compared to unweighted digital matched filters. An example is presented for a sampling rate of four times the symbol rate. As the sampling offset (or phase) varies with respect to the data symbol boundaries, the output SNR varies 1 dB for an unweighted IDF, but only 0.3 dB for the optimum WIDF, averaged over random data patterns. This improvement in performance relative to unweighted IDF means that significantly lower sampling and processing rates can be used for given telemetry symbol rates, resulting in reduced system cost.

Sadr, R.↗

Acquisition times of carrier tracking sampled data phase-locked loops

Phase acquisition times of type II and III loops typical of the Advanced Receiver are studied by computer simulations when the loops are disturbed by gaussian noise. Reliable estimates are obtained by running 5000 trials for each combination of loop signal-to-noise ratio (SNR) and frequency offset. The probabilities of acquisition are shown versus time from start of acquisition for various loop SNRs and frequency offsets. For frequency offsets smaller than one-fourth of the loop bandwidth and for loop SNRs of 10 dB and higher, the loops acquire with probability 0.99 within 2.5 B sub L for type II loops and within 7/B sub L for type III loops.

Aguirre, S.↗

On the probability of cycle-slipping in first-order phase-locked loops.

The first-passage time boundary value problem for first-order phase-locked loops (PLL) is analyzed, and spectral representations are developed for the probability density function (pdf), the distribution function, and the moments of the first time to passage (or cycle-slip). For the sinusoidal PLL, an asymptotic formula, that is surprisingly accurate even at low loop SNR's and large frequency offsets, is obtained for the pdf of the time to cycle-slip, in terms of the mean time to slip.

La Frieda, J. R.↗

Double dither loop for pseudonoise code tracking

A new type of phase detector for pseudonoise code tracking is introduced and analyzed in comparison with the delay lock loop (DLL) and tau-dither loop (TDL) configurations. It is shown that the double dither loop (DDL) combines the best features of the DLL and the TDL in that the DDL is insensitive to gain and offset imbalances and does not suffer the 3-dB degradation in noise performance typically associated with the TDL. The double dither concept is applicable to other dual channel detectors such as in a Costas-type carrier tracking loop.

Hopkins, P. M.↗

An all digital phase locked loop for FM demodulation.

A phase-locked loop designed with all-digital circuitry which avoids certain problems, and a digital voltage controlled oscillator algorithm are described. The system operates synchronously and performs all required digital calculations within one sampling period, thereby performing as a real-time special-purpose computer. The SNR ratio is computed for frequency offsets and sinusoidal modulation, and experimental results verify the theoretical calculations.

Greco, J.↗

Phase ambiguity resolution for offset QPSK modulation systems

A demodulator for Offset Quaternary Phase Shift Keyed (OQPSK) signals modulated with two words resolves eight possible combinations of phase ambiguity which may produce data error by first processing received I(sub R) and Q(sub R) data in an integrated carrier loop/symbol synchronizer using a digital Costas loop with matched filters for correcting four of eight possible phase lock errors, and then the remaining four using a phase ambiguity resolver which detects the words to not only reverse the received I(sub R) and Q(sub R) data channels, but to also invert (complement) the I(sub R) and/or Q(sub R) data, or to at least complement the I(sub R) and Q(sub R) data for systems using nontransparent codes that do not have rotation direction ambiguity.

Nguyen, Tien M.↗

The effects of sinusoidal interference on the second-order carrier tracking loop preceded by a bandpass limiter in the Block 4 receiver

Drop-lock relationships for the second-order phase-locked loop are derived when the carrier and a sinusoidal signal lie within the predetection filter bandwidth of the Block 4 receiver. Limiter suppression factors are calculated when a bandpass hard limiter is used to maintain constant total power at the loop. The parameters of interest are the interference-to-signal power ratio (ISR), the input signal-to-noise power ratio (NSR), and the interference signal frequency offset from carrier delta f. Limiter suppression caused by the combined effects of the noise and the interference signal accounts for the variability in the drop-lock threshold for given values of the input SNR and ISR parameters. Going beyond earlier published work that focused on the limiter's effect on the drop-lock threshold; an account is made for the limiter action in the interference mode and an overall imporvement is provided in the prediction accuracy of the drop-lock model.

Ruggier, C. J.↗