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Results for “on-chip networks”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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44 records · Page 3
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

Multiplexed color centers in a silicon photonic cavity array

Entanglement distribution is central to the modular scaling of quantum processors and establishing quantum networks. Color centers with telecom-band transitions and long spin coherence times are suitable candidates for long-distance entanglement distribution. However, high-bandwidth memory-enhanced quantum communication is limited by high-yield, scalable creation of efficient spin-photon interfaces. Here, we develop a silicon photonics platform consisting of arrays of bus-coupled cavities. The coupling to a common bus waveguide enables simultaneous access to individually addressable cavity-enhanced T center arrays. We demonstrate frequency-multiplexed operation of two T centers in separate photonic crystal cavities. In addition, we investigate the cavity enhancement of a T center through hybridized modes formed between physically distant cavities. Our results show that bus-coupled arrays of cavity-enhanced color centers could enable efficient on-chip and long-distance entanglement distribution.

Komza, Lukasz↗
DOE OSTI2020

FPDeep: Scalable Acceleration of CNN Training on Deeply-Pipelined FPGA Clusters

In this paper, we propose a framework called FPDeep, which uses a hybrid of model and layer paral- lelism to configure distributed reconfigurable clusters to train DNNs. This approach has numerous benefits. First, the design does not suffer from batch size growth. Second, novel workload and weight partitioning leads to balanced loads of both among nodes. And third, the entire system is fine-grained pipeline. This leads to high parallelism and utilization and also minimizes the time features need to be cached while waiting for back-propagation.

Wang, Tianqi↗
DOE OSTI2021

Single photon sources with near unity collection efficiencies by deterministic placement of quantum dots in nanoantennas

Deterministic coupling between photonic nodes in a quantum network is an essential step toward implementing various quantum technologies. The omnidirectionality of free-standing emitters, however, makes this coupling highly inefficient, in particular if the distant nodes are coupled via low numerical aperture (NA) channels such as optical fibers. This limitation requires placing quantum emitters in nanoantennas that can direct the photons into the channels with very high efficiency. Moreover, to be able to scale such technologies to a large number of channels, the placing of the emitters should be deterministic. In this work, we present a method for directly locating single free-standing quantum emitters with high spatial accuracy at the center of highly directional bullseye metal–dielectric nanoantennas. We further employ non-blinking, high quantum yield colloidal quantum dots for on-demand single-photon emission that is uncompromised by instabilities or non-radiative exciton recombination processes. Taken together, this approach results in a record-high collection efficiency of 85% of the single photons into a low NA of 0.5, setting the stage for efficient coupling between on-chip, room temperature nanoantenna-emitter devices and a fiber or a remote free-space node without the need for additional optics.

36 MATERIALS SCIENCE↗
DOE OSTI2023

On-Chip Batteries as Distributed Energy Sources in Heterogeneous 2.5D/3D Integrated Circuits

Energy efficiency in digital systems faces challenges due to the constraints imposed by small-scale transistors. Moreover, the growing demand for portable consumer electronics necessitates the use of compact energy sources. To address these challenges, heterogeneous 3D IC technology has emerged as a promising solution for the former. Regarding the latter, we propose the concept of distributed batteries within a heterogeneous 3D IC. This approach involves utilizing multiple smaller batteries with different specifications among different modules of 3D ICs. This approach optimizes performance and overcomes limitations associated with both 3D ICs and conventional power delivery methods. Distributed batteries play a vital role in effectively managing the heat generated by energy sources and modules within a 3D IC. Furthermore, they contribute to achieving a uniform distribution of heat throughout the entire structure, which ultimately ensures the optimal performance of the batteries and modules. The simulation results indicate a 40 percent enhancement in achieving a more even distribution of generated heat. Additionally, the proposed distributed battery techniques improve power delivery, enhance reliability, and enable optimized voltage regulation while improving efficiency. In addition to the primary benefits, alternative configurations of the proposed approach can offer extra energy storage capacity and act as efficient electromagnetic shields, resulting in an impressive reduction of external electromagnetic noises by 60 dB.

47 OTHER INSTRUMENTATION↗
DOE OSTI2023

Binary operations on neuromorphic hardware with application to linear algebraic operations and stochastic equations

Abstract Non-von Neumann computational hardware, based on neuron-inspired, non-linear elements connected via linear, weighted synapses—so-called neuromorphic systems—is a viable computational substrate. Since neuromorphic systems have been shown to use less power than CPUs for many applications, they are of potential use in autonomous systems such as robots, drones, and satellites, for which power resources are at a premium. The power used by neuromorphic systems is approximately proportional to the number of spiking events produced by neurons on-chip. However, typical information encoding on these chips is in the form of firing rates that unarily encode information. That is, the number of spikes generated by a neuron is meant to be proportional to an encoded value used in a computation or algorithm. Unary encoding is less efficient (produces more spikes) than binary encoding. For this reason, here we present neuromorphic computational mechanisms for implementing binary two’s complement operations. We use the mechanisms to construct a neuromorphic, binary matrix multiplication algorithm that may be used as a primitive for linear differential equation integration, deep networks, and other standard calculations. We also construct a random walk circuit and apply it in Brownian motion simulations. We study how both algorithms scale in circuit size and iteration time.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2024

FPGA-Accelerated Range-Limited Molecular Dynamics

Long timescale Molecular Dynamics (MD) simulation of small molecules is crucial in drug design and basic science. To accelerate a small data set that is executed for a large number of iterations, high-efficiency is required. Recent work in this domain has demonstrated that among COTS devices only FPGA-centric clusters can scale beyond a few processors. The problem addressed here is that, as the number of on-chip processors has increased from fewer than 10 into the hundreds, previous intra-chip routing solutions are no longer viable. We find, however, that through various design innovations, high efficiency can be maintained. These include replacing the previous broadcast networks with ring-routing and then augmenting the rings with out-of-order and caching mechanisms. Others are adding a level of hierarchical filtering and memory recycling. Two novel optimized architectures emerge, together with a number of variations. These are validated, analyzed, and evaluated. We find that in the domain of interest speed-ups over GPUs are achieved. Finally, the potential impact is that this system promises to be the basis for scalable long timescale MD with commodity clusters.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2021

Ultralow-threshold thin-film lithium niobate optical parametric oscillator

Materials with strong second-order ( χ <#comment/> ( 2 ) ) optical nonlinearity, especially lithium niobate, play a critical role in building optical parametric oscillators (OPOs). However, chip-scale integration of low-loss χ <#comment/> ( 2 ) materials remains challenging and limits the threshold power of on-chip χ <#comment/> ( 2 ) OPO. Here we report an on-chip lithium niobate optical parametric oscillator at the telecom wavelengths using a quasi-phase-matched, high-quality microring resonator, whose threshold power ( ∼ <#comment/> 30 µ <#comment/> W ) is 400 times lower than that in previous χ <#comment/> ( 2 ) integrated photonics platforms. An on-chip power conversion efficiency of 11% is obtained from pump to signal and idler fields at a pump power of 93 µW. The OPO wavelength tuning is achieved by varying the pump frequency and chip temperature. With the lowest power threshold among all on-chip OPOs demonstrated so far, as well as advantages including high conversion efficiency, flexibility in quasi-phase-matching, and device scalability, the thin-film lithium niobate OPO opens new opportunities for chip-based tunable classical and quantum light sources and provides a potential platform for realizing photonic neural networks.

Lu, Juanjuan (ORCID:0000000319389119)↗
DOE OSTI2025

Low-Jitter Clock Receivers for Fast Timing Applications

Precision timing is a key requirement for emerging 4D particle tracking, Positron Emission Tomography (PET), beam and fusion plasma diagnostics, and other systems. Time-to-Digital Converters (TDCs) are commonly used to provide digital estimates of the relative timing between events, but the jitter performance of a TDC can be no better than the performance of the circuits that acquire the pulses and deliver them to the TDC. Several clock receiver and distribution circuits were evaluated, and a differential amplifier with resistive loads driving a pseudo-differential clock distribution network, developed using design guidelines for radiation tolerance and cryogenic compatibility, was fabricated as part of three prototypes: an analog front-end testbed chip for high-precision timing pixel readout, a dedicated TDC evaluation chip, and a Low-Gain Avalanche Detector (LGAD) readout circuit. Based on TDC measurements of the prototypes, we infer that the jitter added by the clock receiver and distribution circuits is less than 2.25 ps-rms. This performance meets the requirements of many future precision timing systems. The clock receiver and on-chip pseudo-differential driver were fabricated in commercial 28-nm CMOS technology and occupy 2288 µm 2 .

47 OTHER INSTRUMENTATION↗