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Results for “phase-locking”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

Unified Universal Control and Coordination of Inverter-Based Resources, and Validation for a PV + Battery Hybrid Plant

As renewable energy deployment grows, hybrid power plants (HPPs) combining photovoltaic (PV) and battery systems must evolve to offer both energy and grid stability services. These systems typically include a mix of grid-following (GFL) and grid-forming (GFM) inverters, presenting unique coordination and control challenges. This Department of Energy–funded project developed and validated a Unified Universal Control and Coordination (UUCC) framework for such PV + battery hybrid plants, enabling seamless and stable operation, including ultrafast black start, autonomous synchronization, and robust frequency and voltage regulation, under different grid conditions. The project significantly advanced the understanding of inverter-based resource (IBR) control by developing and validating three complementary system-level approaches for hybrid GFL/GFM operation: 1. A combined Virtual Resistance (VR)-based GFL and Virtual Oscillator Control (VOC)-based GFM method, where each inverter type is governed by a specialized control strategy. Together, these achieve stable, fast-response coordination, eliminating inrush current and enabling smooth black start and grid synchronization across a wide range of grid strengths. 2. A Deadbeat-based UUCC strategy, which uses discrete-time, switching-cycle-level control for both GFL and GFM inverters. This approach replaces traditional PI/PLL control with a control parameter-free, high-bandwidth framework that supports stable LVRT and instantaneous synchronization under all conditions. 3. A benchmark comparison with Siemens’ commercial GFM microgrid controller, which provided a fast baseline platform. The commercial approach decoupled v & f control was implemented on a commercial microgrid controller.The baseline commercial benchmark helped highlight superior transient response and black start performance offered by the deadbeat and VOC approaches. These technical contributions offer substantial improvements over conventional inverter control schemes, which often rely on slow phase-locked loop (PLL)-based synchronization, require careful control parameters tuning, and prone to unstable in weak grids with GFL inverters and in stiff grid with GFM inverters therefore challenging for hybrid GFL+GFM under all grid conditions. The deadbeat-based UUCC framework enables simpler, faster, and more robust operation of hybrid IBR systems using wide-bandgap (WBG) devices such as SiC power semiconductors. The rapid expansion of hybrid distributed energy resources (DERs), including residential and commercial PV-BESS installations such as Tesla Powerwall, PV with vehicle-to-grid (V2G) capability, and other integrated configurations, presents complex operational challenges for medium-voltage radial distribution feeders. These networks are subject to frequent disturbances such as faults, switching operations, rapid reclosing sequences, and feeder reconfigurations, all of which introduce dynamic stress on IBRs. In addition, planned feeder segmentation and deliberate islanding for resilience will require DERs that can autonomously perform blackstart, establish voltage and frequency references, and resynchronize with the main grid. The advanced deadbeat-based UUCC control and blackstart functionalities developed in this project directly address these requirements, enabling decentralized and autonomous operation of inverter-dominated DERs in distribution systems under a wide range of fault and reconfiguration scenarios. From a public benefit perspective, these innovations enable more reliable and cost-effective integration of renewable energy into distribution networks. The ability to autonomously black start and stabilize grids under varying grid conditions support accelerates recovery from outages and support decentralized resilient energy systems. By reducing system complexity and improving performance, this project lays critical groundwork for future inverter-dominated power grids that are clean, reliable, and accessible to all.

14 SOLAR ENERGY↗
DOE OSTI2026

PIP-II LLRF Master Oscillator and Precision Reference Line - Station Level Design and Testing

The PIP-II superconducting linac at Fermilab requires a highly stable RF Reference Line to maintain phase syn- chronization throughout the accelerator. Temperature- induced changes in the electrical length of long coaxial cables can introduce phase drift and measurement errors. The reference-line architecture mitigates these effects by phase averaging the forward and reflected RF signals, while a phase-locked loop anchors the system to the mas- ter oscillator. This work focuses on the characterization, validation, and mechanical integration of station-level RF assemblies using CAD modeling, vector network analyzer measurements, and spectrum analyzer testing. PID-controlled thermal plates will stabilize critical RF components and further reduce temperature-dependent phase and amplitude variations. These methods sup- port repeatable, standardized designs that can be reliably integrated across the different reference-line stations.

Mosher, Alexander [U. Illinois, Chicago]↗
NASA NTRS1966

Interior servicing platform simplifies maintenance of storage tanks

Rapid synchronization of phase-locked oscillators is best achieved by the swept-frequency acquisition technique, wherein the Voltage-Controlled Oscillator /VCO/ is linearly swept through the uncertainty band. The theoretically predicted sweep rates of this technique and the observed experimental results differ by less than seven percent.

Ranger, C. S.↗
NASA NTRS1967

Spacecraft telemetry and command

Probability distribution of time to first loss of lock investigated by second order phase-locked loop - spacecraft telemetry and command

PHASE LOCK↗
NASA NTRS1972

An all digital phase locked loop for FM demodulation.

A phase-locked loop designed with all-digital circuitry which avoids certain problems, and a digital voltage controlled oscillator algorithm are described. The system operates synchronously and performs all required digital calculations within one sampling period, thereby performing as a real-time special-purpose computer. The SNR ratio is computed for frequency offsets and sinusoidal modulation, and experimental results verify the theoretical calculations.

Greco, J.↗
NASA NTRS1974

Synthesis and evaluation of phase detectors for active bit synchronizers

Self-synchronizing digital data communication systems usually use active or phase-locked loop (PLL) bit synchronizers. The three main elements of PLL synchronizers are the phase detector, loop filter, and the voltage controlled oscillator. Of these three elements, phase detector synthesis is the main source of difficulty, particularly when the received signals are demodulated square-wave signals. A phase detector synthesis technique is reviewed that provides a physically realizable design for bit synchronizer phase detectors. The development is based upon nonlinear recursive estimation methods. The phase detector portion of the algorithm is isolated and analyzed.

Mcbride, A. L.↗
NASA NTRS1987

Clock synchronization of a large multiprocessor system in the presence of malicious faults

An interconnection algorithm is presented for achieving clock synchronization in a multiprocessor system. The system is assumed to be maliciously faulty, i.e., some processors are out of synchronization and lie about their clock state to other intragroup or intergroup processors. A phase-locked clock network design is proposed which groups the clocks in the system into diverse clusters. The clusters are then treated as single clock units from the perspective of the network. The algorithm minimizes the number of interconnections while permitting synchronization of large multiprocessor systems controlling time-critical applications such as aircraft, nuclear reactors and industrial processes.

Shin, Kang G.↗
NASA NTRS1961

A Long-Range Precision Ranging System

A technique is presented that may be used for precision real-time continuous range measuring at long ranges. The technique uses a carrier that is phase modulated by a pseudo-random binary sequence. The characteristics of the sequence that make it acquirable are discussed. The general form of a receiver capable of tracking the carrier is given and is shown to be a kind of phase-locked loop. A two-loop system capable of tracking a pseudo-random sequence and its clock is given. The combination of the receiver and the sequence tracking system form a ranging receiver. The power division necessary between the carrier and the sidebands is shown to be determined by the noise bandwidths of the two tracking systems. The bandwidths necessary for tracking space probes and Earth satellites are given and some experiments in radar-tracking Earth satellites are described. Based on these experiments, estimates are made of the useful range of such a system in tracking space probes.

Easterling, Mahlon↗
DOE OSTI2025

An Arbitrary Time Interval Generator Base on Vernier Clocks with 0.67 ps Adjustable Steps Implemented in FPGA

In TDC testing and timing system implementations, it is often necessary to generate signal pulses with finely adjustable time intervals. In delay cell–based schemes, the adjustment resolution is constrained by the propagation delay of the cells—typically 15–20 ps per step—and is sensitive to temperature and supply voltage variations. This document presents a fully digital approach that uses two vernier clocks, generated by two stages of cascaded phase-locked loops (PLLs) with a slight frequency difference, to achieve adjustable timing intervals through accumulated phase differences. The scheme was validated on two families of low-cost FPGA devices, achieving adjustable step sizes of 0.67 ps and 0.97 ps.

Wu, Jin-yuan [Fermilab] (ORCID:0000000344329521)↗