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Results for “power semiconductor device”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
NASA NTRS2001

Development of Electronics for Low-Temperature Space Missions

Electronic systems that are capable of operating at cryogenic temperatures will be needed for many future NASA space missions, including deep space probes and spacecraft for planetary surface exploration. In addition to being able to survive the harsh deep space environment, low-temperature electronics would help improve circuit performance, increase system efficiency, and reduce payload development and launch costs. Terrestrial applications where components and systems must operate in low-temperature environments include cryogenic instrumentation, superconducting magnetic energy storage, magnetic levitation transportation systems, and arctic exploration. An ongoing research and development project for the design, fabrication, and characterization of low-temperature electronics and supporting technologies at NASA Glenn Research Center focuses on efficient power systems capable of surviving in and exploiting the advantages of low-temperature environments. Supporting technologies include dielectric and insulating materials, semiconductor devices, passive power components, optoelectronic devices, and packaging and integration of the developed components into prototype flight hardware. An overview of the project is presented, including a description of the test facilities, a discussion of selected data from component testing, and a presentation of ongoing research activities being performed in collaboration with various organizations.

Patterson, Richard L.↗
NASA NTRS2017

Taking SiC Power Devices to the Final Frontier: Addressing Challenges of the Space Radiation Environment

Silicon carbide power device technology has the potential to enable a new generation of aerospace power systems that demand high efficiency, rapid switching, and reduced mass and volume in order to expand space-based capabilities. For this potential to be realized, SiC devices must be capable of withstanding the harsh space radiation environment. Commercial SiC components exhibit high tolerance to total ionizing dose but to date, have not performed well under exposure to heavy ion radiation representative of the on-orbit galactic cosmic rays. Insertion of SiC power device technology into space applications to achieve breakthrough performance gains will require intentional development of components hardened to the effects of these highly-energetic heavy ions. This work presents heavy-ion test data obtained by the authors over the past several years for discrete SiC power MOSFETs, JFETs, and diodes in order to increase the body of knowledge and understanding that will facilitate hardening of this technology to space radiation effects. Specifically, heavy-ion irradiation data taken under different bias, temperature, and ion beam conditions is presented for devices from different manufacturers, and the emerging patterns discussed.

Power semiconductor devices↗
NASA NTRS2006

Effects of Radiation on Commercial Power Devices

The effects of radiation on various commercial power devices are presented. The devices have proved to be very fragile to single event effects, with some of the devices actually succumbing to catastrophic SEE with protons.

power semiconductor devices↗
DOE OSTI2020

Integrated circuits with programmable gate timing signal generation for power converters and apparatus comprising the same

An apparatus is disclosed that includes a semiconductor device to control a power converter having two or more power FETs. The semiconductor device includes a gate signal generator configured to produce two or more gate signals able to drive the two or more FETs. The gate signal generator has programmable timing configuration parameters to control operation of the two or more gate signals, wherein the timing configuration parameters are digitally programmed via a memory in the semiconductor device. The memory may be implemented with fuses, other non-volatile memory or volatile memory. The parameters may be fixed or updated during a lifetime of the apparatus. A serial-to-parallel conversion may be used to input the parameters. Optimization methods may be performed to determine parameters considered to be optimal. The apparatus may also include the power converter.

42 ENGINEERING↗
DOE OSTI2025

Enhancement-Mode GaN Monolithic Bidirectional Switch With Breakdown Voltage Over 3.3 kV

Here, this work demonstrates a GaN enhancement-mode monolithic bidirectional switch (MBDS) with breakdown voltage (BV) higher than 3.3 kV in both polarities. This MBDS is realized on a dual p-GaN gate high electron mobility transistor (HEMT) platform on sapphire substrate. It features a novel dual junction termination extension design for electric field management, which is built on the p-GaN layer in the gate stack and does not require epitaxial regrowth. The GaN MBDS exhibits symmetric on-state characteristics in both directions with a threshold voltage (V th ) of 0.6 V and a low specific on-resistance (R on,sp ) of 5.6 m Ω · cm2. This device presents the highest BV, as well as one of the best BV and R on,sp trade-offs, in all the reported MBDS devices. The R on,sp is lower than the performance limit of conventional BDS realized by two discrete devices. This 3.3 kV GaN MBDS opens the door for developing new circuit topologies and advancing system performance in medium-voltage power electronics.

42 ENGINEERING↗
DOE OSTI2023

Implanted Guard Ring Edge Termination With Avalanche Capability for Vertical GaN Devices

Edge termination is the key building block in power devices to enable near-ideal, avalanche breakdown voltage (BV). Here, this work presents the design, fabrication, and physics of a GaN guard ring (GR) edge termination formed by selective-area nitrogen implantation through an epitaxial p-GaN layer. The fabrication of this termination only includes a single implantation step that does not require precise control of implant depth, rendering a large process latitude. The selective-area implantation produces p-GaN rings that are separated by the implanted, semi-insulating regions. The number and spacing of the p-type rings are found to determine the BV of the vertical GaN p-n diode. The 16-ring structure enables a BV of 1800 V, being 88% of the theoretical 1-D parallel-plane limit. Avalanche characteristics are observed in devices with a large variety of GR designs. Finally, we present a comprehensive survey on the efficiency, fabrication complexity, real estate, and avalanche capability of various edge termination techniques that have been reported in vertical GaN devices. The high efficiency (among the highest reported in avalanche-capable GaN terminations), simple and robust fabrication process, and uniform avalanche capability make this implanted GR a promising edge termination for high-voltage GaN devices.

42 ENGINEERING↗
DOE OSTI2020

Surge-Energy and Overvoltage Ruggedness of P-Gate GaN HEMTs

An essential ruggedness of power devices is the capability of safely withstanding the surge energy. The surge ruggedness of the GaN high-electron-mobility transistor (HEMT), a power transistor with no or minimal avalanche capability, has not been fully understood. This article unveils the comprehensive physics associated with the surge-energy withstand process and the failure mechanisms of p-gate GaN HEMTs. Two commercial p-gate GaN HEMTs with Ohmic- and Schottky-type gate contacts are studied. Two circuits are developed to study the device surge ruggedness: an unclamped inductive switching circuit is first used to identify the withstand dynamics and failure mechanisms, and a clamped inductive switching circuit with a controllable parasitic inductance is then designed to mimic the surge energy in converter-like switching events. The p-gate GaN HEMT is found to withstand the surge energy through a resonant energy transfer between the device capacitance and the load/parasitic inductance rather than a resistive energy dissipation as occurred in the avalanche. If the device resonant voltage goes below zero, the device reversely turns on and the inductor is discharged. The device failure occurs at the transient of peak resonant voltage and is limited by the device overvoltage capability rather than the surge energy, dV/dt , or overvoltage duration. Almost no energy is dissipated in the resonant withstand process and the device failure is dominated by an electric field rather than a thermal runaway. Furthermore, these results provide critical understandings on the ruggedness of GaN HEMTs and important references for their qualifications and applications.

42 ENGINEERING↗
DOE OSTI2020

Experimental Demonstration of Charge-Balanced GaN Super-Heterojunction Schottky Barrier Diode Capable of 2.8 kV Switching

This letter reports an experimental demonstration of charge-balanced GaN super-heterojunction Schottky barrier diodes (SHJ-SBDs). Charge balance between the n-type delta-doping and the p-type doping was achieved by adjusting the thickness of the pGaN. Furthermore, this device structure enabled scaling of breakdown voltage to over 3 kV, and dynamic switching up to 2.8 kV without using any field-plate.

42 ENGINEERING↗
DOE OSTI2021

12.5 kV GaN Super-Heterojunction Schottky Barrier Diodes

In this work, we report GaN super-heterojunction Schottky barrier diodes (SHJ-SBDs) with substantially improved performance. Metal-2DEG sidewall n-ohmic contacts were deployed to achieve low contact resistance of 0.75 Ω · mm, avoiding the risk of abnormally high contact resistance caused by inaccurate etch depth control. A pGaN notch formed near the cathode successfully eliminated excessive hole conduction caused by the sidewall n-ohmic contact. Isolation was improved by a high-energy Al implantation step. The resulting SHJ-SBD exhibited a breakdown voltage (BV) of 12.5 kV and a specific ON-resistance of 100.8 mΩ · cm 2 .

42 ENGINEERING↗
NASA NTRS2016

Heavy Ion Induced Degradation in SiC Schottky Diodes: Bias and Energy Deposition Dependence

Experimental results on ion-induced leakage current increase in 4H-SiC Schottky power diodes are presented. Monte Carlo and TCAD simulations show that degradation is due to the synergy between applied bias and ion energy deposition. This degradation is possibly related to thermal spot annealing at the metal semiconductor interface. This thermal annealing leads to an inhomogeneity of the Schottky barrier that could be responsible for the increase leakage current as a function of fluence.

modeling↗
NASA NTRS2014

5.8kV SiC PiN Diode for Switching of High-Efficiency Inductive Pulsed Plasma Thruster Circuits

Inductive Pulsed Plasma Thruster (IPPT) pulse circuits, such as those needed to operate the Pulsed Inductive Thruster (PIT), are required to quickly switch capacitor banks operating at a period of μs while conducting current at levels on the order of at least 10 kA. [1,2] For all iterations of the PIT to date, spark gaps have been used to discharge the capacitor bank through an inductive coil. Recent availability of fast, high‐power solid state switching devices makes it possible to consider the use of semiconductor switches in modern IPPTs. In addition, novel pre‐ionization schemes have led to a reduction in discharge energy per pulse for electric thrusters of this type, relaxing the switching requirements for these thrusters. [3,4] Solid state switches offer the advantage of greater controllability and reliability, as well as decreased drive circuit dimensions and mass relative to spark gap switches. The use of solid state devices such as Integrated Gate Bipolar Transistors (IGBTs), Gate Turn‐off Thyristors (GTOs) and Silicon‐Controlled Rectifiers (SCRs) often involves the use of power diodes. These semiconductor devices may be connected antiparallel to the switch for protection from reverse current, or used to reduce power loss in a circuit by clamping off current ringing. In each case, higher circuit efficiency may be achieved by using a diode that is able to transition, or 'switch,' from the forward conducting state ('on' state) to the reverse blocking state ('off' state) in the shortest amount of time, thereby minimizing current ringing and switching losses. Silicon Carbide (SiC) PiN diodes offer significant advantages to conventional fast‐switching Silicon (Si) diodes for high power and fast switching applications. A wider band gap results in a breakdown voltage 10 times that of Si, so that a SiC device may have a thinner drift region for a given blocking voltage. [5] This leads to smaller, lighter devices for high voltage applications, as well as reduced forward conduction losses, faster reverse recovery time (faster turn‐off), and lower‐magnitude reverse recovery current. In addition, SiC devices have lower leakage current as compared to their Si counterparts, and a high thermal conductivity, potentially allowing the former to operate at higher temperatures with a smaller, lighter heatsink (or no heatsink at all).

Toftul, Alexandra↗
DOE OSTI2021

Semiconductor topologies and devices for soft starting and active fault protection of power converters

Various examples are provided related to semiconductor topologies and devices that can be used for soft starting and active fault protection of power converters. In one example, an active switch device includes an active switch having a gating control input; and a thyristor having a gating control input. The thyristor is coupled in parallel with the active switch. The active switch can be an IGBT, MOSFET, or other appropriate device. In another example, a power converter can include the active switch devices and switching control circuitry coupled to gating control inputs of the active switch devices.

Beddingfield, Richard B.↗
DOE OSTI2019

Electrothermal Modeling and Analysis of Gallium Oxide Power Switching Devices: Preprint

Gallium oxide is an emerging wide band-gap material that has the potential to penetrate the power electronics market in the near future. In this paper, a finite-element gallium oxide semiconductor model is presented that can predict the electrical and thermal characteristics of the device. The finite element model of the two-dimensional device architecture is developed inside the Sentaurus environment. A vertical FinFET device architecture is employed to assess the device's behavior and its static and dynamic behavior. Enhancement-mode device operation is realized with this type of device architecture without the need for any selective area doping. The dynamic thermal behavior of the device is characterized through its short-circuit behavior. Based on the device static and dynamic behavior, it is envisioned that reliable vertical transistors can be fabricated for the power electronics applications.

33 ADVANCED PROPULSION SYSTEMS↗
DOE OSTI2022

Bonded Interfaces for High-Temperature Power Electronics

Wide-bandgap devices have pushed the operational limit of semiconductor devices in automotive power electronics packages to higher temperatures (>200 degrees C). While a higher efficiency can be achieved through the use of wide-bandgap devices, the entire package must be re-designed with components that can withstand the higher temperature limits. Sintered silver and transient liquid phase bonds are potential candidates as bonded materials for use in higher temperatures however, the underlying mechanics of deformation under thermal loads and the resulting failure mechanisms in these materials are not well understood. Furthermore, thermomechanical modeling plays a key role in understanding the degradation behavior of bonded interface materials and for design optimization of power electronics packages.

ADVANCED PROPULSION SYSTEMS,DIRECT ENERGY CONVERSI↗
DOE OSTI2020

Liquid-Cooled Heat Sink Optimization for Thermal Imbalance Mitigation in Wide-Bandgap Power Modules

Power semiconductor die layout in substrates used in power modules is generally optimized for minimum electrical parasitics (e.g., stray inductance) by considering the minimum spacing between dies for thermal decoupling. The layout assumes sufficient heat spreading and transfer from dies to the cooling structure. For module designs using a direct substrate cooling method, the base plate is removed, leading to a steady-state thermal asymmetry in the power module due to insufficient heat spreading/transfer. This causes significant temperature differences among the devices. Such unintentional thermal asymmetries can lead to undesirable asymmetries in power conversion among semiconductor devices, which impact reliability. This article proposes a thermal imbalance mitigation method that uses evolutionary optimized liquid-cooled heat sinks to improve the thermal loading among devices.

Sahu, Raj↗