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At least 55 records · Page 3

Final Reports from the Los Alamos National Laboratory Computational Physics Student Summer Workshop

The two primary purposes of LANL’s Computational Physics Student Summer Workshop are (1) To educate graduate and exceptional undergraduate students in the challenges and applications of computational physics of interest to LANL, and (2) Entice their interest toward those challenges. Computational physics is emerging as a discipline in its own right, combining expertise in mathematics, physics, and computer science. The mathematical aspects focus on numerical methods for solving equations on the computer as well as developing test problems with analytical solutions. The physics aspects are very broad, ranging from low-temperature material modeling to extremely high temperature plasma physics, radiation transport and neutron transport. The computer science issues are concerned with matching numerical algorithms to emerging architectures and maintaining the quality of extremely large codes built to achieve multi-physics calculations. Although graduate programs associated with computational physics are emerging, it is apparent that the pool of U.S. citizens in this multidisciplinary field is relatively small and is typically not focused on the aspects that are of primary interest to LANL. Furthermore, more structured foundations for LANL interaction with universities in computational physics is needed; currently interactions rely almost solely on individuals’ personalities and personal contacts. Thus a tertiary purpose of the Summer Workshop is to build an educational network of LANL researchers, university professors, and emerging students to advance the field and LANL’s involvement in it. This was the second year for the Summer Workshop. Like the previous year, the workshop’s goals were achieved by bringing into LANL a select group of students recruited from across the United States and immersing them for ten weeks in lectures and interesting research projects. The lectures provided an overview of the computational physics topics of interest this year along with some detailed instruction while the projects gave the students a positive experience accomplishing technical goals. Each team consisted of two students working under one or more mentors from LANL on specific research projects associated with predefined topics. This year, the topics were on verification of simulations in plasma and radiation-hydrodynamics codes, hypervelocity material deformation, plasma physics, graphical processor unit (“GPU”) programming, multi-material mixing, turbulence modeling, computational material science, and electromagnetic pulse simulations. The students’ growth was furthered by their participation on teams where their teammates were sometimes of different academic rank. It also developed them by requiring them to produce written and oral reports that they presented to peers, mentors, and management.

97 MATHEMATICS AND COMPUTING↗

Simulating non-native cubic interactions on noisy quantum machines

As a milestone for general-purpose computing machines, we demonstrate that quantum processors can be programed to efficiently simulate dynamics that are not native to the hardware. Moreover, on noisy devices without error correction, we show that simulation results are significantly improved when the quantum program is compiled using modular gates instead of a restricted set of standard gates. We demonstrate the general methodology by solving a cubic interaction problem, which appears in nonlinear optics, gauge theories, as well as plasma and fluid dynamics. To encode the non-native Hamiltonian evolution, we decompose the Hilbert space into a direct sum of invariant subspaces in which the nonlinear problem is mapped to a finite-dimensional Hamiltonian simulation problem. Furthermore, in a three-states example, the resultant unitary evolution is realized by a product of approximately 20 standard gates, using which approximately ten simulation steps can be carried out on state-of-the-art quantum hardware before results are corrupted by decoherence. In comparison, the simulation depth is improved by more than an order of magnitude when the unitary evolution is realized as a single cubic gate, which is compiled directly using optimal control. Alternatively, parametric gates may also be compiled by interpolating control pulses. Modular gates thus obtained provide high-fidelity building blocks for quantum Hamiltonian simulations.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

Systems and methods for detection of occupancy using radio waves

Systems and methods are disclosed for detecting a presence of a person in an area of coverage using radar. A transmitter can transmit radio signals in a first direction in an area of coverage defined by a wall and a floor. A receiver can receive the transmitted radio signals reflected back from the area of coverage. A signal conditioning circuit can process the received radio signals. One or more hardware processors can be programmed to analyze the processed radio signals and detect a presence of a person in the area of coverage based on the analysis. The analysis of the processed signals can be performed in both time and frequency domain. In addition to radar, an input from an infrared sensor can also be used in conjunction with radar based detection.

42 ENGINEERING↗

An Early Quantum Computing Proposal

The D-Wave 2X is the third generation of quantum processing created by D-Wave. NASA (with Google and USRA) and Lockheed Martin (with USC), both own D-Wave systems. Los Alamos National Laboratory (LANL) purchased a D-Wave 2X in November 2015. The D-Wave 2X processor contains (nominally) 1152 quantum bits (or qubits) and is designed to specifically perform quantum annealing, which is a well-known method for finding a global minimum of an optimization problem. This methodology is based on direct execution of a quantum evolution in experimental quantum hardware. While this can be a powerful method for solving particular kinds of problems, it also means that the D-Wave 2X processor is not a general computing processor and cannot be programmed to perform a wide variety of tasks. It is a highly specialized processor, well beyond what NNSA currently thinks of as an “advanced architecture.”A D-Wave is best described as a quantum optimizer. That is, it uses quantum superposition to find the lowest energy state of a system by repeated doses of power and settling stages. The D-Wave produces multiple solutions to any suitably formulated problem, one of which is the lowest energy state solution (global minimum). Mapping problems onto the D-Wave requires defining an objective function to be minimized and then encoding that function in the Hamiltonian of the D-Wave system. The quantum annealing method is then used to find the lowest energy configuration of the Hamiltonian using the current D-Wave Two, two-level, quantum processor. This is not always an easy thing to do, and the D-Wave Two has significant limitations that restrict problem sizes that can be run and algorithmic choices that can be made. Furthermore, as more people are exploring this technology, it has become clear that it is very difficult to come up with general approaches to optimization that can both utilize the D-Wave and that can do better than highly developed algorithms on conventional computers for specific applications. These are all fundamental challenges that must be overcome for the D-Wave, or similar, quantum computing technology to be broadly applicable.

97 MATHEMATICS AND COMPUTING↗

Locality-aware and sharing-aware cache coherence for collections of processors

A cache coherence technique for operating a multi-processor system including shared memory includes allocating a cache line of a cache memory of a processor to a memory address in the shared memory in response to execution of an instruction of a program executing on the processor. The technique includes encoding a shared information state of the cache line to indicate whether the memory address is a shared memory address shared by the processor and a second processor, or a private memory address private to the processor, in response to whether the instruction is included in a critical section of the program, the critical section being a portion of the program that confines access to shared, writeable data.

Farmahini Farahani, Amin↗

Implementation and Demonstration of P4 Software for Improving ICS Protocol Visibility and Control [Slides]

No prior enabling funded work applicable to this proposal. Programming Protocol-independent Packet Processors (P4) is an open source, domain-specific programming language for network switching devices. P4 complements traditional Software Defined Networking (SDN) which is primarily concerned with the management of packets (e.g. routing/dropping decisions) rather than how each packet is processed. The introduction of P4 provided new capabilities (e.g. firewall, load balancing, enhanced security) but has primarily been deployed in data centers. This effort investigates ways to expand P4 into other niches such as ICS networks.

97 MATHEMATICS AND COMPUTING↗

Equilipy

There is high demand for high-throughput calculations of phase equilibria based on the CALPHAD method (CALculation of PHAse Diagram). High-throughput calculations are possible through HPC, currently by a commercial program called Thermo-Calc. However, the number of nodes/processors are limited to the number of purchased license (16 processors per license). This program provides a toolkit for high-throughput calculations of phase equilibria by the CALPHAD method. The program is prepared for Python environment, so that it can be easily installed and used together with other open-source programs. The program can be run in supercomputer.

Kwon, Sunyong [Oak Ridge National Laboratory (ORNL↗

Near-optimal routing of noisy quantum states

Placement, routing, and scheduling are essential tasks for near-optimal performance of programs for noisy quantum processors. Reliable execution of an arbitrary quantum circuit on current devices requires routing methods that overcome connectivity limitations while meeting data locality requirements. However, current devices also express highly variable noise levels in both the quantum gates and quantum registers. This requires any routing algorithm to be adaptive to both the circuit and the operating conditions. We demonstrate near-optimal routing methods of noisy quantum states that minimize the overall error of data movement while also limiting the computational complexity of routing decisions. We evaluate our methods against the noise characteristics of a 20-qubit superconducting quantum processor.

Sadlier III, Ronald↗

Data processing with microcode designed with source coding

Programming for a data processor to execute a data processing application is provided using microcode source code. The microcode source code is assembled to produce microcode that includes digital microcode instructions with which to signal the data processor to execute the data processing application.

97 MATHEMATICS AND COMPUTING↗

Method and apparatus for real-time measurement of fuel gas compositions and heating values

An exemplary embodiment can be an apparatus for real-time, in situ measurement of gas compositions and heating values. The apparatus includes a near infrared sensor for measuring concentrations of hydrocarbons and carbon dioxide, a mid infrared sensor for measuring concentrations of carbon monoxide and a semiconductor based sensor for measuring concentrations of hydrogen gas. A data processor having a computer program for reducing the effects of cross-sensitivities of the sensors to components other than target components of the sensors is also included. Also provided are corresponding or associated methods for real-time, in situ determination of a composition and heating value of a fuel gas.

03 NATURAL GAS↗

Subsea processor for underwater drilling operations

A subsea processor may be located near the seabed of a drilling site and used to coordinate operations of underwater drilling components. The subsea processor may be enclosed in a single interchangeable unit that fits a receptor on an underwater drilling component, such as a blow-out preventer (BOP). The subsea processor may issue commands to control the BOP and receive measurements from sensors located throughout the BOP. The subsea processor may relay information to the surface for recording or monitoring. The subsea processor may also be programmed with a model from which to base operation of the BOP, such as in emergency conditions.

42 ENGINEERING↗

Method and apparatus for real time, in situ sensing and characterization of roughness, geometrical shapes, geometrical structures, composition, defects, and temperature in three-dimensional manufacturing systems

Methods and apparatuses for manufacturing are disclosed, including (a) providing an apparatus having: a laser; scanner; powder injection system; powder spreading system; dichroic filter; imager-and-processor; and computer; (b) programming the computer with specifications of a sample; (c) using the computer to set initial parameters based on the sample specifications; (d) adjusting a stage to position the sample; (e) focusing and scanning electromagnetic radiation onto the sample while powder is concurrently injected onto the sample in order to deposit a layer; (f) capturing two-dimensional images of the sample and probing the sample to determine whether the deposited layer was manufactured per the specifications; (g) use the computer to adjust the three-dimensional manufacturing parameters based on the determination made in step (f) prior to additively manufacturing a subsequent layer or making repairs; and (h) repeating steps (d), (e), (f), and (g) until the manufacture is complete. Other embodiments are described and claimed.

Liu, Jian↗

A preliminary user-friendly, digital console for the control room parameters supervision in old-generation Nuclear Plants

Improvements in the awareness of a system status is an essential requirement to achieve safety in every kind of plant. In particular, in the case of Nuclear Power Plants (NPPs), a progress is crucial to enhance the Human Machine Interface (HMI) in order to optimize monitoring and analyzing processes of NPP operational states. Firstly, as old-fashioned plants are concerned, an upgrading of the whole console instrumentation is desirable in order to replace an analog visualization with a full-digital system. In this work, we present a novel instrument able to interface the control console of a nuclear reactor, developed by using CompactRio, a National Instruments embedded architecture and its dedicated programming language. This real-time industrial controller composed by a real-time processor and FPGA modules has been programmed to visualize the parameters coming from the reactor, and to storage and reproduce significant conditions anytime. This choice has been made on the basis of the FPGA properties: high reliability, determinism, true parallelism and re-configurability, achieved by a simple programming method, based on LabVIEW real-time environment. The system architecture exploits the FPGA capabilities of implementing custom timing and triggering, hardware-based analysis and co-processing, and highest performance control algorithms. Data stored during the supervisory phase can be reproduced by loading data from a measurement file, re-enacting worthwhile operations or conditions. The system has been thought to be used in three different modes, namely Log File Mode, Supervisory Mode and Simulation Mode. The proposed system can be considered as a first step to develop a more complete Decision Support System (DSS): indeed this work is part of a wider project that includes the elaboration of intelligent agents and meta-theory approaches. A synoptic has been created to monitor every kind of action on the plant through an intuitive sight. Furthermore, another important aim of this work is the possibility to have a front panel available on a web interface: CompactRio acts as a remote server and it is accessible on a dedicated LAN. This supervisory system has been tested and validated on the basis of the real control console for the 1-MW TRIGA reactor RC-1 at the ENEA, Casaccia Research Center. In this paper we show some results obtained by recording each variable as the reactor reaches its maximum level of power. The choice of a research reactor for testing the developed system relies on its training and didactic importance for the education of plant operators: in this context a digital instrument can offer a better user-friendly tool for learning and training. It is worthwhile to remark that such a system does not interfere with the console instrumentation, the latter continuing to preserve the total control. (authors)

22 GENERAL STUDIES OF NUCLEAR REACTORS↗

Computer systems and methods for the query and visualization multidimensional databases

A method of generating a data visualization is performed at a computer having a display, one or more processors, and memory. The memory stores one or more programs for execution by the one or more processors. The process receives user specification of a plurality of characteristics of a data visualization. The data visualization is based on data from a multidimensional database. The characteristics specify at least x-position and y-position of data marks corresponding to tuples of data retrieved from the database. The process generates a data visualization according to the specified plurality of characteristics. The data visualization has an x-axis defined based on data for one or more first fields from the database that specify x-position of the data marks and the data visualization has a y-axis defined based on data for one or more second fields from the database that specify y-position of the data marks.

97 MATHEMATICS AND COMPUTING↗

Shared performance monitor in a multiprocessor system

A performance monitoring unit (PMU) and method for monitoring performance of events occurring in a multiprocessor system. The multiprocessor system comprises a plurality of processor devices units, each processor device for generating signals representing occurrences of events in the processor device, and, a single shared counter resource for performance monitoring. The performance monitor unit is shared by all processor cores in the multiprocessor system. The PMU comprises: a plurality of performance counters each for counting signals representing occurrences of events from one or more the plurality of processor units in the multiprocessor system; and, a plurality of input devices for receiving the event signals from one or more processor devices of the plurality of processor units, the plurality of input devices programmable to select event signals for receipt by one or more of the plurality of performance counters for counting, wherein the PMU is shared between multiple processing units, or within a group of processors in the multiprocessing system. The PMU is further programmed to monitor event signals issued from non-processor devices.

97 MATHEMATICS AND COMPUTING↗

A Principled Kernel Testbed for Hardware/Software Co-Design Research

Recently, advances in processor architecture have become the driving force for new programming models in the computing industry, as ever newer multicore processor designs with increasing number of cores are introduced on schedules regimented by marketing demands. As a result, collaborative parallel (rather than simply concurrent) implementations of important applications, programming languages, models, and even algorithms have been forced to adapt to these architectures to exploit the available raw performance. We believe that this optimization regime is flawed. In this paper, we present an alternate approach that, rather than starting with an existing hardware/software solution laced with hidden assumptions, defines the computational problems of interest and invites architects, researchers and programmers to implement novel hardware/software co-designed solutions. Our work builds on the previous ideas of computational dwarfs, motifs, and parallel patterns by selecting a representative set of essential problems for which we provide: An algorithmic description; scalable problem definition; illustrative reference implementations; verification schemes. This testbed will enable comparative research in areas such as parallel programming models, languages, auto-tuning, and hardware/software codesign. For simplicity, we focus initially on the computational problems of interest to the scientific computing community but proclaim the methodology (and perhaps a subset of the problems) as applicable to other communities. We intend to broaden the coverage of this problem space through stronger community involvement.

96 KNOWLEDGE MANAGEMENT AND PRESERVATION↗

A Survey of Techniques for Approximate Computing

Approximate computing trades off computation quality with the effort expended and as rising performance demands confront with plateauing resource budgets, approximate computing has become, not merely attractive, but even imperative. Here, we present a survey of techniques for approximate computing (AC). We discuss strategies for finding approximable program portions and monitoring output quality, techniques for using AC in different processing units (e.g., CPU, GPU and FPGA), processor components, memory technologies etc., and programming frameworks for AC. Moreover, we classify these techniques based on several key characteristics to emphasize their similarities and differences. Finally, the aim of this paper is to provide insights to researchers into working of AC techniques and inspire more efforts in this area to make AC the mainstream computing approach in future systems.

97 MATHEMATICS AND COMPUTING↗

Operating Systems Support for Advanced Programming Languages

As machines grow in scale and complexity, techniques to make the most effective use of network, memory, and processor resources will also become increasingly important. Programming models that rely on one-sided communication or global address space support have demonstrated advantages for productivity and performance, but they are most effective when used with proper OS support. We propose to develop OS and runtime support for programming models like UPC, GA, Charm++, and HPCS languages, which rely on one-sided communication. Rather than a full OS model, we envision applications bundled with only the necessary OS functions linked in to the application in user space -- relying on the hypervisor for protaction, resource sharing, and mangagement of Quality of Service guarantees. Our services will include support for remote reads and writes to memory, along with remote active message handlers, which are essential for support of fast noncontiguous memory operations, atomic operations, and event-driven applications.

97 MATHEMATICS AND COMPUTING↗