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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
NASA NTRS2004

Lab-On-a-Chip Application Development (LOCAD): Bridging Technology Readiness for Exploration

At Marshall Space Flight Center we have established a capability to investigate the use of microfluidics for space flight. The Lab-On-a-Chip Application Development (LOCAD) team has created a program for advancing Technology Readiness Levels (TRL) of 1 and 2 to TRL 6 and 7, quickly and economically for Lab-On-a-Chip (LOC) applications. Scientists and engineers can utilize LOCAD'S process to efficiently learn about microfluidics and determine if microfluidics is applicable to their needs. Once the applicability has been determined, LOCAD can then perform tests to develop the new fluidic protocols which are different from macro-scale chemical reaction protocols. With this information new micro-fluidic devices can be created and tested. Currently, LOCAD is focused on using microfluidics for both Environmental Monitoring & Control, and Medical Systems. Eventually, handheld portable units utilizing LOC technology will perform rapid tests to determine water quality, and microbial contamination levels. Since LOC technology is drastically reduced in physical size, it thereby reduces power, weight, volume, and sample requirements, a big advantage considering the resource constraints associated with spaceflight. Another one of LOCAD's current activities is the development of a microfluidic system to aid in the search for life on Mars.

Spearing, Scott F.↗
NASA NTRS2009

OP09O-OP404-9 Wide Field Camera 3 CCD Quantum Efficiency Hysteresis

The HST/Wide Field Camera (WFC) 3 UV/visible channel CCD detectors have exhibited an unanticipated quantum efficiency hysteresis (QEH) behavior. At the nominal operating temperature of -83C, the QEH feature contrast was typically 0.1-0.2% or less. The behavior was replicated using flight spare detectors. A visible light flat-field (540nm) with a several times full-well signal level can pin the detectors at both optical (600nm) and near-UV (230nm) wavelengths, suppressing the QEH behavior. We are characterizing the timescale for the detectors to become unpinned and developing a protocol for flashing the WFC3 CCDs with the instrument's internal calibration system in flight. The HST/Wide Field Camera 3 UV/visible channel CCD detectors have exhibited an unanticipated quantum efficiency hysteresis (QEH) behavior. The first observed manifestation of QEH was the presence in a small percentage of flat-field images of a bowtie-shaped contrast that spanned the width of each chip. At the nominal operating temperature of -83C, the contrast observed for this feature was typically 0.1-0.2% or less, though at warmer temperatures contrasts up to 5% (at -50C) have been observed. The bowtie morphology was replicated using flight spare detectors in tests at the GSFC Detector Characterization Laboratory by power cycling the detector while cold. Continued investigation revealed that a clearly-related global QE suppression at the approximately 5% level can be produced by cooling the detector in the dark; subsequent flat-field exposures at a constant illumination show asymptotically increasing response. This QE "pinning" can be achieved with a single high signal flat-field or a series of lower signal flats; a visible light (500-580nm) flat-field with a signal level of several hundred thousand electrons per pixel is sufficient for QE pinning at both optical (600nm) and near-UV (230nm) wavelengths. We are characterizing the timescale for the detectors to become unpinned and developing a protocol for flashing the WFC3 CCDs with the instrument's internal calibration system in flight. A preliminary estimate of the decay timescale for one detector is that a drop of 0.1-0.2% occurs over a ten day period, indicating that relatively infrequent cal lamp exposures can mitigate the behavior to extremely low levels.

Collins, Nick↗
NASA NTRS2006

BAE Systems Radiation Hardened SpaceWire ASIC and Roadmap

An Application Specific Integrated Circuit (ASIC) that implements the SpaceWire protocol has been developed in a radiation hardened 0.25 micron CMOS, technology. This effort began in March 2003 as a joint development between the NASA Goddard Space Flight Center (GSFC) and BAE Systems. The BAE Systems SpaceWire ASlC is comprised entirely of reusable core elements, many of which are already flight-proven. It incorporates a 4-port SpaceWire router with two local ports, dual PC1 bus interfaces, a microcontroller, 32KB of internal memory, -and a memory controller for additional external memory use. The SpaceWire ASlC is planned for use on both the Geostationary Operational Environmental Satellites (GOES)-R and the Lunar Reconnaissance Orbiter (LRO). Engineering parts have already been delivered to both programs. This paper discusses the SpaceWire protocol and those elements of it that have been built into the current SpaceWire reusable core. There are features within the core that go beyond the current standard that can be enabled or disabled by the user and these will be described. The adaptation of SpaceWire to BAE Systems' On Chip Bus (OCB) for compatibility with the other reusable cores will be discussed. Optional configurations within user systems will be shown. The physical imp!ementation of the design will be described and test results from the hardware will be discussed. Finally, the BAE Systems roadmap for SpaceWire developments will be discussed, including some products already in design as well as longer term plans.

Berger, Richard↗
DOE OSTI2024

Automated Lane Centering: An Off-the-Shelf Computer Vision Product vs. Infrastructure-Based Chip-Enabled Raised Pavement Markers

Safe autonomous vehicle (AV) operations depend on an accurate perception of the driving environment, which necessitates the use of a variety of sensors. Computational algorithms must then process all of this sensor data, which typically results in a high on-vehicle computational load. For example, existing lane markings are designed for human drivers, can fade over time, and can be contradictory in construction zones, which require specialized sensing and computational processing in an AV. But, this standard process can be avoided if the lane information is simply transmitted directly to the AV. High definition maps and road side units (RSUs) can be used for direct data transmission to the AV, but can be prohibitively expensive to establish and maintain. Additionally, to ensure robust and safe AV operations, more redundancy is beneficial. A cost-effective and passive solution is essential to address this need effectively. In this research, we propose a new infrastructure information source (IIS), chip-enabled raised pavement markers (CERPMs), which provide environmental data to the AV while also decreasing the AV compute load and the associated increase in vehicle energy use. CERPMs are installed in place of traditional ubiquitous raised pavement markers along road lane lines to transmit geospatial information along with the speed limit using long range wide area network (LoRaWAN) protocol directly to nearby vehicles. This information is then compared to the Mobileye commercial off-the-shelf traditional system that uses computer vision processing of lane markings. Our perception subsystem processes the raw data from both CEPRMs and Mobileye to generate a viable path required for a lane centering (LC) application. To evaluate the detection performance of both systems, we consider three test routes with varying conditions. Our results show that the Mobileye system failed to detect lane markings when the road curvature exceeded ±0.016 m -1 . For the steep curvature test scenario, it could only detect lane markings on both sides of the road for just 6.7% of the given test route. On the other hand, the CERPMs transmit the programmed geospatial information to the perception subsystem on the vehicle to generate a reference trajectory required for vehicle control. The CERPMs successfully generated the reference trajectory for vehicle control in all test scenarios. Moreover, the CERPMs can be detected up to 340 m from the vehicle’s position. Our overall conclusion is that CERPM technology is viable and that it has the potential to address the operational robustness and energy efficiency concerns plaguing the current generation of AVs.

33 ADVANCED PROPULSION SYSTEMS↗
NASA NTRS1987

Command/response protocols and concurrent software

A version of the program to control the parallel jaw gripper is documented. The parallel jaw end-effector hardware and the Intel 8031 processor that is used to control the end-effector are briefly described. A general overview of the controller program is given and a complete description of the program's structure and design are contained. There are three appendices: a memory map of the on-chip RAM, a cross-reference listing of the self-scheduling routines, and a summary of the top-level and monitor commands.

Bynum, W. L.↗
DOE OSTI2024

Qubit-Based Detector For Dark Matter Search And Radiation Studies

One of the challenges in exploring promising novel materials for dark matter searches is the detection of sub-eV energy excitations from light-dark matter interaction with a target material. Dark matter interaction can excite sub-eV optical phonon modes in polar materials like sapphire. We plan to utilize superconducting qubits on a sapphire substrate to study their response to energy deposition into the superconducting film and the substrate by irradiating them with photons and particles and also generating phonons in the chip. A fraction of the incident energy is expected to break Cooper pairs in the superconductor, releasing quasiparticles. As the quasiparticles tunnel across the Josephson junction, the charge parity of the qubit changes. The parity switching rate is proportional to the quasiparticle density in the qubit superconductor film and can be measured using standard qubit readout protocol. This presentation describes our ongoing attempt to build such a prototype detector.

Khatiwada, Rakshya↗
DOE OSTI2021

XVC FTDI JTAG v1.0

the Xilinx tools relay on a component on the board (FTDI chip) to have a small memory from a particular manufacturer (Digilent) to serve as a bridge to the FPGA. What the software we're requesting to release simply does is to run between the Xilinx tools (one of them is called Vivado but there are others) and our boards so that we don't need that memory on our boards. The protocol the software uses to communicate with the Xilinx tools is called XVC (Xilinx Virtual Cable). This server code runs on the computer that is physically connected to the FPGA board, but the Xilinx tools that communicate with it can run either on that computer or some other computer connected to it over the network, this is where the network component comes into play.

Norum, William↗
DOE OSTI2020

Experimental Passive-State Preparation for Continuous-Variable Quantum Communications

In the Gaussian-modulated coherent state quantum key distribution (QKD) protocol, the sender first generates Gaussian-distributed random numbers and then encodes them on weak laser pulses actively by performing amplitude and phase modulations. Recently, an equivalent passive QKD scheme has been proposed by exploring the intrinsic field fluctuations of a thermal source [B. Qi, P. G. Evans, and W. P. Grice, Phys. Rev. A 97, 012317 (2018)]. This passive QKD scheme is especially appealing for chip-scale implementation since no active modulation is required. In this paper, we conduct an experimental study of the passively encoded QKD scheme using an off-the-shelf amplified spontaneous emission source operated in continuous-wave mode. Our results show that the excess noise introduced by the passive state preparation scheme can be effectively suppressed by applying optical attenuation and a secure key can be generated over metro-area distances.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
NASA NTRS2015

Wireless Sensor Node for Autonomous Monitoring and Alerts in Remote Environments

A method, apparatus, system, and computer program products provides personal alert and tracking capabilities using one or more nodes. Each node includes radio transceiver chips operating at different frequency ranges, a power amplifier, sensors, a display, and embedded software. The chips enable the node to operate as either a mobile sensor node or a relay base station node while providing a long distance relay link between nodes. The power amplifier enables a line-of-sight communication between the one or more nodes. The sensors provide a GPS signal, temperature, and accelerometer information (used to trigger an alert condition). The embedded software captures and processes the sensor information, provides a multi-hop packet routing protocol to relay the sensor information to and receive alert information from a command center, and to display the alert information on the display.

Monacos, Steve P.↗
DOE OSTI2024

Strain-concentration for fast, compact photonic modulation and non-volatile memory

A critical figure of merit (FoM) for electro-optic (EO) modulators is the transmission change per voltage, d T / d V . Conventional approaches in wave-guided modulators maximize d T / d V via a high EO coefficient or longer light-material interaction lengths but are ultimately limited by material losses and nonlinearities. Optical and RF resonances improve d T / d V at the cost of spectral non-uniformity, especially for high- Q optical cavity resonances. Here, we introduce an EO modulator based on piezo-strain-concentration of a photonic crystal cavity to address both trade-offs: (i) it eliminates the trade-off between d T / d V and waveguide loss—i.e., enhancement of the resonance tuning efficiency d v c / d V for the fixed EO coefficient, waveguide length, and cavity Q —and (ii) at high DC strains it exhibits a non-volatile (NV) cavity tuning Δ v c ,NV for passive memory and programming of multiple devices into resonance despite fabrication variations. The device is fabricated on a scalable silicon nitride-on-aluminum nitride platform. We measure d v c / d V =177±1MHz/V, corresponding to Δ v c =40±0.32GHz for a voltage spanning ±120V with an energy consumption of δ U /Δ v c =0.17nW/GHz. The modulation bandwidth is flat up to ω BW,3dB /2 π =3.2±0.07MHz for broadband DC-AC and 142±17MHz for resonant operation near a 2.8 GHz mechanical resonance. Optical extinction up to 25 dB is obtained via Fano-type interference. Strain-induced beam-buckling modes are programmable under a “read-write” protocol with a continuous, repeatable tuning range of 5±0.25GHz, allowing for storage and retrieval, which we quantify with mutual information of 2.4 bits and a maximum non-volatile excursion of 8 GHz. Using a full piezo-optical finite-element-model (FEM) we identify key design principles for optimizing strain-based modulators and chart a path towards achieving performance comparable to lithium niobate-based modulators and the study of high strain physics on-chip.

Wen, Y. Henry (ORCID:0009000685423628)↗
NASA NTRS2013

NASA Tech Briefs, August 2013

Topics covered include: Radial Internal Material Handling System (RIMS) for Circular Habitat Volumes; Conical Seat Shut-Off Valve; Impact-Actuated Digging Tool for Lunar Excavation; Flexible Mechanical Conveyors for Regolith Extraction and Transport; Remote Memory Access Protocol Target Node Intellectual Property; Soft Decision Analyzer; Distributed Prognostics and Health Management with a Wireless Network Architecture; Minimal Power Latch for Single-Slope ADCs; Bismuth Passivation Technique for High-Resolution X-Ray Detectors; High-Strength, Super-elastic Compounds; Cu-Cr-Nb-Zr Alloy for Rocket Engines and Other High-Heat- Flux Applications; Microgravity Storage Vessels and Conveying-Line Feeders for Cohesive Regolith; CRUQS: A Miniature Fine Sun Sensor for Nanosatellites; On-Chip Microfluidic Components for In Situ Analysis, Separation, and Detection of Amino Acids; Spectroscopic Determination of Trace Contaminants in High-Purity Oxygen; Method of Separating Oxygen From Spacecraft Cabin Air to Enable Extravehicular Activities; Atomic Force Microscope Mediated Chromatography; Sample Analysis at Mars Instrument Simulator; Access Control of Web- and Java-Based Applications; Tool for Automated Retrieval of Generic Event Tracks (TARGET); Bilayer Protograph Codes for Half-Duplex Relay Channels; Influence of Computational Drop Representation in LES of a Droplet-Laden Mixing Layer.

Source record↗
DOE OSTI2022

The QICK (Quantum Instrumentation Control Kit): Readout and control for qubits and detectors

We introduce a Xilinx RF System-on-Chip (RFSoC)-based qubit controller (called the Quantum Instrumentation Control Kit, or QICK for short), which supports the direct synthesis of control pulses with carrier frequencies of up to 6 GHz. The QICK can control multiple qubits or other quantum devices. The QICK consists of a digital board hosting an RFSoC field-programmable gate array, custom firmware, and software and an optional companion custom-designed analog front-end board. We characterize the analog performance of the system as well as its digital latency, important for quantum error correction and feedback protocols. We benchmark the controller by performing standard characterizations of a transmon qubit. We achieve an average gate fidelity of ℱ avg =99.93%. All of the schematics, firmware, and software are open-source.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
NASA NTRS1992

Circuit design tool. User's manual, revision 2

The CAM chip design was produced in a UNIX software environment using a design tool that supports definition of digital electronic modules, composition of these modules into higher level circuits, and event-driven simulation of these circuits. Our design tool provides an interface whose goals include straightforward but flexible primitive module definition and circuit composition, efficient simulation, and a debugging environment that facilitates design verification and alteration. The tool provides a set of primitive modules which can be composed into higher level circuits. Each module is a C-language subroutine that uses a set of interface protocols understood by the design tool. Primitives can be altered simply by recoding their C-code image; in addition new primitives can be added allowing higher level circuits to be described in C-code rather than as a composition of primitive modules--this feature can greatly enhance the speed of simulation.

Miyake, Keith M.↗
DOE OSTI2021

A 24-Channel Digitizer With a JESD204B-Compliant Serial Interface for High-Speed Detectors

In this report a 24-channel application-specific integrated circuit (ASIC) for the readout of high-speed CMOS active pixel sensors for charged particle detection is presented. The chip comprises 24 preamplifiers, 24 distinct 12-bit, 25 MSPS Pipelined analog-to-digital converters (ADCs) with self-calibration, an internal phase-locked loop (PLL), and a 3 Gbps serial interface that conforms to the JESD204B standard. To simplify interfacing with a variety of sensors, the ASIC also includes an automatic offset calibration loop. The high level of integration of the ASIC reduces overall system cost and area, and exploiting the signal characteristics of the image sensor allows the ADC to be optimized for reduced power dissipation. The use of an integrated serializer and an industry standard protocol simplifies integration of the ASIC into a complete camera system. The ASIC, called the High-Speed Image Preprocessor Targeted for Electron Readout, or HIPSTER, with a die area of 64.26 mm 2 , is packaged in a 480-ball grid array (BGA) and is fabricated in 180-nm CMOS technology. HIPSTER achieves typical differential nonlinearity (DNL) < 0.55 LSB, input-referred thermal noise of $114.5 μV-rms, and a bit error rate (BER) of better than 10-14. The power dissipation is 98 mW/channel.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
NASA NTRS2012

High Energy/LET Radiation EEE Parts Certification Handbook

Certifying electronic components is a very involved process. It includes pre-coordination with the radiation test facility for time, schedule and cost, as well as intimate work with designers to develop test procedures and hardware. It also involves work with radiation engineers to understand the effects of the radiation field on the test article/setup as well as the analysis and production of a test report. The technical content of traditional ionizing radiation testing protocol is in wide use and generally follows established standards (ref. Appendix C). This document is not intended to cover all these areas but to cover the methodology of using Variable Depth Bragg Peak (VDBP) to accomplish the goal of characterizing an electronic component. The Variable Depth Bragg Peak (VDBP) test method is primarily used for deep space applications of electronics. However, it can be used on any part for any radiation environment, especially those parts where the sensitive volume cannot be reached by the radiation beam. An example of this problem would be issues that arise in de-lidding of parts or in parts with flip-chip designs, etc. The VDBP method is ideally suited to test modern avionics designs which increasingly incorporate commercial off-the-shelf (COTS) parts and units. Johnson Space Center (JSC) developed software provides assistance to users in developing the radiation characterization data from the raw test data.

Reddell, Brandon↗
DOE OSTI2021

Isolation of Histone from Sorghum Leaf Tissue for Top Down Mass Spectrometry Profiling of Potential Epigenetic Markers

Histones belong to a family of highly conserved proteins in eukaryotes. They pack DNA into nucleosomes as functional units of chromatin. Post-translational modifications (PTMs) of histones, which are highly dynamic and can be added or removed by enzymes, play critical roles in regulating gene expression. In plants, epigenetic factors including histone PTMs are related to their adaptive responses to the environment. Understanding the molecular mechanisms of epigenetic control can bring unprecedented opportunities for engineering solutions to increase the resilience of crops to climate change. Herein, we describe a protocol to isolate the nuclei and purify histones from sorghum leaf tissue. The extracted histones can be analyzed as their intact forms by top-down mass spectrometry (MS) coupled to online reversed-phase (RP) liquid chromatography (LC). Combinations and stoichiometry of multiple PTMs on the same histone proteoform can be readily identified. In addition, histone tail clipping can be detected using the top-down LC-MS workflow thus yielding the global PTM profile of core histones (H4, H2A, H2B, H3). By comparing the PTM profile among samples corresponding to different conditions (e.g. drought vs. control), potential epigenetic marks can be discovered as targets for further characterization using approaches such as chromatin immunoprecipitation – sequencing (ChIP-seq).

59 BASIC BIOLOGICAL SCIENCES↗
DOE OSTI2020

A 20 Gbps Data Transmitting ASIC with PAM4 for Particle Physics Experiments

We present the design principle and test results of a data transmitting ASIC, GBS20, for particle physics experiments. The goal of GBS20 will be an ASIC that employs two serializers each from the 10.24 Gbps lpGBT SerDes, sharing the PLL also from lpGBT. A PAM4 encoder plus a VCSEL driver will be implemented in the same die to use the same clock system, eliminating the need of CDRs in the PAM4 encoder. This way the transmitter module, GBT20, developed using the GBS20 ASIC, will have the exact lpGBT data interface and transmission protocol, with an output up to 20.48 Gbps over one fiber. With PAM4 embedded FPGAs at the receiving end, GBT20 will halve the fibers needed in a system and better use the input bandwidth of the FPGA. A prototype, GBS20v0 is fabricated using a commercial 65 nm CMOS technology. This prototype has two serializers and a PAM4 encoder sharing the lpGBT PLL, but no user data input. An internal PRBS generator provides data to the serializers. GBS20v0 is tested barely up to 20.48 Gbps. With lessons learned from this prototype, we are designing the second prototype, GBS20v1, that will have 16 user data input channels each at 1.28 Gbps. We present the design concept of the GBS20 ASIC and the GBT20 module, the preliminary test results, and lessons learned from GBS20v0 and the design of GBS20v1 which will be not only a test chip but also a user chip with 16 input data channels.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
NASA NTRS1992

The VLBA correlator: Real-time in the distributed era

The correlator is the signal processing engine of the Very Long Baseline Array (VLBA). Radio signals are recorded on special wideband (128 Mb/s) digital recorders at the 10 telescopes, with sampling times controlled by hydrogen maser clocks. The magnetic tapes are shipped to the Array Operations Center in Socorro, New Mexico, where they are played back simultaneously into the correlator. Real-time software and firmware controls the playback drives to achieve synchronization, compute models of the wavefront delay, control the numerous modules of the correlator, and record FITS files of the fringe visibilities at the back-end of the correlator. In addition to the more than 3000 custom VLSI chips which handle the massive data flow of the signal processing, the correlator contains a total of more than 100 programmable computers, 8-, 16- and 32-bit CPUs. Code is downloaded into front-end CPU's dependent on operating mode. Low-level code is assembly language, high-level code is C running under a RT OS. We use VxWorks on Motorola MVME147 CPU's. Code development is on a complex of SPARC workstations connected to the RT CPU's by Ethernet. The overall management of the correlation process is dependent on a database management system. We use Ingres running on a Sparcstation-2. We transfer logging information from the database of the VLBA Monitor and Control System to our database using Ingres/NET. Job scripts are computed and are transferred to the real-time computers using NFS, and correlation job execution logs and status flow back by the route. Operator status and control displays use windows on workstations, interfaced to the real-time processes by network protocols. The extensive network protocol support provided by VxWorks is invaluable. The VLBA Correlator's dependence on network protocols is an example of the radical transformation of the real-time world over the past five years. Real-time is becoming more like conventional computing. Paradoxically, 'conventional' computing is also adopting practices from the real-time world: semaphores, shared memory, light-weight threads, and concurrency. This appears to be a convergence of thinking.

Wells, D. C.↗