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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
DOE OSTI2021

Toroidal polar topology in strained ferroelectric polymer

Polar topological texture has become an emerging research field for exotic phenomena and potential applications in reconfigurable electronic devices. Here, we report toroidal topological texture self-organized in a ferroelectric polymer, poly(vinylidene fluoride-ran-trifluoroethylene) [P(VDF-TrFE)], that exhibits concentric topology with anticoupled chiral domains. The interplay among the elastic, electric, and gradient energies results in continuous rotation and toroidal assembly of the polarization perpendicular to polymer chains, whereas relaxor behavior is induced along polymer chains. Such toroidal polar topology gives rise to periodic absorption of polarized far-infrared (FIR) waves, enabling the manipulation of the terahertz wave on a mesoscopic scale. Our observations should inform design principles for flexible ferroic materials toward complex topologies and provide opportunities for multistimuli conversions in flexible electronics.

36 MATERIALS SCIENCE↗
NASA NTRS2000

Evolutionary design of smart analog circuits

This paper discusses the use of Evolvable Hardware (EHW) in automatic synthesis of electronic circuits for computational intelligence (CI) hardware.

evolvable hardware fuzzy logic reconfigurable devi↗
NASA NTRS2010

The Application of Ultrasonic Inspection to Crimped Electrical Connections

The development of a new ultrasonic measurement technique to quantitatively assess wire crimp terminations is discussed. The development of a prototype instrument, based on a modified, commercially available, crimp tool, is demonstrated for applying this technique when wire crimps are installed. The crimp tool has three separate crimping locations that accommodate the three different ferrule diameters. The crimp tool in this study is capable of crimping wire diameters ranging from 12 to 26 American Wire Gauge (AWG). A transducer design is presented that allows for interrogation of each of the three crimp locations on the crimp tool without reconfiguring the device. An analysis methodology, based on transmitted ultrasonic energy and timing of the first received pulse is shown to correlate to both crimp location in the tool and the AWG of the crimp/ferrule combination. The detectability of a number of the crimp failure pathologies, such as missing strands, partially inserted wires and incomplete crimp compression, is discussed. A wave propagation model, solved by finite element analysis, describes the compressional ultrasonic wave propagation through the junction during the crimping process.

Cramer, K. Elliott↗
NASA NTRS2011

IONAC-Lite

The Interplanetary Overlay Net - working Protocol Accelerator (IONAC) described previously in The Inter - planetary Overlay Networking Protocol Accelerator (NPO-45584), NASA Tech Briefs, Vol. 32, No. 10, (October 2008) p. 106 (http://www.techbriefs.com/component/ content/article/3317) provides functions that implement the Delay Tolerant Networking (DTN) bundle protocol. New missions that require high-speed downlink-only use of DTN can now be accommodated by the unidirectional IONAC-Lite to support high data rate downlink mission applications. Due to constrained energy resources, a conventional software implementation of the DTN protocol can provide only limited throughput for any given reasonable energy consumption rate. The IONAC-Lite DTN Protocol Accelerator is able to reduce this energy consumption by an order of magnitude and increase the throughput capability by two orders of magnitude. In addition, a conventional DTN implementation requires a bundle database with a considerable storage requirement. In very high downlink datarate missions such as near-Earth radar science missions, the storage space utilization needs to be maximized for science data and minimized for communications protocol-related storage needs. The IONAC-Lite DTN Protocol Accelerator is implemented in a reconfigurable hardware device to accomplish exactly what s needed for high-throughput DTN downlink-only scenarios. The following are salient features of the IONAC-Lite implementation: An implementation of the Bundle Protocol for an environment that requires a very high rate bundle egress data rate. The C&DH (command and data handling) subsystem is also expected to be very constrained so the interaction with the C&DH processor and the temporary storage are minimized. Fully pipelined design so that bundle processing database is not required. Implements a lookup table-based approach to eliminate multi-pass processing requirement imposed by the Bundle Protocol header s length field structure and the SDNV (self-delimiting numeric value) data field formatting. 8-bit parallel datapath to support high data-rate missions. Reduced resource utilization implementation for missions that do not require custody transfer features. There was no known implementation of the DTN protocol in a field programmable gate array (FPGA) device prior to the current implementation. The combination of energy and performance optimization that embodies this design makes the work novel.

Torgerson, Jordan L.↗
NASA NTRS2005

Reconfiguration of Analog Electronics for Extreme Environments: Problem or Solution?

This paper argues in favor of adaptive reconfiguration as a technique to expand the operational envelope of analog electronics for extreme environments (EE). In addition to hardening-by-process and hardening-by-design, "hardening-by-reconfiguration", when applicable, could be used to mitigate drifts, degradation, or damage on electronic devices (chips) in EE, by using re-configurable devices and an adaptive self-reconfiguration of their circuit topology. Conventional circuit design exploits device characteristics within a certain temperature/radiation range; when that is exceeded, the circuit function degrades. On a reconfigurable device, although component parameters change in EE, as long as devices still operate, albeit degraded, a new circuit design, suitable for new parameter values, may be mapped into the reconfigurable structure to recover the initial circuit function. Partly degraded resources are still used, while completely damaged resources are bypassed. Designs suitable for various environmental conditions can be determined prior to operation or can be determined in-situ, by adaptive reconfiguration algorithms running on built-in digital controllers. Laboratory demonstrations of this technique were performed by JPL in several independent experiments in which bulk CMOS reconfigurable devices were exposed to, and degraded by, low temperatures (approx. 196 C), high temperatures (approx.300 C) or radiation (300kRad TID), and then recovered by adaptive reconfiguration using evolutionary search algorithms. Taking this technology from Technology Readiness Level (TRL) 3 to TRL 5 is the target of a current NASA project.

Field Programmable Transistor Array (FPTA)↗
NASA NTRS2001

Adaptive Instrument Module: Space Instrument Controller "Brain" through Programmable Logic Devices

The Adaptive Instrument Module (AIM) will be the first true demonstration of reconfigurable computing with field-programmable gate arrays (FPGAs) in space, enabling the 'brain' of the system to evolve or adapt to changing requirements. In partnership with NASA Goddard Space Flight Center and the Australian Cooperative Research Centre for Satellite Systems (CRC-SS), APL has built the flight version to be flown on the Australian university-class satellite FEDSAT. The AIM provides satellites the flexibility to adapt to changing mission requirements by reconfiguring standardized processing hardware rather than incurring the large costs associated with new builds. This ability to reconfigure the processing in response to changing mission needs leads to true evolveable computing, wherein the instrument 'brain' can learn from new science data in order to perform state-of-the-art data processing. The development of the AIM is significant in its enormous potential to reduce total life-cycle costs for future space exploration missions. The advent of RAM-based FPGAs whose configuration can be changed at any time has enabled the development of the AIM for processing tasks that could not be performed in software. The use of the AIM enables reconfiguration of the FPGA circuitry while the spacecraft is in flight, with many accompanying advantages. The AIM demonstrates the practicalities of using reconfigurable computing hardware devices by conducting a series of designed experiments. These include the demonstration of implementing data compression, data filtering, and communication message processing and inter-experiment data computation. The second generation is the Adaptive Processing Template (ADAPT) which is further described in this paper. The next step forward is to make the hardware itself adaptable and the ADAPT pursues this challenge by developing a reconfigurable module that will be capable of functioning efficiently in various applications. ADAPT will take advantage of radiation tolerant RAM-based field programmable gate array (FPGA) technology to develop a reconfigurable processor that combines the flexibility of a general purpose processor running software with the performance of application specific processing hardware for a variety of high performance computing applications.

Darrin, Ann Garrison↗
NASA NTRS2008

Update on Development of SiC Multi-Chip Power Modules

Progress has been made in a continuing effort to develop multi-chip power modules (SiC MCPMs). This effort at an earlier stage was reported in 'SiC Multi-Chip Power Modules as Power-System Building Blocks' (LEW-18008-1), NASA Tech Briefs, Vol. 31, No. 2 (February 2007), page 28. The following recapitulation of information from the cited prior article is prerequisite to a meaningful summary of the progress made since then: 1) SiC MCPMs are, more specifically, electronic power-supply modules containing multiple silicon carbide power integrated-circuit chips and silicon-on-insulator (SOI) control integrated-circuit chips. SiC MCPMs are being developed as building blocks of advanced expandable, reconfigurable, fault-tolerant power-supply systems. Exploiting the ability of SiC semiconductor devices to operate at temperatures, breakdown voltages, and current densities significantly greater than those of conventional Si devices, the designs of SiC MCPMs and of systems comprising multiple SiC MCPMs are expected to afford a greater degree of miniaturization through stacking of modules with reduced requirements for heat sinking; 2) The stacked SiC MCPMs in a given system can be electrically connected in series, parallel, or a series/parallel combination to increase the overall power-handling capability of the system. In addition to power connections, the modules have communication connections. The SOI controllers in the modules communicate with each other as nodes of a decentralized control network, in which no single controller exerts overall command of the system. Control functions effected via the network include synchronization of switching of power devices and rapid reconfiguration of power connections to enable the power system to continue to supply power to a load in the event of failure of one of the modules; and, 3) In addition to serving as building blocks of reliable power-supply systems, SiC MCPMs could be augmented with external control circuitry to make them perform additional power-handling functions as needed for specific applications. Because identical SiC MCPM building blocks could be utilized in such a variety of ways, the cost and difficulty of designing new, highly reliable power systems would be reduced considerably. This concludes the information from the cited prior article. The main activity since the previously reported stage of development was the design, fabrication, and testing a 120- VDC-to-28-VDC modular power-converter system composed of eight SiC MCPMs in a 4 (parallel)-by-2 (series) matrix configuration, with normally-off controllable power switches. The SiC MCPM power modules include closed-loop control subsystems and are capable of operating at high power density or high temperature. The system was tested under various configurations, load conditions, load-transient conditions, and failure-recovery conditions. Planned future work includes refinement of the demonstrated modular system concept and development of a new converter hardware topology that would enable sharing of currents without the need for communication among modules. Toward these ends, it is also planned to develop a new converter control algorithm that would provide for improved sharing of current and power under all conditions, and to implement advanced packaging concepts that would enable operation at higher power density.

Lostetter, Alexander↗
NASA NTRS2005

Evolvable hardware system at extreme low temperatures

This paper describes circuit evolutionary experiments at extreme low temperatures, including the test of all system components at this extreme environment (EE). In addition to hardening-by-process and hardening-by-design, 'hardening-by-reconfiguration ', when applicable, could be used to mitigate drifts, degradation, or damage on electronic devices (chips) in EE, by using re-configurable devices and an adaptive selfreconfiguration of their circuit topology. Conventional circuit design exploits device characteristics within a certain temperature/radiation range; when that is exceeded, the circuit function degrades. On a reconfigurable device, although component parameters change in EE, a new circuit design, suitable for new parameter values, may be mapped into the reconfigurable structure to recover the initial circuit function. This paper demonstrates this technique for circuit evolution and recovery at liquid nitrogen temperatures (-196.6 (deg)C). In addition, preliminary tests are performed to assess the survivability limitations of the evolutionary processor at extreme low temperatures.

evolvable harware↗
NASA NTRS2006

Protocol Sensing Across Multiple Space Missions

In this work, we present sensing performance using an architecture for a reconfigurable protocol chip for spacebased applications. Toward utilizing the IP packet architecture, utilizing data link layer framing structures for multiplexed data on a channel are the targeted application considered for demonstration purposes. Specifically, we examine three common framing standards and present the sensing performance of these standards and their relative de-correlation metrics. Some analysis is performed to investigate the impact of lossy links and on the number of packets required to perform a decision with some probability. Finally, we present results on a demonstration platform that integrated reconfigurable sensing technology into the Ground Station Interface Device (GRID) for End-to-End IP demonstrations in space.

Ground Station Interface Device (GRID)↗
NASA NTRS2010

Methods and circuitry for reconfigurable SEU/SET tolerance

A device is disclosed in one embodiment that has multiple identical sets of programmable functional elements, programmable routing resources, and majority voters that correct errors. The voters accept a mode input for a redundancy mode and a split mode. In the redundancy mode, the programmable functional elements are identical and are programmed identically so the voters produce an output corresponding to the majority of inputs that agree. In a split mode, each voter selects a particular programmable functional element output as the output of the voter. Therefore, in the split mode, the programmable functional elements can perform different functions, operate independently, and/or be connected together to process different parts of the same problem.

Shuler, Jr., Robert L.↗
DOE OSTI2024

Modular Quantum Processor with an All-to-All Reconfigurable Router

Superconducting qubits provide a promising approach to large-scale fault-tolerant quantum computing. However, qubit connectivity on a planar surface is typically restricted to only a few neighboring qubits. Achieving longer-range and more flexible connectivity, which is particularly appealing in light of recent developments in error-correcting codes, however, usually involves complex multilayer packaging and external cabling, which is resource intensive and can impose fidelity limitations. Here, we propose and realize a high-speed on-chip quantum processor that supports reconfigurable all-to-all coupling with a large on-off ratio. We implement the design in a four-node quantum processor, built with a modular design comprising a wiring substrate coupled to two separate qubit-bearing substrates, each including two single-qubit nodes. We use this device to demonstrate reconfigurable controlled-𝑍 gates across all qubit pairs, with a benchmarked average fidelity of 96.00% ± 0.08% and best fidelity of 97.14% ± 0.07%, limited mainly by dephasing in the qubits. We also generate multiqubit entanglement, distributed across the separate modules, demonstrating GHZ-3 and GHZ-4 states with fidelities of 88.15% ± 0.24% and 75.18% ± 0.11%, respectively. This approach promises efficient scaling to larger-scale quantum circuits and offers a pathway for implementing quantum algorithms and error-correction schemes that benefit from enhanced qubit connectivity.

Quantum circuits↗
NASA NTRS2010

Reconfigurable Fault Tolerance for FPGAs

The invention allows a field-programmable gate array (FPGA) or similar device to be efficiently reconfigured in whole or in part to provide higher capacity, non-redundant operation. The redundant device consists of functional units such as adders or multipliers, configuration memory for the functional units, a programmable routing method, configuration memory for the routing method, and various other features such as block RAM, I/O (random access memory, input/output) capability, dedicated carry logic, etc. The redundant device has three identical sets of functional units and routing resources and majority voters that correct errors. The configuration memory may or may not be redundant, depending on need. For example, SRAM-based FPGAs will need some type of radiation-tolerant configuration memory, or they will need triple-redundant configuration memory. Flash or anti-fuse devices will generally not need redundant configuration memory. Some means of loading and verifying the configuration memory is also required. These are all components of the pre-existing redundant FPGA. This innovation modifies the voter to accept a MODE input, which specifies whether ordinary voting is to occur, or if redundancy is to be split. Generally, additional routing resources will also be required to pass data between sections of the device created by splitting the redundancy. In redundancy mode, the voters produce an output corresponding to the two inputs that agree, in the usual fashion. In the split mode, the voters select just one input and convey this to the output, ignoring the other inputs. In a dual-redundant system (as opposed to triple-redundant), instead of a voter, there is some means to latch or gate a state update only when both inputs agree. In this case, the invention would require modification of the latch or gate so that it would operate normally in redundant mode, and would separately latch or gate the inputs in non-redundant mode.

Shuler, Robert, Jr.↗
DOE OSTI2021

Reprogrammable electro-chemo-optical devices and methods for using the same

Reconfigurable, active optical components can flexibly manipulate light. One example of these components is an electro-chemo-optical device that utilizes a metal oxide film with a complex refractive index that varies as a function of an oxygen vacancy concentration. The optical device may include a metal oxide film, a first electrode, and a second electrode. The first electrode and the second electrode may be used to supply a bias voltage to induce a change in the oxygen vacancy concentration in order to change the optical properties (absorbance, transmittance, and/or reflectance) of the optical device. The magnitude and spatial distribution of the oxygen vacancy concentration may be altered to affect the optical properties of the optical device. In some designs, the optical device may also include an ionic conductor and oxygen source to supply/receive oxygen ions to/from the metal oxide film.

Kalaev, Dmitri↗
DOE OSTI2025

Manipulating Ferroelectric Topological Polar Structures with Twisted Light

Abstract The dynamic control of non‐equilibrium states represents a central challenge in condensed matter physics. While intense terahertz fields drive metal‐insulator transitions and ferroelectricity via soft phonon modes, recent theory suggests that twisted light with orbital angular momentum (OAM) offers a distinct route to manipulate ferroelectric order and stabilize topological excitations including skyrmions, vortices, and Hopfions. Control of ferroelectric polarization in quasi‐2D CsBiNb 2 O 7 (CBNO) is demonstrated using non‐resonant twisted ultra‐violet (UV) light (375 nm, 800 THz). Combining in situ X‐ray Bragg coherent diffractive imaging (BCDI), twisted optical Raman spectroscopy, and density functional theory (DFT), three‐dimensional (3D) ionic displacements, strain fields, and polarization changes are resolved in single crystals. Operando measurements reveal light‐induced strain hysteresis under twisted light–a hallmark of nonlinear, history‐dependent ferroelastic switching driven by OAM. Discrete, irreversible domain transitions emerge as the topological charge ℓ is cycled, stabilizing non‐trivial domain textures including vortex‐antivortex pairs, Bloch/anti‐Bloch points, and merons. These persist after OAM removal, indicating a memory effect. Competing mechanisms are discussed, including multiphoton absorption, strain‐mediated polarization switching, and defect‐wall interactions. The findings establish structured light as a tool for deterministic, reversible control of ferroic states, enabling optically reconfigurable non‐volatile devices.

Chemistry↗
DOE OSTI2020

Widely Tunable Optical and Thermal Properties of Dirac Semimetal Cd 3 As 2

In this paper, a detailed analysis of the temperature-dependent optical properties of epitaxially grown cadmium arsenide (Cd 3 As 2 ), a newly discovered 3D Dirac semimetal is reported. Fermi level tuning—instigated from Pauli-blocking in the linear Dirac cone—and varying Drude response, generate large variations in the mid- and far-infrared optical properties. Thermo-optic shifts larger than those of traditional III–V semiconductors are demonstrated. Electron scattering rate, plasma frequency edge, Fermi level shift, optical conductivity, and electron effective mass analysis of Cd 3 As 2 thin-films are quantified and discussed in detail. The ab initio density functional study and experimental analysis of epitaxially grown Cd 3 As 2 promise applications for nanophotonic and nanoelectronic devices, such as reconfigurable metamaterials and metasurfaces, nanoscale thermal emitters, and on-chip directional antennas.

36 MATERIALS SCIENCE↗
DOE OSTI2025

Nanoscale control of LaAlO 3 /SrTiO 3 conductance beyond the polar catastrophe

Conductive atomic force microscope (c-AFM) lithography can be utilized to create a wide range of LaAlO 3 /SrTiO 3 (LAO/STO)-based nanoelectronic devices in a reconfigurable manner. Experiments were generally performed with intrinsically insulating LAO/STO heterostructures, with LAO thickness less than the critical value at which a polar catastrophe takes place [<4 unit cell (u.c.)]. Here, we use inductively coupled plasma reactive ion etching (ICPRIE) to fabricate c-AFM “canvases” on intrinsically conducting LAO/STO samples with ≥4 u.c. LAO. We observe that its interfacial two-dimensional electron gas (2DEG) can be pinched off and then switched back on by c-AFM lithography. Nanowires created with initially conductive LAO/STO interfaces have an order-of-magnitude longer lifetime in ambient conditions, when compared to an identically created 3.4 u.c. LAO/STO nanowire. We also demonstrate key nanoscale properties such as ballistic transport in a quasi-one-dimensional electron waveguide at a 5 u.c. LAO/STO interface. This approach frees c-AFM-written nanodevice designs from time constraints in air associated with <4 u.c. LAO/STO heterostructures.

36 MATERIALS SCIENCE↗