Reconfigurable Sensor Fusion Processing Hardware
The paper presents the concept and initial test from the hardware implementation of a low-power, high-speed reconfigurable sensor fusion processor.
Hardware implementation multisensor fusion data fu↗
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The Design Process of an Evolutionary Oriented Reconfigurable Architecture
This paper describes the design of a reconfigurable chip programmable at the transistor level and oriented to the implementation of Evolvable Hardware (EHW) experiements.
evolvable hardware reconfigurable hardware genetic↗
Logic design for dynamic and interactive recovery.
Recovery in a fault-tolerant computer means the continuation of system operation with data integrity after an error occurs. This paper delineates two parallel concepts embodied in the hardware and software functions required for recovery; detection, diagnosis, and reconfiguration for hardware, data integrity, checkpointing, and restart for the software. The hardware relies on the recovery variable set, checking circuits, and diagnostics, and the software relies on the recovery information set, audit, and reconstruct routines, to characterize the system state and assist in recovery when required. Of particular utility is a handware unit, the recovery control unit, which serves as an interface between error detection and software recovery programs in the supervisor and provides dynamic interactive recovery.
Carter, W. C.↗
Intrinsic Hardware Evolution for the Design and Reconfiguration of Analog Speed Controllers for a DC Motor
Evolvable hardware provides the capability to evolve analog circuits to produce amplifier and filter functions. Conventional analog controller designs employ these same functions. Analog controllers for the control of the shaft speed of a DC motor are evolved on an evolvable hardware platform utilizing a second generation Field Programmable Transistor Array (FPTA2). The performance of an evolved controller is compared to that of a conventional proportional-integral (PI) controller. It is shown that hardware evolution is able to create a compact design that provides good performance, while using considerably less functional electronic components than the conventional design. Additionally, the use of hardware evolution to provide fault tolerance by reconfiguring the design is explored. Experimental results are presented showing that significant recovery of capability can be made in the face of damaging induced faults.
Gwaltney, David A.↗
Results on the Fitness and Population Based Fault Tolerance Approaches using Reconfigurable Electronic Devices
The paper presents and compares two approaches to design fault-tolerant evolvable hardware: one based on the fitness definition and the other based on the population statistics.
evolvable↗
Adaptive Instrument Module: Space Instrument Controller "Brain" through Programmable Logic Devices
The Adaptive Instrument Module (AIM) will be the first true demonstration of reconfigurable computing with field-programmable gate arrays (FPGAs) in space, enabling the 'brain' of the system to evolve or adapt to changing requirements. In partnership with NASA Goddard Space Flight Center and the Australian Cooperative Research Centre for Satellite Systems (CRC-SS), APL has built the flight version to be flown on the Australian university-class satellite FEDSAT. The AIM provides satellites the flexibility to adapt to changing mission requirements by reconfiguring standardized processing hardware rather than incurring the large costs associated with new builds. This ability to reconfigure the processing in response to changing mission needs leads to true evolveable computing, wherein the instrument 'brain' can learn from new science data in order to perform state-of-the-art data processing. The development of the AIM is significant in its enormous potential to reduce total life-cycle costs for future space exploration missions. The advent of RAM-based FPGAs whose configuration can be changed at any time has enabled the development of the AIM for processing tasks that could not be performed in software. The use of the AIM enables reconfiguration of the FPGA circuitry while the spacecraft is in flight, with many accompanying advantages. The AIM demonstrates the practicalities of using reconfigurable computing hardware devices by conducting a series of designed experiments. These include the demonstration of implementing data compression, data filtering, and communication message processing and inter-experiment data computation. The second generation is the Adaptive Processing Template (ADAPT) which is further described in this paper. The next step forward is to make the hardware itself adaptable and the ADAPT pursues this challenge by developing a reconfigurable module that will be capable of functioning efficiently in various applications. ADAPT will take advantage of radiation tolerant RAM-based field programmable gate array (FPGA) technology to develop a reconfigurable processor that combines the flexibility of a general purpose processor running software with the performance of application specific processing hardware for a variety of high performance computing applications.
Darrin, Ann Garrison↗
Evolution of the Hubble Space Telescope Safing Systems
The Hubble Space Telescope (HST) was launched on April 24 1990, with an expected lifespan of 15 years. Central to the spacecraft design was the concept of a series of on-orbit shuttle servicing missions permitting astronauts to replace failed equipment, update the scientific instruments and keep the HST at the forefront of astronomical discoveries. One key to the success of the Hubble mission has been the robust Safing systems designed to monitor the performance of the observatory and to react to keep the spacecraft safe in the event of equipment anomaly. The spacecraft Safing System consists of a range of software tests in the primary flight computer that evaluate the performance of mission critical hardware, safe modes that are activated when the primary control mode is deemed inadequate for protecting the vehicle, and special actions that the computer can take to autonomously reconfigure critical hardware. The HST Safing System was structured to autonomously detect electrical power system, data management system, and pointing control system malfunctions and to configure the vehicle to ensure safe operation without ground intervention for up to 72 hours. There is also a dedicated safe mode computer that constantly monitors a keep-alive signal from the primary computer. If this signal stops, the safe mode computer shuts down the primary computer and takes over control of the vehicle, putting it into a safe, low-power configuration. The HST Safing system has continued to evolve as equipment has aged, as new hardware has been installed on the vehicle, and as the operation modes have matured during the mission. Along with the continual refinement of the limits used in the safing tests, several new tests have been added to the monitoring system, and new safe modes have been added to the flight software. This paper will focus on the evolution of the HST Safing System and Safing tests, and the importance of this evolution to prolonging the science operations of the telescope.
Pepe, Joyce↗
Light Microscopy Module Imaging Tested and Demonstrated
The Fluids Integrated Rack (FIR), a facility-class payload, and the Light Microscopy Module (LMM), a subrack payload, are integrated research facilities that will fly in the U.S. Laboratory module, Destiny, aboard the International Space Station. Both facilities are being engineered, designed, and developed at the NASA Glenn Research Center by Northrop Grumman Information Technology. The FIR is a modular, multiuser scientific research facility that is one of two racks that make up the Fluids and Combustion Facility (the other being the Combustion Integrated Rack). The FIR has a large volume dedicated for experimental hardware; easily reconfigurable diagnostics, power, and data systems that allow for unique experiment configurations; and customizable software. The FIR will also provide imagers, light sources, power management and control, command and data handling for facility and experiment hardware, and data processing and storage. The first payload in the FIR will be the LMM. The LMM integrated with the FIR is a remotely controllable, automated, on-orbit microscope subrack facility, with key diagnostic capabilities for meeting science requirements--including video microscopy to observe microscopic phenonema and dynamic interactions, interferometry to make thin-film measurements with nanometer resolution, laser tweezers to manipulate micrometer-sized particles, confocal microscopy to provide enhanced three-dimensional visualization of structures, and spectrophotometry to measure the photonic properties of materials. Vibration disturbances were identified early in the LMM development phase as a high risk for contaminating the science microgravity environment. An integrated FIR-LMM test was conducted in Glenn's Acoustics Test Laboratory to assess mechanical sources of vibration and their impact to microscopic imaging. The primary purpose of the test was to characterize the LMM response at the sample location, the x-y stage within the microscope, to vibration emissions from the FIR and LMM support structures.
Gati, Frank↗
Reconfigurable HIL Testing of Earth Satellites
In recent years, hardware-in-the-loop (HIL) testing has carved a strong niche in several industries, such as automotive, aerospace, telecomm, and consumer electronics. As desktop computers have realized gains in speed, memory size, and data storage capacity, hardware/software platforms have evolved into high performance, deterministic HIL platforms, capable of hosting the most demanding applications for testing components and subsystems. Using simulation software to emulate the digital and analog I/O signals of system components, engineers of all disciplines can now test new systems in realistic environments to evaluate their function and performance prior to field deployment. Within the Aerospace industry, space-borne satellite systems are arguably some of the most demanding in terms of their requirement for custom engineering and testing. Typically, spacecraft are built one or few at a time to fulfill a space science or defense mission. In contrast to other industries that can amortize the cost of HIL systems over thousands, even millions of units, spacecraft HIL systems have been built as one-of-a-kind solutions, expensive in terms of schedule, cost, and risk, to assure satellite and spacecraft systems reliability. The focus of this paper is to present a new approach to HIL testing for spacecraft systems that takes advantage of a highly flexible hardware/software architecture based on National Instruments PXI reconfigurable hardware and virtual instruments developed using LabVIEW. This new approach to HIL is based on a multistage/multimode spacecraft bus emulation development model called Reconfigurable Hardware In-the-Loop or RHIL.
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Evolutionary Experiments with a Fine-Grained Reconfigurable Architecture for Analog and Digital CMOS Circuits
The paper describes the architectual details of a fine-grained Programmable Transistor Array (PTA) architecture and illustrates its use in evolutionary experiments on the synthesis of both analog and digital circuits.
evolvable↗
Pre-Hardware Optimization of Spacecraft Image Processing Algorithms and Hardware Implementation
Spacecraft telemetry rates and telemetry product complexity have steadily increased over the last decade presenting a problem for real-time processing by ground facilities. This paper proposes a solution to a related problem for the Geostationary Operational Environmental Spacecraft (GOES-8) image data processing and color picture generation application. Although large super-computer facilities are the obvious heritage solution, they are very costly, making it imperative to seek a feasible alternative engineering solution at a fraction of the cost. The proposed solution is based on a Personal Computer (PC) platform and synergy of optimized software algorithms, and reconfigurable computing hardware (RC) technologies, such as Field Programmable Gate Arrays (FPGA) and Digital Signal Processors (DSP). It has been shown that this approach can provide superior inexpensive performance for a chosen application on the ground station or on-board a spacecraft.
Kizhner, Semion↗
Collision management utilizing CCD and remote sensing technology
With the threat of damage to aerospace systems (space station, shuttle, hypersonic a/c, solar power satellites, loss of life, etc.) from collision with debris (manmade/artificial), there exists an opportunity for the design of a novel system (collision avoidance) to be incorporated into the overall design. While incorporating techniques from ccd and remote sensing technologies, an integrated system utilized in the infrared/visible spectrum for detection, tracking, localization, and maneuvering from doppler shift measurements is achievable. Other analysis such as impact assessment, station keeping, chemical, and optical tracking/fire control solutions are possible through this system. Utilizing modified field programmable gated arrays (software reconfiguring the hardware) the mission and mission effectiveness can be varied. This paper outlines the theoretical operation of a prototype system as it applies to collision avoidance (to be followed up by research).
Mcdaniel, Harvey E., Jr.↗
Software Component Technologies and Space Applications
In the near future, software systems will be more reconfigurable than hardware. This will be possible through the advent of software component technologies which have been prototyped in universities and research labs. In this paper, we outline the foundations for those technologies and suggest how they might impact software for space applications.
Batory, Don↗
Temperature Tolerant Evolvable Systems Utilizing FPGA Boards and Bias-Controlled Amplifiers
Space missions often require radiation and extreme-temperature hardened electronics to survive the harsh environments beyond Earth's atmosphere. Traditional approaches to preserve electronics incorporate shielding, insulation and redundancy at the expense of power and weight. However, a novel way of bypassing these problems is the concept of evolutionary hardware. A reconfigurable device, consisting of several switches interconnected with analog/digital parts, is controlled by an evolutionary processor (EP). When the EP detects degradation in the circuit it sends signals to reconfigure the switches, thus forming a new circuit with the desired output. This concept has been developed since the mid-l990s, but one problem remains-the EP cannot degrade substantially. For this reason, extensive testing at extreme temperatures (-180 to 120 C) has been done on devices found on FPGA boards (taking the role of the EP), such as the Analog to Digital and the Digital to Analog Converter. The EP is used in conjunction with a bias-controlled amplifier and a new prototype relay board, which is interconnected with 6 G4-FETs, a tri-input transistor-like element developed at JPL. The greatest improvements to be made lie in the reconfigurable device, so future design and testing of the G4-FET chip is required.
Kumar, Nikhil R.↗
A reconfigurable robotic exploratory vehicle for navigation on rough terrain
This paper discusses the development of a new family of reconfigurable robotic vehicles for use in exploration of the surfaces of Mars and other remote planets.
reconfigurable hardware adaptable software↗
The Interplanetary Overlay Networking Protocol Accelerator
A document describes the Interplanetary Overlay Networking Protocol Accelerator (IONAC) an electronic apparatus, now under development, for relaying data at high rates in spacecraft and interplanetary radio-communication systems utilizing a delay-tolerant networking protocol. The protocol includes provisions for transmission and reception of data in bundles (essentially, messages), transfer of custody of a bundle to a recipient relay station at each step of a relay, and return receipts. Because of limitations on energy resources available for such relays, data rates attainable in a conventional software implementation of the protocol are lower than those needed, at any given reasonable energy-consumption rate. Therefore, a main goal in developing the IONAC is to reduce the energy consumption by an order of magnitude and the data-throughput capability by two orders of magnitude. The IONAC prototype is a field-programmable gate array that serves as a reconfigurable hybrid (hardware/ firmware) system for implementation of the protocol. The prototype can decode 108,000 bundles per second and encode 100,000 bundles per second. It includes a bundle-cache static randomaccess memory that enables maintenance of a throughput of 2.7Gb/s, and an Ethernet convergence layer that supports a duplex throughput of 1Gb/s.
Pang, Jackson↗
Towards On-board Synthesis and Adaptation of Electronic Functions: An Evolvable Hardware Approach
Autonomous space systems will need to adapt to new environments and perform new functions, in addition to those specified at launch.
adaptive↗
Hybrid-Electric Aero-Propulsion Controls Testbed Results with Energy Storage
Electrified aircraft propulsion (EAP) research is a priority of the National Aeronautics and Space Administration (NASA) for its potential to increase propulsion system efficiency, performance, and operability at the subsystem and vehicle levels while decreasing emissions. These EAP systems demand more advanced control algorithms due to increased complexity. NASA has developed a reconfigurable, hardware-in-the-loop rig to verify control algorithm performance using a sub-scale electro-mechanical system. A novel capability of this rig is the ability to test full scale EAP control algorithms on a sub-scale representation of the electro-mechanical system without turbomachinery/rotors. A novel feature is the use of a physical energy storage device within the electro-mechanical system. A dual spool, parallel hybrid-electric turbofan architecture and energy management control system is tested with the goal of verifying the ability to obtain turbomachinery model operability benefits while controlling sub-scale electro-mechanical hardware. Pre-test predictions of the turbofan model, control, and rig performance were obtained through simulation using a software model of the rig. Theoretical results showing the true performance of the turbofan model were obtained through a software simulation using full-scale mechanical shaft models. The paper compares theoretical, predicted, and actual test results from the turbofan model, energy management control and rig perspectives. The results show that the presence of sub-scale electro-mechanical hardware did not inhibit the energy management algorithm from achieving turbomachinery operability benefits.
hybrid↗