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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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All sourcesNASA NTRSDOE OSTI
NASA NTRSDate not supplied

A 96% Alumina based Packaging System for 500°C Test of SiC Integrated Circuits

With the development of silicon carbide (SiC) sensors and electronic devices for operation at 500°C, compatible packaging technologies are needed for long term high temperature test and deployment of these sensors and electronic devices. 96% Al2O3ceramic is an excellent electrically insulating material with acceptable dielectric constant and low dielectric loss over wide temperature and frequency ranges. This paper presents a packaging system for low power integrated circuits including a prototype 8-I/O chip-level package and printed circuit board (PCB) based on 96% Al2O3ceramic substrates and Au thick-film metallization for 500°C applications. The details related to designs of packages and PCBs, packaging materials, and specific packaging step recipes including wire -bonding and die-attach, are presented. Some test results of this prototype packaging approach applied to SiC integrated circuits at 500°C are reviewed.

High Temperature, Packaging, Alumina, Thick Film↗
NASA NTRSDate not supplied

A 96% Alumina based Packaging System for 500°C Test of SiC Integrated Circuits

With the development of silicon carbide (SiC) sensors and electronic devices for operation at 500°C, compatible packaging technologies are needed for long term high temperature test and deployment of these sensors and electronic devices. 96% Al2O3 ceramic is an excellent electrically insulating material with acceptable dielectric constant and low dielectric loss over wide temperature and frequency ranges. This paper presents a packaging system for low power integrated circuits including a prototype 8-I/O chip-level package and printed circuit board (PCB) based on 96% Al2O3 ceramic substrates and Au thick-film metallization for 500°C applications. The details related to designs of packages and PCBs, packaging materials, and specific packaging step recipes including wire - bonding and die-attach, are presented. Some test results of this prototype packaging approach applied to SiC integrated circuits at 500oC are reviewed.

high temperature↗
NASA NTRS1991

Single board system for fuzzy inference

The very large scale integration (VLSI) implementation of a fuzzy logic inference mechanism allows the use of rule-based control and decision making in demanding real-time applications. Researchers designed a full custom VLSI inference engine. The chip was fabricated using CMOS technology. The chip consists of 688,000 transistors of which 476,000 are used for RAM memory. The fuzzy logic inference engine board system incorporates the custom designed integrated circuit into a standard VMEbus environment. The Fuzzy Logic system uses Transistor-Transistor Logic (TTL) parts to provide the interface between the Fuzzy chip and a standard, double height VMEbus backplane, allowing the chip to perform application process control through the VMEbus host. High level C language functions hide details of the hardware system interface from the applications level programmer. The first version of the board was installed on a robot at Oak Ridge National Laboratory in January of 1990.

Symon, James R.↗
NASA NTRS2003

Packaging Technology Designed, Fabricated, and Assembled for High-Temperature SiC Microsystems

A series of ceramic substrates and thick-film metalization-based prototype microsystem packages designed for silicon carbide (SiC) high-temperature microsystems have been developed for operation in 500 C harsh environments. These prototype packages were designed, fabricated, and assembled at the NASA Glenn Research Center. Both the electrical interconnection system and the die-attach scheme for this packaging system have been tested extensively at high temperatures. Printed circuit boards used to interconnect these chip-level packages and passive components also are being fabricated and tested. NASA space and aeronautical missions need harsh-environment, especially high-temperature, operable microsystems for probing the inner solar planets and for in situ monitoring and control of next-generation aeronautical engines. Various SiC high-temperature-operable microelectromechanical system (MEMS) sensors, actuators, and electronics have been demonstrated at temperatures as high as 600 C, but most of these devices were demonstrated only in the laboratory environment partially because systematic packaging technology for supporting these devices at temperatures of 500 C and beyond was not available. Thus, the development of a systematic high-temperature packaging technology is essential for both in situ testing and the commercialization of high-temperature SiC MEMS. Researchers at Glenn developed new prototype packages for high-temperature microsystems using ceramic substrates (aluminum nitride and 96- and 90-wt% aluminum oxides) and gold (Au) thick-film metalization. Packaging components, which include a thick-film metalization-based wirebond interconnection system and a low-electrical-resistance SiC die-attachment scheme, have been tested at temperatures up to 500 C. The interconnection system composed of Au thick-film printed wire and 1-mil Au wire bond was tested in 500 C oxidizing air with and without 50-mA direct current for over 5000 hr. The Au thick-film metalization-based wirebond electrical interconnection system was also tested in an extremely dynamic thermal environment to assess thermal reliability. The I-V curve1 of a SiC high-temperature diode was measured in oxidizing air at 500 C for 1000 hr to electrically test the Au thick-film material-based die-attach assembly.

Chen, Liang-Yu↗
NASA NTRS1972

Development of chip passivated monolithic complementary MISFET circuits with beam leads

Fabrication method is described for alumina passivated silicon MISFET arrays. Technique involves total passivation beam-lead approach and provides completely sealed chip with double level interconnect capability. Refractory metal alloy is used to form interconnect system and obtain metal contacts that withstand temperatures of 873 K for short periods of time.

Ragonese, L. J.↗
NASA NTRS1987

Error propagation in a digital avionic mini processor

A methodology is introduced and demonstrated for the study of error propagation from the gate to the chip level. The importance of understanding error propagation derives from its close tie with system activity. In this system the target system is BDX-930, a digital avionic multiprocessor. The simulator used was developed at NASA-Langley, and is a gate level, event-driven, unit delay, software logic simulator. An approach is highly structured and easily adapted to other systems. The analysis shows the nature and extent of the dependency of error propagation on microinstruction type, assembly level instruction, and fault-free gate activity.

Lomelino, Dale L.↗
NASA NTRSDate not supplied

Testing of the ISS’s Charcoal HEPA Integrated Particle Scrubber (CHIPS) Filters to Ascertain an Efficiency Curve and Most Penetrating Particle Size

High air quality is a top priority in hermetically sealed environments, such as the International Space Station (ISS). Aerosol particulate filtration on the ISS is achieved via 21 HEPA filters. Traditional HEPA filters have an efficiency of 99.97%, but HEPA filters aboard the ISS have been found to achieve 99.99% efficiency. This may be due to the flight-grade HEPA filters chosen or, less likely, that they are combined with activated charcoal filters for siloxane removal in a combination referred to as Charcoal HEPA Integrated Particle Scrubbers (CHIPS) filters. All filters have a Most Penetrating Particle Size (MPPS), but, until now, the MPPS and efficiency curve of the CHIPS filters was not known. The efficiency curve of the CHIPS filters was ascertained at NASA Glenn Research Center through standard salt crystal aerosolization. This method was selected over aerosolized oil droplets due to a desire to preserve the filter’s function for further testing. The CHIPS filters were tested as they are oriented on the ISS (activated charcoal filter followed by a flight-grade HEPA filter), with the HEPA portion alone, and with the activated charcoal portion alone. The results of this experiment are generally useful but can be especially useful for the microbiology and Environmental Control and Life Support Systems (ECLSS). This is due to microbial contamination being a potential concern in the air revitalization systems on the ISS. Knowing the MMPS of the CHIPS filters, in conjunction with levels of airborne microbes, is useful for predicting which and how many microbes are likely to get through the HEPA filters that sit in the beginning of the ISS airstream. It may also be useful to other groups at NASA to know how many particulates are able to pass through high-efficiency filtration, and even for healthcare cleanrooms and other air purification pursuits.

A Nicolas Whitlock↗
NASA NTRS1987

The use of transputers in processing telemetry data

Parallelism will be an essential ingredient of high performance systems of the future. The Inmos transputer is a high performance single-chip computer whose architecture facilitates the construction of parallel processing systems. Occam is a high level language developed for use with the Inmos transputer. This paper describes a project to evaluate the feasibility of using the transputer to implement real time processing of telemetry data.

Delgado, Hugo M., Jr.↗
NASA NTRS1996

Chip-on-Board Technology 1996 Year-end Report (Design, Manufacturing, and Reliability Study)

The major impetus for flight qualifying Chip-On-Board (COB) packaging technology is the shift in emphasis for space missions to smaller, better, and cheaper spacecraft and satellites resulting from the NASA New Millenium initiative and similar requirements in DoD-sponsored programs. The most important benefit that can potentially be derived from miniaturizing spacecraft and satellites is the significant cost saving realizable if a smaller launch vehicle may be employed. Besides the program cost saving, there are several other advantages to building COB-based space hardware. First, once a well-controlled process is established, COB can be low cost compared to standard Multi-Chip Module (MCM) technology. This cost competitiveness is regarded as a result of the generally greater availability and lower cost of Known Good Die (KGD). Coupled with the elimination of the first level of packaging (chip package), compact, high-density circuit boards can be realized with Printed Wiring Boards (PWB) that can now be made with ever-decreasing feature size in line width and via hole. Since the COB packaging technique in this study is based mainly on populating bare dice on a suitable multi-layer laminate substrate which is not hermetically sealed, die coating for protection from the environment is required. In recent years, significant improvements have been made in die coating materials which further enhance the appeal of COB. Hysol epoxies, silicone, parylene and silicon nitride are desirable because of their compatible Thermal Coefficient of Expansion (TCE) and good moisture resistant capability. These die coating materials have all been used in the space and other industries with varying degrees of success. COB technology, specifically siliconnitride coated hardware, has been flown by Lockheed on the Polar satellite. In addition, DARPA has invested a substantial amount of resources on MCM and COB-related activities recently. With COB on the verge of becoming a dominant player in DoD programs, DARPA is increasing its support of the availability of KGDs which will help decrease their cost. Aside from the various major developments and trends in the space and defense industries that are favorable to the acceptance and widespread use of'COB packaging technology, implementing COB can be appealing in other aspects. Since the interconnection interface is usually the weak link in a system, the overall circuit or system reliability may actually be improved because of the elimination of a level of interconnect/packaging at the chip. With COB, mixing packaging technologies is possible. Because some devices are only available in commercial plastic packages, populating a multi-layer laminate substrate with both bare dice and plastic-package parts is inevitable. Another attractive feature of COB is that re-workability is possible if die coating is applied only on the die top. This method allows local replacement of individual dice that were found to be defective instead of replacing an entire board. In terms of thermal management, unpackaged devices offer a shorter thermal resistance path than their packaged counterparts thereby improving thermal sinking and heat removal from the parts.

Le, Binh Q.↗
NASA NTRS2004

Lab on a Chip Application Development for Exploration

At Marshall Space Flight Center a new capability has been established to aid the advancement of microfluidics for space flight monitoring systems. Lab-On-a-Chip Application Development (LOCAD) team has created a program for advancing Technology Readiness Levels (TRL) of 1 & 2 to TRL 6 and 7, quickly and economically for Lab-On-a-Chip (LOC) applications. Scientists and engineers can utilize LOCAD's process to efficiently learn about microfluidics and determine if microfluidics is applicable to their needs. Once the applicability has been determined, LOCAD can then perform tests to develop the new fluidic protocols which are different from macro-scale chemical reaction protocols. With this information new micro-devices can be created such as the development of a microfluidic system to aid in the search for life, past and present, on Mars. Particular indicators in the Martian soil can contain the direct evidence of life. But to extract the information from the soil and present it to the proper detectors requires multiple fluidic/chemical operations. This is where LOCAD is providing its unique abilities.

Monaco, Lisa↗
NASA NTRS2002

Rapid evolution of analog circuits configured on a field programmable transistor array

The purpose of this paper is to illustrate evolution of analog circuits on a stand-alone board-level evolvable system (SABLES). SABLES is part of an effort to achieve integrated evolvable systems. SABLES provides autonomous, fast (tens to hundreds of seconds), on-chip circuit evolution involving about 100,000 circuit evaluations. Its main components are a JPL Field Programmable Transistor Array (FPTA) chip used as transistor-level reconfigurable hardware, and a TI DSP that implements the evolutionary algorithm controlling the FPTA reconfiguration. The paper details an example of evolution on SABLES and points out to certain transient and memory effects that affect the stability of solutions obtained reusing the same piece of hardware for rapid testing of individuals during evolution.

SABLES analog circuits field programmable transist↗
NASA NTRS2010

Reconfigurable Hardware for Compressing Hyperspectral Image Data

High-speed, low-power, reconfigurable electronic hardware has been developed to implement ICER-3D, an algorithm for compressing hyperspectral-image data. The algorithm and parts thereof have been the topics of several NASA Tech Briefs articles, including Context Modeler for Wavelet Compression of Hyperspectral Images (NPO-43239) and ICER-3D Hyperspectral Image Compression Software (NPO-43238), which appear elsewhere in this issue of NASA Tech Briefs. As described in more detail in those articles, the algorithm includes three main subalgorithms: one for computing wavelet transforms, one for context modeling, and one for entropy encoding. For the purpose of designing the hardware, these subalgorithms are treated as modules to be implemented efficiently in field-programmable gate arrays (FPGAs). The design takes advantage of industry- standard, commercially available FPGAs. The implementation targets the Xilinx Virtex II pro architecture, which has embedded PowerPC processor cores with flexible on-chip bus architecture. It incorporates an efficient parallel and pipelined architecture to compress the three-dimensional image data. The design provides for internal buffering to minimize intensive input/output operations while making efficient use of offchip memory. The design is scalable in that the subalgorithms are implemented as independent hardware modules that can be combined in parallel to increase throughput. The on-chip processor manages the overall operation of the compression system, including execution of the top-level control functions as well as scheduling, initiating, and monitoring processes. The design prototype has been demonstrated to be capable of compressing hyperspectral data at a rate of 4.5 megasamples per second at a conservative clock frequency of 50 MHz, with a potential for substantially greater throughput at a higher clock frequency. The power consumption of the prototype is less than 6.5 W. The reconfigurability (by means of reprogramming) of the FPGAs makes it possible to effectively alter the design to some extent to satisfy different requirements without adding hardware. The implementation could be easily propagated to future FPGA generations and/or to custom application-specific integrated circuits.

Aranki, Nazeeh↗
DOE OSTI2026

Robustness of the smartpixels classifier for different simulated sensor geometries and non-ideal detector conditions

Pixel tracking detectors at upcoming collider experiments will see unprecedented charged-particle densities. Real-time data reduction on the detector will enable higher granularity and faster readout, possibly enabling the use of the pixel detector in high-rate online event selection, such as the ATLAS or CMS first-level trigger systems. This data reduction can be accomplished with a neural network (NN) in the readout chip bonded with the sensor that recognizes and rejects tracks with low transverse momentum (p T ) based on the geometrical shape of the charge deposition (“cluster”). To design viable detectors for deployment, the dependence of the NN as a function of the sensor geometry, external magnetic field, irradiation, and noise must be understood. In this paper, we present first studies of the efficiency and data reduction for planar pixel sensors exploring these parameters. For the CMS HL-LHC sensor geometry, we obtain a signal efficiency of (91.9 ± 0.7)% and a data reduction of (29.7 ± 1.0)%. A smaller sensor pitch in the bending direction improves the p T discrimination, but a larger pitch can be partially compensated with detector thickness. Any accumulated radiation damage also changes the cluster shape, reducing the signal efficiency compared to the baseline by approximately 30–60% in absolute terms, but nearly all of the performance can be recovered through retraining of the network and updating the weights. Finally, the impact of noise was investigated, and retraining the network on noise-injected datasets was found to maintain performance within 6% of the baseline network trained and evaluated on noiseless data. •ASIC-compatible track-momentum classifier is robust in realistic detector conditions.•About 90% signal efficiency and 30% data reduction per layer for CMS HL-LHC geometry.•Single-layer signal efficiency increases for smaller pixel pitch or thicker sensors.•Performance with noise or after radiation damage mostly recovered by retraining.

Shekar, Danush [Illinois U., Chicago] (ORCID:00000↗
DOE OSTI2026

Identifying materials-level sources of performance variation in superconducting transmon qubits

The Superconducting Quantum Materials and Systems Center, a U. S. Department of Energy National Quantum Information Science Research Center, has conducted a comprehensive and coordinated study using superconducting transmon qubit chips with known performance metrics to identify the underlying materials-level sources of device-to-device performance variation. Following qubit coherence measurements, these qubits of varying base superconducting metals and substrates have been examined with various non-destructive and invasive material characterization techniques at Northwestern University, Ames National Laboratory, and Fermilab as part of a blind study. We find trends in variations of the depth of the etched substrate trench, the thickness of the surface oxide, and the geometry of the sidewall, which when combined, lead to correlations with the T1 lifetime across different qubits on the same chip. In addition, we provide a list of features that varied from device to device, for which the impact on performance requires further studies. Finally, we identify two low-temperature characterization techniques that may potentially serve as proxy tools for qubit measurements. These insights provide materials-oriented solutions to not only reduce performance variations across neighboring devices but also to engineer and fabricate devices with optimal geometries to achieve performance metrics beyond the state-of-the-art values.

Murthy, Akshay A. [Fermilab] (ORCID:00000001767768↗
NASA NTRS1995

MEMS Technology for Space Applications

Micro-technology enables the manufacturing of all kinds of components for miniature systems or micro-systems, such as sensors, pumps, valves, and channels. The integration of these components into a micro-electro-mechanical system (MEMS) drastically decreases the total system volume and mass. These properties, combined with the increasing need for monitoring and control of small flows in (bio)chemical experiments, makes MEMS attractive for space applications. The level of integration and applied technology depends on the product demands and the market. The ultimate integration is process integration, which results in a one-chip system. An example of process integration is a dosing system of pump, flow sensor, micromixer, and hybrid feedback electronics to regulate the flow. However, for many applications, a hybrid integration of components is sufficient and offers the advantages of design flexibility and even the exchange of components in the case of a modular set up. Currently, we are working on hybrid integration of all kinds of sensors (physical and chemical) and flow system modules towards a modular system; the micro total analysis system (micro TAS). The substrate contains electrical connections as in a printed circuit board (PCB) as well as fluid channels for a circuit channel board (CCB) which, when integrated, form a mixed circuit board (MCB).

vandenBerg, A.↗
DOE OSTI2024

USPAS Digital Low-Level RF firmware and software suite (uspas_llrf) v1.0

The USPAS Digital Low-Level RF firmware and software suite was originally developed for the USPAS 2023 LLRF course, for demonstrating the close loop RF control on the BerkeleyLab Marble FPGA carrier and Zest digitizer platform in controlling the RF field for various accelerators. The suite features Register-transfer level (RTL) designs for the board-support layer, digital signal processing and verification test benches, system-on-chip architecture, and Experimental Physics and Industrial Control System (EPICS) support, utilizing a open-source tool chain.

Du, Qiang↗
NASA NTRS2013

Millimeter-Wave Localizers for Aircraft-to-Aircraft Approach Navigation

Aerial refueling technology for both manned and unmanned aircraft is critical for operations where extended aircraft flight time is required. Existing refueling assets are typically manned aircraft, which couple to a second aircraft through the use of a refueling boom. Alignment and mating of the two aircraft continues to rely on human control with use of high-resolution cameras. With the recent advances in unmanned aircraft, it would be highly advantageous to remove/reduce human control from the refueling process, simplifying the amount of remote mission management and enabling new operational scenarios. Existing aerial refueling uses a camera, making it non-autonomous and prone to human error. Existing commercial localizer technology has proven robust and reliable, but not suited for aircraft-to-aircraft approaches like in aerial refueling scenarios since the resolution is too coarse (approximately one meter). A localizer approach system for aircraft-to-aircraft docking can be constructed using the same modulation with a millimeterwave carrier to provide high resolution. One technology used to remotely align commercial aircraft on approach to a runway are ILS (instrument landing systems). ILS have been in service within the U.S. for almost 50 years. In a commercial ILS, two partially overlapping beams of UHF (109 to 126 MHz) are broadcast from an antenna array so that their overlapping region defines the centerline of the runway. This is called a localizer system and is responsible for horizontal alignment of the approach. One beam is modulated with a 150-Hz tone, while the other with a 90-Hz tone. Through comparison of the modulation depths of both tones, an autopilot system aligns the approaching aircraft with the runway centerline. A similar system called a glide-slope (GS) exists in the 320-to-330MHz band for vertical alignment of the approach. While this technology has been proven reliable for millions of commercial flights annually, its UHF nature limits its ability to operate beyond the 1-to-2-meter precisions associated with commercial runway width. A prototype ILS-type system operates at millimeter-wave frequencies to provide automatic and robust approach control for aerial refueling. The system allows for the coupling process to remain completely autonomous, as a boom operator is no longer required. Operating beyond 100 GHz provides enough resolution and a narrow enough beamwidth that an approach corridor of centimeter scales can be maintained. Two modules were used to accomplish this task. The first module is a localizer/glide-slope module that can be fitted on a refueling aircraft. This module provides the navigation beams for aligning the approaching aircraft. The second module is navigational receiver fitted onto the approaching aircraft to be re fueled that can detect the approach beams. Since unmanned aircraft have a limited payload size and limited electrical power, the receiver portion was implemented in CMOS (complementary metal oxide semiconductor) technology based on a super-regenerative receiver (SRR) architecture. The SRR achieves mW-level power consumption and chip sizes less than l mm2. While super-regenerative techniques have small bandwidths that limit use in communication systems, their advantages of high sensitivity, low complexity, and low power make them ideal in this situation where modulating tones of less than 1 kHz are used.

Tang, Adrian J.↗
NASA NTRS2013

NASA Tech Briefs, January 2013

Topics include: Single-Photon-Sensitive HgCdTe Avalanche Photodiode Detector; Surface-Enhanced Raman Scattering Using Silica Whispering-Gallery Mode Resonators; 3D Hail Size Distribution Interpolation/Extrapolation Algorithm; Color-Changing Sensors for Detecting the Presence of Hypergolic Fuels; Artificial Intelligence Software for Assessing Postural Stability; Transformers: Shape-Changing Space Systems Built with Robotic Textiles; Fibrillar Adhesive for Climbing Robots; Using Pre-Melted Phase Change Material to Keep Payloads in Space Warm for Hours without Power; Development of a Centrifugal Technique for the Microbial Bioburden Analysis of Freon (CFC-11); Microwave Sinterator Freeform Additive Construction System (MS-FACS); DSP/FPGA Design for a High-Speed Programmable S-Band Space Transceiver; On-Chip Power-Combining for High-Power Schottky Diode-Based Frequency Multipliers; FPGA Vision Data Architecture; Memory Circuit Fault Simulator; Ultra-Compact Transputer-Based Controller for High-Level, Multi-Axis Coordination; Regolith Advanced Surface Systems Operations Robot Excavator; Magnetically Actuated Seal; Hybrid Electrostatic/Flextensional Mirror for Lightweight, Large-Aperture, and Cryogenic Space Telescopes; System for Contributing and Discovering Derived Mission and Science Data; Remote Viewer for Maritime Robotics Software; Stackfile Database; Reachability Maps for In Situ Operations; JPL Space Telecommunications Radio System Operating Environment; RFI-SIM: RFI Simulation Package; ION Configuration Editor; Dtest Testing Software; IMPaCT - Integration of Missions, Programs, and Core Technologies; Integrated Systems Health Management (ISHM) Toolkit; Wind-Driven Wireless Networked System of Mobile Sensors for Mars Exploration; In Situ Solid Particle Generator; Analysis of the Effects of Streamwise Lift Distribution on Sonic Boom Signature; Rad-Tolerant, Thermally Stable, High-Speed Fiber-Optic Network for Harsh Environments; Towed Subsurface Optical Communications Buoy; High-Collection-Efficiency Fluorescence Detection Cell; Ultra-Compact, Superconducting Spectrometer-on-a-Chip at Submillimeter Wavelengths; UV Resonant Raman Spectrometer with Multi-Line Laser Excitation; Medicine Delivery Device with Integrated Sterilization and Detection; Ionospheric Simulation System for Satellite Observations and Global Assimilative Model Experiments - ISOGAME; Airborne Tomographic Swath Ice Sounding Processing System; flexplan: Mission Planning System for the Lunar Reconnaissance Orbiter; Estimating Torque Imparted on Spacecraft Using Telemetry; PowderSim: Lagrangian Discrete and Mesh-Free Continuum Simulation Code for Cohesive Soils; Multiple-Frame Detection of Subpixel Targets in Thermal Image Sequences; Metric Learning to Enhance Hyperspectral Image Segmentation; Basic Operational Robotics Instructional System; Sheet Membrane Spacesuit Water Membrane Evaporator; Advanced Materials and Manufacturing for Low-Cost, High-Performance Liquid Rocket Combustion Chambers; Motor Qualification for Long-Duration Mars Missions.

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