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Material variations on an atomic scale enable the quantum mechanical functionality of devices such as resonant tunneling diodes (RTDs), quantum well infrared photodetectors (QWIPs), quantum well lasers, and heterostructure field effect transistors (HFETs).
Material variations on an atomic scale enable the quantum mechanical functionality of devices such as resonant tunneling diodes (RTDs), quantum well infrared photodetectors (QWIPs), quantum well lasers, and heterostructure field effect transistors (HFETs).
In 1965, just four years after the first planar integrated circuit (IC) was discovered, Cordon Moore observed that the number of transistors per integrated circuit had grown exponentially. He predicted that this would continue, and the media soon began to call his prophesy "Moore's Law" For nearly forty years, Moore's Law has been validated by the technological progress achieved in the semiconductor industry. Now, however, industry experts are warning of a "Red Brick Wall" that may soon block the continued scaling predicted by by Moore's Law. The "red bricks" in the wall are those areas of technical challenge for which no known manufacturable solution exists. One such "brick" is the challenge of finding a new material and processing technology to replace the metals used today to interconnect transistors on a chip.
Further improvements in the performance of integrated electronics will eventually halt due to practical fundamental limits on our ability to downsize transistors and interconnect wiring. Avoiding these limits requires a revolutionary approach to switching device technology and computing architecture. Nanoelectronics, the technology of exploiting physics on the nanometer scale for computation and communication, attempts to avoid conventional limits by developing new approaches to switching, circuitry, and system integration. This presentation overviews the basic principles that operate on the nanometer scale that can be assembled into practical devices and circuits. Quantum resonant tunneling (RT) is used as the center-piece of the overview since RT devices already operate at high temperature (120 degrees C) and can be scaled, in principle, to a few nanometers in semiconductors. Near- and long-term applications of GaAs and silicon quantum devices are suggested for signal and information processing, memory, optoelectronics, and radio frequency (RF) communication.
It is increasingly recognized that semiconductor based electronics that can function at ambient temperatures higher than 150 C without external cooling could greatly benefit a variety of important applications, especially-in the automotive, aerospace, and energy production industries. The fact that wide bandgap semiconductors are capable of electronic functionality at much higher temperatures than silicon has partially fueled their development, particularly in the case of SiC. It appears unlikely that wide bandgap semiconductor devices will find much use in low-power transistor applications until the ambient temperature exceeds approximately 300 C, as commercially available silicon and silicon-on-insulator technologies are already satisfying requirements for digital and analog very large scale integrated circuits in this temperature range. However, practical operation of silicon power devices at ambient temperatures above 200 C appears problematic, as self-heating at higher power levels results in high internal junction temperatures and leakages. Thus, most electronic subsystems that simultaneously require high-temperature and high-power operation will necessarily be realized using wide bandgap devices, once the technology for realizing these devices become sufficiently developed that they become widely available. Technological challenges impeding the realization of beneficial wide bandgap high ambient temperature electronics, including material growth, contacts, and packaging, are briefly discussed.
Theoretical analysis and some experiments have demonstrated that siliconon- insulator (SOI) 4-gate transistors the type known as G(exp 4)FETs could be efficiently used for in-plane crossing of signal paths. Much of the effort of designing very-large-scale integrated (VLSI) circuits is focused on area-efficient routing of signals. The main source of difficulty in VLSI signal routing is the requirement to prevent crossing, in the same plane, of wires that are meant to be kept electrically insulated from each other. Consequently, it often becomes necessary to design and build VLSI circuits in multiple layers with vias (connections between conductors in different layers at selected locations). Suitable devices that would prevent, or at least sufficiently suppress, undesired electrical coupling (cross-talk) between wires crossing in the same plane would enable compact, simpler implementation complex interconnection networks with in-plane crossings that, heretofore, have not been possible in VLSI circuitry. The use of G4FETs as in-plane signal-crossing devices or routers, in combination with the use of G(exp 4)FETs as universal programmable logic gates, would create opportunities for reducing complexity in VLSI design.
Test data were collected on 1035 plastic encapsulated devices and 75 hermetically scaled control group devices that were purchased from each of five different manufacturers in the categories of (1) low power Schottsky TTL (bipolar) digital circuits; (2) CMOS digital circuits; (3) operational amplifier linear circuits; and (4) NPN transistors. These parts were subjected to three different initial screening conditions, then to extended life testing, to determine any possible advantages or trends for any particular screen. Several tests were carried out in the areas of flammability testing, humidity testing, high pressure steam (auroclave) testing, and high temperature storage testing. Test results are presented. Procurement and application considerations for use of plastic encapsulated semiconductors are presented and a statistical analysis program written to study the log normal distributions resulting from life testing is concluded.
When a medium- or large-scale integrated circuit is designed, efforts are usually made to avoid the use of resistor-capacitor time constant generators. The capacitor needed for this circuit usually takes up more surface area on the chip than several resistors and transistors. When the use of this network is unavoidable, the designer usually makes an effort to see that the choice of resistor and capacitor combinations is such that a minimum amount of surface area is consumed. The optimum ratio of resistance to capacitance that will result in this minimum area is equal to the ratio of resistance to capacitance which may be obtained from a unit of surface area for the particular process being used. The minimum area required is a function of the square root of the reciprocal of the products of the resistance and capacitance per unit area. This minimum occurs when the area required by the resistor is equal to the area required by the capacitor.
Plasma-enhanced chemical vapor deposition (PECVD) and high-throughput manufacturing techniques for integrating single, aligned carbon nanotubes (CNTs) into novel 3D nanoscale architectures have been developed. First, the PECVD growth technique ensures excellent alignment of the tubes, since the tubes align in the direction of the electric field in the plasma as they are growing. Second, the tubes generated with this technique are all metallic, so their chirality is predetermined, which is important for electronic applications. Third, a wafer-scale manufacturing process was developed that is high-throughput and low-cost, and yet enables the integration of just single, aligned tubes with nanoscale 3D architectures with unprecedented placement accuracy and does not rely on e-beam lithography. Such techniques should lend themselves to the integration of PECVD grown tubes for applications ranging from interconnects, nanoelectromechanical systems (NEMS), sensors, bioprobes, or other 3D electronic devices. Chemically amplified polyhydroxystyrene-resin-based deep UV resists were used in conjunction with excimer laser-based (lambda = 248 nm) step-and-repeat lithography to form Ni catalyst dots = 300 nm in diameter that nucleated single, vertically aligned tubes with high yield using dc PECVD growth. This is the first time such chemically amplified resists have been used, resulting in the nucleation of single, vertically aligned tubes. In addition, novel 3D nanoscale architectures have been created using topdown techniques that integrate single, vertically aligned tubes. These were enabled by implementing techniques that use deep-UV chemically amplified resists for small-feature-size resolution; optical lithography units that allow unprecedented control over layer-to-layer registration; and ICP (inductively coupled plasma) etching techniques that result in near-vertical, high-aspect-ratio, 3D nanoscale architectures, in conjunction with the use of materials that are structurally and chemically compatible with the high-temperature synthesis of the PECVD-grown tubes. The techniques offer a wafer-scale process solution for integrating single PECVD-grown nanotubes into novel architectures that should accelerate their integration in 3D electronics in general. NASA can directly benefit from this technology for its extreme-environment planetary missions. Current Si transistors are inherently more susceptible to high radiation, and do not tolerate extremes in temperature. These novel 3D nanoscale architectures can form the basis for NEMS switches that are inherently less susceptible to radiation or to thermal extremes.
We have combined integrated circuit antenna technology with microwave oscillator design to build an active slot-oscillator. The design is planar, does not require via holes and is compatible with monolithic transistor technology. The CPW-fed antenna impedance is calculated using a full-wave analysis technique. Slot-oscillators were built at 7, 13, and 22 GHz, and the predicted oscillation frequencies agree well with experiments. The design is easily scaled to millimeter-wave frequencies and can be extended to power combining arrays.
The Q/U Imaging ExperimenT (QUIET) is designed to measure polarization in the Cosmic Microwave Background, targeting the imprint of inflationary gravitational waves at large angular scales ( approx 1 deg.) . Between 2008 October and 2010 December, two independent receiver arrays were deployed sequentially on a 1.4 m side-fed Dragonian telescope. The polarimeters which form the focal planes use a highly compact design based on High Electron Mobility Transistors (HEMTs) that provides simultaneous measurements of the Stokes parameters Q, U, and I in a single module. The 17-element Q-band polarimeter array, with a central frequency of 43.1 GHz, has the best sensitivity (69 micro Ks(exp 1/2)) and the lowest instrumental systematic errors ever achieved in this band, contributing to the tensor-to-scalar ratio at r < 0.1. The 84-element W-band polarimeter array has a sensitivity of 87 micro Ks(exp 1/2) at a central frequency of 94.5 GHz. It has the lowest systematic errors to date, contributing at r < 0.01 (QUIET Collaboration 2012) The two arrays together cover multipoles in the range l approximately equals 25-975 . These are the largest HEMT-ba.sed arrays deployed to date. This article describes the design, calibration, performance of, and sources of systematic error for the instrument,
An ac motor controller for an induction motor electric vehicle drive system was designed, fabricated, tested, evaluated, and cost analyzed. A vehicle performance analysis was done to establish the vehicle tractive effort-speed requirements. These requirements were then converted into a set of ac motor and ac controller requirements. The power inverter is a three-phase bridge using power Darlington transistors. The induction motor was optimized for use with an inverter power source. The drive system has a constant torque output to base motor speed and a constant horsepower output to maximum speed. A gear shifting transmission is not required. The ac controller was scaled from the base 20 hp (41 hp peak) at 108 volts dec to an expanded horsepower and battery voltage range. Motor reversal was accomplished by electronic reversal of the inverter phase sequence. The ac controller can also be used as a boost chopper battery charger. The drive system was tested on a dynamometer and results are presented. The current-controlled pulse width modulation control scheme yielded improved motor current waveforms. The ac controller favors a higher system voltage.
A new design of an active antenna with a dielectric resonator stabilized high electron mobility transistor (HEMT) oscillator (DRO) and an aperture-coupled patch antenna is reported. The circuit is fabricated using coplanar waveguide (CPW) with the oscillator and the antenna on opposite sides of the substrate. The active antenna was demonstrated at 7.6 GHz; however, the design can be scaled to higher frequencies. Excellent oscillator characteristics and radiation patterns were obtained.
A design of an active antenna with a dielectric resonator stabilized high-electron-mobility transistor (HEMT) oscillator (DRO) and an aperture-coupled patch antenna is reported. The circuit is fabricated using coplanar waveguide (CPW) with the oscillator and the antenna on opposite sides of the substrate. The active antenna was demonstrated at 7.6 GHz; however, the design can be scaled to higher frequencies. Excellent oscillator characteristics and radiation patterns were obtained.
Limited by increased parasitics and thermal effects as the device size becomes large, current commercial SiGe power HBTs are difficult to operate at X-band (8-12 GHz) with adequate power added efficiencies at high power levels. We found that, by changing the heterostructure and doping profile of SiGe HBTs, their power gain can be significantly improved without resorting to substantial lateral scaling. Furthermore, employing a common-base configuration with proper doping profile instead of a common-emitter configuration improves the power gain characteristics of SiGe HBTs, which thus permits these devices to be efficiently operated at X-band. In this paper, we report the results of SiGe power HBTs and MMIC power amplifiers operating at 8-10 GHz. At 10 GHz, 22.5 dBm (178 mW) RF output power with concurrent gain of 7.32 dB is measured at the peak power-added efficiency of 20.0% and the maximum RF output power of 24.0 dBm (250 mW) is achieved from a 20 emitter finger SiGe power HBT. Demonstration of single-stage X-band medium-power linear MMIC power amplifier is also realized at 8 GHz. Employing a 10-emitter finger SiGe HBT and on-chip input and output matching passive components, a linear gain of 9.7 dB, a maximum output power of 23.4 dBm and peak power added efficiency of 16% is achieved from the power amplifier. The MMIC exhibits very low distortion with third order intermodulation (IM) suppression C/I of -13 dBc at output power of 21.2 dBm and over 20dBm third order output intercept point (OIP3).
The very large scale integration (VLSI) implementation of a fuzzy logic inference mechanism allows the use of rule-based control and decision making in demanding real-time applications. Researchers designed a full custom VLSI inference engine. The chip was fabricated using CMOS technology. The chip consists of 688,000 transistors of which 476,000 are used for RAM memory. The fuzzy logic inference engine board system incorporates the custom designed integrated circuit into a standard VMEbus environment. The Fuzzy Logic system uses Transistor-Transistor Logic (TTL) parts to provide the interface between the Fuzzy chip and a standard, double height VMEbus backplane, allowing the chip to perform application process control through the VMEbus host. High level C language functions hide details of the hardware system interface from the applications level programmer. The first version of the board was installed on a robot at Oak Ridge National Laboratory in January of 1990.
HEMT-based receiver arrays with excellent noise and scalability are already starting to be manufactured at 100 GHz, but the advances in technology should make it possible to develop receiver modules with even greater operation frequency up to 200 GHz. A prototype heterodyne amplifier module has been developed for operation from 140 to 170 GHz using monolithic millimeter-wave integrated circuit (MMIC) low-noise InP high electron mobility transistor (HEMT) amplifiers. The compact, scalable module is centered on the 150-GHz atmospheric window using components known to operate well at these frequencies. Arrays equipped with hundreds of these modules can be optimized for many different astrophysical measurement techniques, including spectroscopy and interferometry. This module is a heterodyne receiver module that is extremely compact, and makes use of 35-nm InP HEMT technology, and which has been shown to have excellent noise temperatures when cooled cryogenically to 30 K. This reduction in system noise over prior art has been demonstrated in commercial mixers (uncooled) at frequencies of 160-180 GHz. The module is expected to achieve a system noise temperature of 60 K when cooled. An MMIC amplifier module has been designed to demonstrate the feasibility of expanding heterodyne amplifier technology to the 140 to 170-GHz frequency range for astronomical observations. The miniaturization of many standard components and the refinement of RF interconnect technology have cleared the way to mass-production of heterodyne amplifier receivers, making it a feasible technology for many large-population arrays. This work furthers the recent research efforts in compact coherent receiver modules, including the development of the Q/U Imaging ExperimenT (QUIET) modules centered at 40 and 90 GHz, and the production of heterodyne module prototypes at 90 GHz.
The increasing use of power electronics, such as high-current semiconductor devices and modules, within space vehicles is driving the need to develop specialty thermal management materials in both the packaging of these discrete devices and the packaging of modules consisting of these device arrays. Developed by Applied Nanotech, Inc. (ANI), CarbAl heat transfer material is uniquely characterized by its low density, high thermal diffusivity, and high thermal conductivity. Its coefficient of thermal expansion (CTE) is similar to most power electronic materials, making it an effective base plate substrate for state-of-the-art silicon carbide (SiC) super junction transistors. The material currently is being used to optimize hybrid vehicle inverter packaging. Adapting CarbAl-based substrates to space applications was a major focus of the SBIR project work. In Phase I, ANI completed modeling and experimentation to validate its deployment in a space environment. Key parameters related to cryogenic temperature scaling of CTE, thermal conductivity, and mechanical strength. In Phase II, the company concentrated on improving heat sinks and thermally conductive circuit boards for power electronic applications.