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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 541 records · Page 30
All sourcesNASA NTRSDOE OSTI
NASA NTRS2012

Demonstration of the Wide-Field Imaging Interferometer Testbed Using a Calibrated Hyperspectral Image Projector

The Wide-field Imaging Interferometer testbed (WIIT) at NASA's Goddard Space Flight Center uses a dual-Michelson interferometric technique. The WIIT combines stellar interferometry with Fourier-transform interferometry to produce high-resolution spatial-spectral data over a large field-of-view. This combined technique could be employed on future NASA missions such as the Space Infrared Interferometric Telescope (SPIRIT) and the Sub-millimeter Probe of the Evolution of Cosmic Structure (SPECS). While both SPIRIT and SPECS would operate at far-infrared wavelengths, the WIIT demonstrates the dual-interferometry technique at visible wavelengths. The WIIT will produce hyperspectral image data, so a true hyperspectral object is necessary. A calibrated hyperspectral image projector (CHIP) has been constructed to provide such an object. The CHIP uses Digital Light Processing (DLP) technology to produce customized, spectrally-diverse scenes. CHIP scenes will have approximately 1.6-micron spatial resolution and the capability of . producing arbitrary spectra in the band between 380 nm and 1.6 microns, with approximately 5-nm spectral resolution. Each pixel in the scene can take on a unique spectrum. Spectral calibration is achieved with an onboard fiber-coupled spectrometer. In this paper we describe the operation of the CHIP. Results from the WIIT observations of CHIP scenes will also be presented.

Bolcar, Matthew R.↗
NASA NTRS2018

Challenges and Opportunities in Gen3 Embedded Cooling with High-Quality Microgap Flow

Gen3, Embedded Cooling, promises to revolutionize thermal management of advanced microelectronic systems by eliminating the sequential conductive and interfacial thermal resistances which dominate the present 'remote cooling' paradigm. Single-phase interchip microfluidic flow with high thermal conductivity chips and substrates has been used successfully to cool single transistors dissipating more than 40kW/sq cm, but efficient heat removal from transistor arrays, larger chips, and chip stacks operating at these prodigious heat fluxes would require the use of high vapor fraction (quality), two-phase cooling in intra- and inter-chip microgap channels. The motivation, as well as the challenges and opportunities associated with evaporative embedded cooling in realistic form factors, is the focus of this paper. The paper will begin with a brief review of the history of thermal packaging, reflecting the 70-year 'inward migration' of cooling technology from the computer-room, to the rack, and then to the single chip and multichip module with 'remote' or attached air- and liquid-cooled coldplates. Discussion of the limitations of this approach and recent results from single-phase embedded cooling will follow. This will set the stage for discussion of the development challenges associated with application of this Gen3 thermal management paradigm to commercial semiconductor hardware, including dealing with the effects of channel length, orientation, and manifold-driven centrifugal acceleration on the governing behavior.

microchannel↗
NASA NTRS2018

High Power W-Band/F-Band Schottky Diode Based Frequency Multipliers

A solid state device chip including diodes (generating a higher frequency output through frequency multiplication of the input frequency) and a novel on-chip power combining design. Together with the on-chip power combining, the chip has increased efficiency because the diodes' anodes, being micro-fabricated simultaneously on the same patch of a GaAs wafer under identical conditions, are very well balanced. The diodes' GaAs heterostructure and the overall chip geometry are designed to be optimized for high power operation. As a result of all these features, the device can generate record-setting power having a signal frequency in the F-band and W-band (30% conversion efficiency).

Siles Perez, Jose Vicente↗
NASA NTRS2002

Commercial-Off-The-Shelf Microelectromechanical Systems (MEMS) Flow-Measurement Probes Fabricated And Assembled

As an alternative to conventional tubing instrumentation for measuring airflow, designers and technicians at the NASA Glenn Research Center have been fabricating packaging components and assembling a set of unique probes using commercial-off-the-shelf microelectromechanical systems (MEMS) integrated circuits (computer chips). Using MEMS as an alternative has some compelling advantages over standard measurement devices. Sensor technologies have matured through high-production usage in industries such as automotive and aircraft manufacturers. Currently, MEMS are the choice in applications such as tire pressure monitors, altimeters, pneumatic controls, cable leak detectors, and consumer appliances. Conventional instrumentation uses tubing buried in the model aerodynamic surfaces or wind tunnel walls. The measurements are made when pressure is introduced at the tube opening. The pressure then must travel the tubing for lengths ranging from 20 to hundreds of feet before reaching an electronic signal conditioner. This condition causes a considerable amount of damping and requires measurements to be made only after the test rig has reached steady-state operation. The electronic MEMS pressure sensor is able to take readings continuously under dynamic states in nearly real time. The use of stainless steel tubing for pressure measurements requires many tubes to be cleaned, cut to length, carefully installed, and delicately deburred and spliced for use. A cluster of a few hundred 1/16-in.- (0.0625-in.-) diameter tubes (not uncommon in research testing facilities) can be several inches in diameter and may weigh enough to require two men to handle. Replacing hard tubing with electronic chips can eliminate much of the bulk. Each sensor would fit on the tip of the 1/16-in. tubing with room to spare. The P592 piezoresistive silicon pressure sensor (Lucas NovaSensor, Fremont, CA) was chosen for this project because of its cost, availability, and tolerance to extreme ambient conditions. The chip is 1 mm square by 0.6 mm thick (0.039 by 0.023 in.) with 0.12-mm (0.005-in.) wire connection tabs. Three MEMS chips were used to build the first type of flow-angularity probe. This MEMS probe will be demonstrated as an alternative to a standard tube type "Cobra Probe" now used routinely in wind tunnel and aeronautical hardware applications. The response time and accuracy would allow the probe to be translated on an actuator across a flow field, yielding precision dynamic measurements not possible with conventional instrumentation. The low profile, the minimal power requirement, the rugged construction, and the moderate cost all contribute to making MEMS sensors the enticing choice instrument in future research measurement needs. The MEMS probe efforts are a continuation of work initiated by Brian Willis, without whose foresight and efforts this project would never have been realized. This task was funded through cooperation with the NASA Electronic Parts and Packaging (NEPP) program at the Jet Propulsion Laboratory.

Redding, Chip↗
NASA NTRS2005

Reliability Assessment of Advanced Flip-clip Interconnect Electronic Package Assemblies under Extreme Cold Temperatures (-190 and -120 C)

Flip-chip interconnect electronic package boards have been assembled, underfilled, non-destructively evaluated and subsequently subjected to extreme temperature thermal cycling to assess the reliability of this advanced packaging interconnect technology for future deep space, long-term, extreme temperature missions. In this very preliminary study, the employed temperature range covers military specifications (-55 C to 100 C), extreme cold Martian (-120 C to 115 C) and asteroid Nereus (-180 C to 25 C) environments. The resistance of daisy-chained, flip-chip interconnects were measured at room temperature and at various intervals as a function of extreme temperature thermal cycling. Electrical resistance measurements are reported and the tests to date have not shown significant change in resistance as a function of extreme temperature thermal cycling. However, the change in interconnect resistance becomes more noticeable with increasing number of thermal cycles. Further research work has been carried out to understand the reliability of flip-chip interconnect packages under extreme temperature applications (-190 C to 85 C) via continuously monitoring the daisy chain resistance. Adaptation of suitable diagnostic techniques to identify the failure mechanisms is in progress. This presentation will describe the experimental test results of flip-chip testing under extreme temperatures.

thermal cycling↗
DOE OSTI2025

Incubating advances in integrated photonics with emerging sensing and computational capabilities

As photonic technologies grow in multidimensional aspects, integrated photonics holds a unique position and continuously presents enormous possibilities for research communities. Applications include data centers, environmental monitoring, medical diagnosis, and highly compact communication components, with further possibilities continuously growing. Herein, we review state-of-the-art integrated photonic on-chip sensors that operate in the visible to mid-infrared wavelength region on various material platforms. Among the different materials, architectures, and technologies leading the way for on-chip sensors, we discuss the optical sensing principles that are commonly applied to biochemical and gas sensing. Our focus is on passive optical waveguides, including dispersion-engineered metamaterial-based structures, which are essential for enhancing the interaction between light and analytes in chip-scale sensors. We harness a diverse array of cutting-edge sensing technologies, heralding a revolutionary on-chip sensing paradigm. Our arsenal includes refractive-index-based sensing, plasmonics, and spectroscopy, which forge an unparalleled foundation for innovation and precision. Furthermore, we include a brief discussion of recent trends and computational concepts, incorporating Artificial Intelligence & Machine Learning (AI/ML) and deep learning approaches over the past few years to improve the qualitative and quantitative analysis of sensor measurements.

Jain, Sourabh (ORCID:0000000279923275)↗
DOE OSTI2024

In situ counter-diffusion crystallization and long-term crystal preservation in microfluidic fixed targets for serial crystallography

Compared with batch and vapor diffusion methods, counter diffusion can generate larger and higher-quality protein crystals yielding improved diffraction data and higher-resolution structures. Typically, counter-diffusion experiments are conducted in elongated chambers, such as glass capillaries, and the crystals are either directly measured in the capillary or extracted and mounted at the X-ray beamline. Despite the advantages of counter-diffusion protein crystallization, there are few fixed-target devices that utilize counter diffusion for crystallization. In this article, different designs of user-friendly counter-diffusion chambers are presented which can be used to grow large protein crystals in a 2D polymer microfluidic fixed-target chip. Methods for rapid chip fabrication using commercially available thin-film materials such as Mylar, propylene and Kapton are also detailed. Rules of thumb are provided to tune the nucleation and crystal growth to meet users' needs while minimizing sample consumption. These designs provide a reliable approach to forming large crystals and maintaining their hydration for weeks and even months. This allows ample time to grow, select and preserve the best crystal batches before X-ray beam time. Importantly, the fixed-target microfluidic chip has a low background scatter and can be directly used at beamlines without any crystal handling, enabling crystal quality to be preserved. The approach is demonstrated with serial diffraction of photoactive yellow protein, yielding 1.32 Å resolution at room temperature. Fabrication of this standard microfluidic chip with commercially available thin films greatly simplifies fabrication and provides enhanced stability under vacuum. These advances will further broaden microfluidic fixed-target utilization by crystallographers.

Liu, Zhongrui↗
DOE OSTI2024

Single-mode squeezed-light generation and tomography with an integrated optical parametric oscillator

Quantum optical technologies promise advances in sensing, computing, and communication. A key resource is squeezed light, where quantum noise is redistributed between optical quadratures. We introduce a monolithic, chip-scale platform that exploits the χ (2) nonlinearity of a thin-film lithium niobate (TFLN) resonator device to efficiently generate squeezed states of light. Our system integrates all essential components—except for the laser and two detectors—on a single chip with an area of one square centimeter, reducing the size, operational complexity, and power consumption associated with conventional setups. Using the balanced homodyne measurement subsystem that we implemented on the same chip, we measure a squeezing of 0.55 decibels and an anti-squeezing of 1.55 decibels. We use 20 milliwatts of input power to generate the parametric oscillator pump field by using second harmonic generation on the same chip. Our work represents a step toward compact and efficient quantum optical systems posed to leverage the rapid advances in integrated nonlinear and quantum photonics.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2025

Physical Testing of The PSEC5 ASIC

The PSEC5 ASIC is a high-speed waveform sampling chip designed for ultra-fast timing detectors, offering up to 40 GSPS sampling with 10-bit resolution. This makes it well-suited for applications requiring fine time resolution, such as MCPs and LGADs. This work focuses on the physical testing and validation of the chip s internal clocking and SPI-controlled registers. Testing began with inspection of schematics and the prototype to identify and resolve design issues. Then, custom firmware was developed for an Arduino controller to interface with the chip via SPI, enabling read and write access to key control registers. Results confirm that the VCO operates between ~3.2 4.0 GHz and remains stable under non-VCOVDD fluctuations. The Division Ratio register enables frequency division by known factors (256, 128, 64, etc.), indicating a pre-division frequency of 3.2 GHz when the digital band is unmodified. While most registers responded correctly, some issues were observed, including unexpected current draw and unstable discriminator behavior. Overall, the chip shows promising functionality, but further work is needed to understand the state of the read only registers and address the existing issues. Continued testing and firmware development will be critical to ensuring reliable integration into detector systems.

Fahey, Alexander [Unlisted, US]↗
DOE OSTI2025

The ETROC2 as the Final Version for CMS Endcap Timing Layer (ETL) Upgrade

The ETROC (Endcap Timing Readout Chip) is being developed for the LGAD-based CMS Endcap Timing Layer (ETL) at HL-LHC. The ETL on each side of the interaction region will be instrumented with a two-disk system of MIP-sensitive LGAD (Low Gain Avalanche Diodes) silicon devices, read out by ETROCs for precision timing measurement with down to ~30 ps timing resolution per track. The ETROC is designed to handle a 16 x 16 pixel cell matrix, with each pixel being 1.3 mm x 1.3 mm to match the LGAD sensor pixel size. The front-end design for preamplifier and discriminator has been specifically optimized for the reduced LGAD signals, with enough flexibilities to meet the ETL specific needs for time resolution, power budget and radiation profile. The ETROC chip is implemented in a commercial 65nm CMOS process. Each channel consists of a preamplifier, a discriminator, a TDC used for TOA (Time Of Arrival) and TOT (Time Over Threshold) measurements, and a memory for data storage and readout. An in-pixel auto threshold calibration is included, along with a self-testing pattern generator. The TOT is used for time-walk correction of the TOA measurement. The detailed hit information (TOA and TOT) from each cell will be read out from a local circular buffer after each Level-1 Accept (about 1 MHz). In addition, a charge injection circuit is implemented to allow for testing and calibration. For more detailed monitoring of the signal pulses, waveform sampling circuits are included for one pixel. The clock distribution is based on a 16x16 H-tree design with a shielding structure to alleviate potential interference. The global peripheral circuits include a PLL, a phase shifter, an I2C slave controller, a fast control block, a global readout, and a data driver along with an efuse and temperature sensor. The ETROC builds event data frames for each L1A selected event and is also capable of providing L1 trigger information for user-defined delayed hits. The main design challenge is how to extract precision timing information from the small LGAD signals in the presence of high irradiation fluence, while keeping the power consumption and digital activity low. The ETL design goal for the time resolution of 50 ps per hit is required to achieve a 35 ps arrival time measurement for a MIP particle, which has its track registered in two ETL disk layers. The LGAD contribution is known to be about 30 ps, this means that the jitter from the ETROC has to be kept below 40 ps. The ETROC2 is the first full size full functionality prototype design fully compatible with the final chip specifications for CMS ETL and now becomes the final version. The ETROC2 chips have been extensively tested. We will present here new testing results including the bump bonding yield improvement study, the time walk correction (TWC) generality study with one pixel TWC applying to all pixels, the final SEU testing using both heavy ion and proton beam, more beam test studies including different sensors, and readiness for the ETROC2 production for CMS ETL upgrade.

Liu, Tiehui [Fermilab] (ORCID:0009000765225605)↗
DOE OSTI2025

Automating Testing of DUNE Electronics via a Finite State Machine

The Deep Underground Neutrino Experiment (DUNE) is a flagship international collaboration designed to study neutrinos tiny, nearly massless particles that may hold answers to fundamental questions about the Universe. Fermilab s Robotic Test Stand (RTS) plays a critical role in ensuring the quality of approximately 50,000 Application-Specific Integrated Circuit (ASIC) chips that will be used in DUNE s massive liquid argon detectors. These electronics will be inside the cryostat; therefore, they will need to have a high yield of working chips and low noise. To improve the automation and reliability of the RTS, this project focused on designing and implementing a Python-based finite state machine (FSM) to manage chip handling workflows. The FSM was developed as a modular software framework to coordinate robotic arm movements, manage chip tray positions, and monitor system states during testing. Key features include robust error handling routines, a pause/resume system for safe mid-cycle interruptions, and a simulation mode for iterative testing without hardware dependencies. The system was designed to prepare for seamless integration with RTS hardware components such as the robotic arm and vision system. This integration will streamline collaboration and enable efficient deployment of updates across the six total institutions performing testing. The outcomes of this internship contribute to Fermilab s mission to advance high-energy physics and support the DOE s national goals by directly improving the testing of equipment to be used in DUNE. The project also provided valuable experience in software design and contributing to the success of DUNE.

Kang, Caleb [William Rainey Harper Coll.]↗
DOE OSTI2025

Performance of the AstroPix Prototype Module for the Barrel Imaging Calorimeter at the ePIC Detector and in Space-Based Payloads

AstroPix is a high-voltage CMOS (HV-CMOS) monolithic active pixel sensor originally developed to enable precision gamma-ray imaging and spectroscopy in the medium-energy regime (~100 keV–100 MeV) based on the groundwork laid by ATLASpix and MuPix. It features a 500 μm pixel pitch, in-pixel amplification and digitization, and low power consumption (~3-4 mW/cm2), making it scalable for large-area, multilayer telescope detector planes. The detectors have a designed dynamic range of 25 keV to 700 keV. With these features, AstroPix meets the requirements of future space-based high-energy telescopes and the imaging layers of the Barrel Imaging Calorimeter (BIC) in the Electron-Proton/Ion Collider (ePIC) detector at the future Electron-Ion Collider (EIC). For the space-based payload, AstroPix is being integrated into sounding rocket and balloon payloads to demonstrate the technical readiness of the devices. For BIC, AstroPix-based imaging layers interleaved within the lead/scintillating-fiber (Pb/SciFi) sampling calorimeter provide granular shower imaging, enabling key performance features such as electron/pion or gamma/neutral pion separation. As part of the ongoing detector R&D efforts, we have been testing various AstroPix_v3 configurations: the single chip, a quad-chip assembly, a three-layer stack of quad chips, and a 9-chip module that represents the smallest prototype unit of the BIC imaging layer. This presentation will highlight recent performance test results from these AstroPix detector configurations.

Kim, Bobae (ORCID:0000000295396815)↗
DOE OSTI2026

Fine-Grained Power and Energy Attribution on AMD GPU/APU-Based Exascale Nodes

Modern exascale GPU- and APU-based systems provide multiple power and energy sensors, but differences in scope, update rate, timing, and filtering complicate the attribution of short-lived accelerator activity. This paper presents a methodology to characterize and correct these effects on Cray EX systems with AMD Instinct MI250X GPUs (Frontier) and MI300A APUs (Portage). Using controlled square-wave workloads, we quantify update intervals, delay, aliasing, and variability across up to 512 GPUs and 480 APUs with on-chip (rocm-smi/amd-smi) and off-chip Cray Power Management sensors. We reconstruct power from cumulative energy counters to achieve faster response times, validate it against on-chip, off-chip, and node-level sensors, and integrate the resulting streams into a Score-P/PAPI-based tool for time-aligned, phase-level attribution. Applied to rocHPL, rocHPL-MxP, and HPG-MxP, the method separates energy savings due to reduced runtime from changes in power. Mixed precision reduces node energy on Frontier by 79% for rocHPL-MxP and 31% for HPG-MxP, with similar trends on Portage. These results provide portable guidance for sensor validation and power-aware optimization on current and future exascale systems.

Mcdaniel, Adam [ORNL] (ORCID:000000016926028X)↗
NASA NTRS1968

Multichip packaging with thermal insulation

Thermal insulation technique permits low and high power electronic chips to operate in the same package without thermal cross-coupling. An alumina glass shield thermally isolates the low power chip from the high power chip while Kovar substrate acts as a heat sink to remove heat from the high power chip.

Mc Inturff, R. G.↗
NASA NTRS1971

Design, development, fabrication and delivery of register and multiplexer units

Two complementary MOS monolithic chip types were developed, which contain a register and multiplexer unit to be used in the central processing unit of a digital computer. The partition of the logic into a chip size consistent with the characteristics of the packages is discussed. The logic was implemented by specially configured circuitry designed to layout, as well as to optimize, performance by taking advantage of the properties of CMOS logic. Of several approaches considered for generating LSI CMOS arrays, the CMOS standard cell array design technique was selected. These design automation techniques were used to generate the chip layout, art work and working master plates, followed by the fabrication and testing of the two chip types. Sixty functional LSI arrays were delivered.

Feller, A.↗
NASA NTRS1979

CMOS-array design-automation techniques

Thirty four page report discusses design of 4,096-bit complementary metal oxide semiconductor (CMOS) read-only memory (ROM). CMOSROM is either mask or laser programable. Report is divided into six sections; section one describes background of ROM chips; section two presents design goals for chip; section three discusses chip implementation and chip statistics; conclusions and recommendations are given in sections four thru six.

Feller, A.↗
NASA NTRS1979

Feasibility study of silicon nitride protection of plastic encapsulated semiconductors

The application of low temperature silicon nitride protective layers on wire bonded integrated circuits mounted on lead frame assemblies is reported. An evaluation of the mechanical and electrical compatibility of both plasma nitride and photochemical silicon nitride (photonitride) passivations (parallel evaluations) of integrated circuits which were then encapsulated in plastic is described. Photonitride passivation is compatible with all wire bonded lead frame assemblies, with or without initial chip passivation. Plasma nitride passivation of lead frame assemblies is possible only if the chip is passivated before lead frame assembly. The survival rate after the environmental test sequence of devices with a coating of plasma nitride on the chip and a coating of either plasma nitride or photonitride over the assembled device is significantly greater than that of devices assembled with no nitride protective coating over either chip or lead frame.

Peters, J. W.↗
NASA NTRS1979

Design, processing and testing of LSI arrays, hybrid microelectronics task

Mathematical cost models previously developed for hybrid microelectronic subsystems were refined and expanded. Rework terms related to substrate fabrication, nonrecurring developmental and manufacturing operations, and prototype production are included. Sample computer programs were written to demonstrate hybrid microelectric applications of these cost models. Computer programs were generated to calculate and analyze values for the total microelectronics costs. Large scale integrated (LST) chips utilizing tape chip carrier technology were studied. The feasibility of interconnecting arrays of LSU chips utilizing tape chip carrier and semiautomatic wire bonding technology was demonstrated.

Himmel, R. P.↗