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At least 541 records · Page 30

Towards an Open, Distributed Software Architecture for UxS Operations

To address the growing need to evaluate, test, and certify an ever expanding ecosystem of UxS platforms in preparation of cultural integration, NASA Langley Research Center's Autonomy Incubator (AI) has taken on the challenge of developing a software framework in which UxS platforms developed by third parties can be integrated into a single system which provides evaluation and testing, mission planning and operation, and out-of-the-box autonomy and data fusion capabilities. This software framework, named AEON (Autonomous Entity Operations Network), has two main goals. The first goal is the development of a cross-platform, extensible, onboard software system that provides autonomy at the mission execution and course-planning level, a highly configurable data fusion framework sensitive to the platform's available sensor hardware, and plug-and-play compatibility with a wide array of computer systems, sensors, software, and controls hardware. The second goal is the development of a ground control system that acts as a test-bed for integration of the proposed heterogeneous fleet, and allows for complex mission planning, tracking, and debugging capabilities. The ground control system should also be highly extensible and allow plug-and-play interoperability with third party software systems. In order to achieve these goals, this paper proposes an open, distributed software architecture which utilizes at its core the Data Distribution Service (DDS) standards, established by the Object Management Group (OMG), for inter-process communication and data flow. The design decisions proposed herein leverage the advantages of existing robotics software architectures and the DDS standards to develop software that is scalable, high-performance, fault tolerant, modular, and readily interoperable with external platforms and software.

Cross, Charles D.↗

Advanced Wireless Sensor Nodes - MSFC

NASA field center Marshall Space Flight Center (Huntsville, AL), has invested in advanced wireless sensor technology development. Developments for a wireless microcontroller back-end were primarily focused on the commercial Synapse Wireless family of devices. These devices have many useful features for NASA applications, good characteristics and the ability to be programmed Over-The-Air (OTA). The effort has focused on two widely used sensor types, mechanical strain gauges and thermal sensors. Mechanical strain gauges are used extensively in NASA structural testing and even on vehicle instrumentation systems. Additionally, thermal monitoring with many types of sensors is extensively used. These thermal sensors include thermocouples of all types, resistive temperature devices (RTDs), diodes and other thermal sensor types. The wireless thermal board will accommodate all of these types of sensor inputs to an analog front end. The analog front end on each of the sensors interfaces to the Synapse wireless microcontroller, based on the Atmel Atmega128 device. Once the analog sensor output data is digitized by the onboard analog to digital converter (A/D), the data is available for analysis, computation or transmission. Various hardware features allow custom embedded software to manage battery power to enhance battery life. This technology development fits nicely into using numerous additional sensor front ends, including some of the low-cost printed circuit board capacitive moisture content sensors currently being developed at Auburn University.

Varnavas, Kosta↗

IMAPS Device Packaging Conference 2017 - Engineered Micro Systems & Devices Track

NASA field center Marshall Space Flight Center (Huntsville, AL), has invested in advanced wireless sensor technology development. Developments for a wireless microcontroller back-end were primarily focused on the commercial Synapse Wireless family of devices. These devices have many useful features for NASA applications, good characteristics and the ability to be programmed Over-The-Air (OTA). The effort has focused on two widely used sensor types, mechanical strain gauges and thermal sensors. Mechanical strain gauges are used extensively in NASA structural testing and even on vehicle instrumentation systems. Additionally, thermal monitoring with many types of sensors is extensively used. These thermal sensors include thermocouples of all types, resistive temperature devices (RTDs), diodes and other thermal sensor types. The wireless thermal board will accommodate all of these types of sensor inputs to an analog front end. The analog front end on each of the sensors interfaces to the Synapse wireless microcontroller, based on the Atmel Atmega128 device. Once the analog sensor output data is digitized by the onboard analog to digital converter (A/D), the data is available for analysis, computation or transmission. Various hardware features allow custom embedded software to manage battery power to enhance battery life. This technology development fits nicely into using numerous additional sensor front ends, including some of the low-cost printed circuit board capacitive moisture content sensors currently being developed at Auburn University.

Varnavas, Kosta↗

NASA’s Space Launch System: Comprehensive Test Program Leads to Mission Success during Artemis I Flight Test

NASA’s SLS (Space Launch System) rocket had a successful first launch on Nov. 16, 2022, sending an uncrewed Orion spacecraft to the Moon on the agency’s Artemis I mission. Ten 6U CubeSats were also deployed from SLS during the mission. Orbital insertion parameters, including insertion velocity and altitude, were within hundredths and tenths of a percent from predicted values, corroborating data collected from the individual elements that showed similar performance accuracy. While launch remains the main test – and Artemis I was a true test flight – to collect data, confirm and refine computer models, and validate hardware test data, multiple test programs led up to the first flight and enabled the historic launch. Additionally, SLS was designed from the beginning to be a crew-rated launch vehicle, and teams put the astronauts who will fly on it at the forefront of the development process. This paper and presentation will cover the SLS design and development programs that led to the successful Artemis I mission, and which have set the stage to send the first astronauts back to cislunar space since the Apollo 17 crew in 1972.

John Honeycutt↗

Comprehensive Test Program of NASA's Space Launch System Rocket Leads to Successful Artemis Mission

NASA’s SLS (Space Launch System) rocket had a successful first launch on Nov. 16, 2022, sending an uncrewed Orion spacecraft to the Moon on the agency’s Artemis I mission. Ten 6U CubeSats were also deployed from SLS during the mission. Orbital insertion parameters, including insertion velocity and altitude, were within hundredths and tenths of a percent from predicted values, corroborating data collected from the individual elements that showed similar performance accuracy. While launch remains the main test – and Artemis I was a true test flight – to collect data, confirm and refine computer models, and validate hardware test data, multiple test programs led up to the first flight and enabled the historic launch. Additionally, SLS was designed from the beginning to be a crew-rated launch vehicle, and teams put the astronauts who will fly on it at the forefront of the development process. This paper and presentation will cover the SLS design and development programs that led to the successful Artemis I mission, and which have set the stage to send the first astronauts back to cislunar space since the Apollo 17 crew in 1972.

John Honeycutt↗

Independent Orbiter Assessment (IOA): Analysis of the backup flight system

The results of the Independent Orbiter Assessment (IOA) of the Failure Modes and Effects Analysis (FMEA) and Critical Items List (CIL) are presented. The IOA approach features a top-down analysis of the hardware to determine failure modes, criticality, and potential critical items. To preserve independence, this analysis was accomplished without reliance upon the results contained within the NASA FMEA/CIL documentation. This report documents the analysis results corresponding to the Orbiter Backup Flight System (BFS) hardware. The BFS hardware consists of one General Purpose Computer (GPC) loaded with backup flight software and the components used to engage/disengage that unique GPC. Specifically, the BFS hardware includes the following: DDU (Display Driver Unit), BFC (Backup Flight Controller), GPC (General Purpose Computer), switches (engage, disengage, GPC, CRT), and circuit protectors (fuses, circuit breakers). The IOA analysis process utilized available BFS hardware drawings and schematics for defining hardware assemblies, components, and hardware items. Each level of hardware was evaluated and analyzed for possible failure modes and effects. Criticality was assigned based upon the severity of the effect for each failure mode. Of the failure modes analyzed, 19 could potentially result in a loss of life and/or loss of vehicle.

Prust, E. E.↗

Integrating Commercial Off-The-Shelf (COTS) graphics and extended memory packages with CLIPS

This paper addresses the question of how to mix CLIPS with graphics and how to overcome PC's memory limitations by using the extended memory available in the computer. By adding graphics and extended memory capabilities, CLIPS can be converted into a complete and powerful system development tool, on the other most economical and popular computer platform. New models of PCs have amazing processing capabilities and graphic resolutions that cannot be ignored and should be used to the fullest of their resources. CLIPS is a powerful expert system development tool, but it cannot be complete without the support of a graphics package needed to create user interfaces and general purpose graphics, or without enough memory to handle large knowledge bases. Now, a well known limitation on the PC's is the usage of real memory which limits CLIPS to use only 640 Kb of real memory, but now that problem can be solved by developing a version of CLIPS that uses extended memory. The user has access of up to 16 MB of memory on 80286 based computers and, practically, all the available memory (4 GB) on computers that use the 80386 processor. So if we give CLIPS a self-configuring graphics package that will automatically detect the graphics hardware and pointing device present in the computer, and we add the availability of the extended memory that exists in the computer (with no special hardware needed), the user will be able to create more powerful systems at a fraction of the cost and on the most popular, portable, and economic platform available such as the PC platform.

Callegari, Andres C.↗

Applying Model-Based Reasoning to the FDIR of the Command and Data Handling Subsystem of the International Space Station

All of the International Space Station (ISS) systems which require computer control depend upon the hardware and software of the Command and Data Handling System (C&DH) system, currently a network of over 30 386-class computers called Multiplexor/Dimultiplexors (MDMs)[18]. The Caution and Warning System (C&W)[7], a set of software tasks that runs on the MDMs, is responsible for detecting, classifying, and reporting errors in all ISS subsystems including the C&DH. Fault Detection, Isolation and Recovery (FDIR) of these errors is typically handled with a combination of automatic and human effort. We are developing an Advanced Diagnostic System (ADS) to augment the C&W system with decision support tools to aid in root cause analysis as well as resolve differing human and machine C&DH state estimates. These tools which draw from sources in model-based reasoning[ 16,291, will improve the speed and accuracy of flight controllers by reducing the uncertainty in C&DH state estimation, allowing for a more complete assessment of risk. We have run tests with ISS telemetry and focus on those C&W events which relate to the C&DH system itself. This paper describes our initial results and subsequent plans.

Robinson, Peter↗

The science of computing - Parallel computation

Although parallel computation architectures have been known for computers since the 1920s, it was only in the 1970s that microelectronic components technologies advanced to the point where it became feasible to incorporate multiple processors in one machine. Concommitantly, the development of algorithms for parallel processing also lagged due to hardware limitations. The speed of computing with solid-state chips is limited by gate switching delays. The physical limit implies that a 1 Gflop operational speed is the maximum for sequential processors. A computer recently introduced features a 'hypercube' architecture with 128 processors connected in networks at 5, 6 or 7 points per grid, depending on the design choice. Its computing speed rivals that of supercomputers, but at a fraction of the cost. The added speed with less hardware is due to parallel processing, which utilizes algorithms representing different parts of an equation that can be broken into simpler statements and processed simultaneously. Present, highly developed computer languages like FORTRAN, PASCAL, COBOL, etc., rely on sequential instructions. Thus, increased emphasis will now be directed at parallel processing algorithms to exploit the new architectures.

Denning, P. J.↗

Initial test results on state estimation on the SCOLE mast

Modal state estimation tests are performed on the SCOLE mast for the fixed Shuttle platform case. Kalman filter state estimation results from a five mode computer model of the SCOLE mast, developed from a finite element analysis, are compared with those state estimates obtained from laboratory tests. Two comparison runs are presented, one an excitation of the first two bending modes, another, an excitation of the first torsional mode of the mast. Results from both runs show poor agreement in modal estimation between the computer model simulations and the laboratory test data. At present, the reason(s) for this poor performance is unknown. Both the laboratory hardware and software and the computer model are being checked for possible sources of errors. Further computer simulations as well as laboratory testing will be performed.

Sparks, D., Jr.↗

Hidden Statistics Approach to Quantum Simulations

Recent advances in quantum information theory have inspired an explosion of interest in new quantum algorithms for solving hard computational (quantum and non-quantum) problems. The basic principle of quantum computation is that the quantum properties can be used to represent structure data, and that quantum mechanisms can be devised and built to perform operations with this data. Three basic non-classical properties of quantum mechanics superposition, entanglement, and direct-product decomposability were main reasons for optimism about capabilities of quantum computers that promised simultaneous processing of large massifs of highly correlated data. Unfortunately, these advantages of quantum mechanics came with a high price. One major problem is keeping the components of the computer in a coherent state, as the slightest interaction with the external world would cause the system to decohere. That is why the hardware implementation of a quantum computer is still unsolved. The basic idea of this work is to create a new kind of dynamical system that would preserve the main three properties of quantum physics superposition, entanglement, and direct-product decomposability while allowing one to measure its state variables using classical methods. In other words, such a system would reinforce the advantages and minimize limitations of both quantum and classical aspects. Based upon a concept of hidden statistics, a new kind of dynamical system for simulation of Schroedinger equation is proposed. The system represents a modified Madelung version of Schroedinger equation. It preserves superposition, entanglement, and direct-product decomposability while allowing one to measure its state variables using classical methods. Such an optimal combination of characteristics is a perfect match for simulating quantum systems. The model includes a transitional component of quantum potential (that has been overlooked in previous treatment of the Madelung equation). The role of the transitional potential is to provide a jump from a deterministic state to a random state with prescribed probability density. This jump is triggered by blowup instability due to violation of Lipschitz condition generated by the quantum potential. As a result, the dynamics attains quantum properties on a classical scale. The model can be implemented physically as an analog VLSI-based (very-large-scale integration-based) computer, or numerically on a digital computer. This work opens a way of developing fundamentally new algorithms for quantum simulations of exponentially complex problems that expand NASA capabilities in conducting space activities. It has been illustrated that the complexity of simulations of particle interaction can be reduced from an exponential one to a polynomial one.

Zak, Michail↗

Interfacing laboratory instruments to multiuser, virtual memory computers

Incentives, problems and solutions associated with interfacing laboratory equipment with multiuser, virtual memory computers are presented. The major difficulty concerns how to utilize these computers effectively in a medium sized research group. This entails optimization of hardware interconnections and software to facilitate multiple instrument control, data acquisition and processing. The architecture of the system that was devised, and associated programming and subroutines are described. An example program involving computer controlled hardware for ultrasonic scan imaging is provided to illustrate the operational features.

Generazio, Edward R.↗

Interfacing laboratory instruments to multiuser, virtual memory computers

Incentives, problems and solutions associated with interfacing laboratory equipment with multiuser, virtual memory computers are presented. The major difficulty concerns how to utilize these computers effectively in a medium sized research group. This entails optimization of hardware interconnections and software to facilitate multiple instrument control, data acquisition and processing. The architecture of the system that was devised, and associated programming and subroutines are described. An example program involving computer controlled hardware for ultrasonic scan imaging is provided to illustrate the operational features.

Generazio, Edward R.↗

TSE computers - A means for massively parallel computations

A description is presented of hardware concepts for building a massively parallel processing system for two-dimensional data. The processing system is to use logic arrays of 128 x 128 elements which perform over 16 thousand operations simultaneously. Attention is given to image data, logic arrays, basic image logic functions, a prototype negator, an interleaver device, image logic circuits, and an image memory circuit.

Strong, J. P., III↗

Pulsed holography for combustion diagnostics

Image reconstruction and data extraction techniques were considered with respect to their application to combustion diagnostics. A system was designed and constructed that possesses sufficient stability and resolution to make quantitative data extraction possible. Example data were manually processed using the system to demonstrate its feasibility for the purpose intended. The system was interfaced with the PDP-11-04 computer for maximum design capability. It was concluded that the use of specialized digital hardware controlled by a relatively small computer provides the best combination of accuracy, speed, and versatility for this particular problem area.

Klein, N.↗

RISC Processors and High Performance Computing

In this tutorial, we will discuss top five current RISC microprocessors: The IBM Power2, which is used in the IBM RS6000/590 workstation and in the IBM SP2 parallel supercomputer, the DEC Alpha, which is in the DEC Alpha workstation and in the Cray T3D; the MIPS R8000, which is used in the SGI Power Challenge; the HP PA-RISC 7100, which is used in the HP 700 series workstations and in the Convex Exemplar; and the Cray proprietary processor, which is used in the new Cray J916. The architecture of these microprocessors will first be presented. The effective performance of these processors will then be compared, both by citing standard benchmarks and also in the context of implementing a real applications. In the process, different programming models such as data parallel (CM Fortran and HPF) and message passing (PVM and MPI) will be introduced and compared. The latest NAS Parallel Benchmark (NPB) absolute performance and performance per dollar figures will be presented. The next generation of the NP13 will also be described. The tutorial will conclude with a discussion of general trends in the field of high performance computing, including likely future developments in hardware and software technology, and the relative roles of vector supercomputers tightly coupled parallel computers, and clusters of workstations. This tutorial will provide a unique cross-machine comparison not available elsewhere.

Saini, Subhash↗

Economical Implementation of a Filter Engine in an FPGA

A logic design has been conceived for a field-programmable gate array (FPGA) that would implement a complex system of multiple digital state-space filters. The main innovative aspect of this design lies in providing for reuse of parts of the FPGA hardware to perform different parts of the filter computations at different times, in such a manner as to enable the timely performance of all required computations in the face of limitations on available FPGA hardware resources. The implementation of the digital state-space filter involves matrix vector multiplications, which, in the absence of the present innovation, would ordinarily necessitate some multiplexing of vector elements and/or routing of data flows along multiple paths. The design concept calls for implementing vector registers as shift registers to simplify operand access to multipliers and accumulators, obviating both multiplexing and routing of data along multiple paths. Each vector register would be reused for different parts of a calculation. Outputs would always be drawn from the same register, and inputs would always be loaded into the same register. A simple state machine would control each filter. The output of a given filter would be passed to the next filter, accompanied by a "valid" signal, which would start the state machine of the next filter. Multiple filter modules would share a multiplication/accumulation arithmetic unit. The filter computations would be timed by use of a clock having a frequency high enough, relative to the input and output data rate, to provide enough cycles for matrix and vector arithmetic operations. This design concept could prove beneficial in numerous applications in which digital filters are used and/or vectors are multiplied by coefficient matrices. Examples of such applications include general signal processing, filtering of signals in control systems, processing of geophysical measurements, and medical imaging. For these and other applications, it could be advantageous to combine compact FPGA digital filter implementations with other application-specific logic implementations on single integrated-circuit chips. An FPGA could readily be tailored to implement a variety of filters because the filter coefficients would be loaded into memory at startup.

Kowalski, James E.↗