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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 541 records · Page 30
All sourcesNASA NTRSDOE OSTI
NASA NTRS1985

The design and implementation of cost-effective algorithms for direct solution of banded linear systems on the vector processor system 32 supercomputer

The problem of solving banded linear systems by direct (non-iterative) techniques on the Vector Processor System (VPS) 32 supercomputer is considered. Two efficient direct methods for solving banded linear systems on the VPS 32 are described. The vector cyclic reduction (VCR) algorithm is discussed in detail. The performance of the VCR on a three parameter model problem is also illustrated. The VCR is an adaptation of the conventional point cyclic reduction algorithm. The second direct method is the Customized Reduction of Augmented Triangles' (CRAT). CRAT has the dominant characteristics of an efficient VPS 32 algorithm. CRAT is tailored to the pipeline architecture of the VPS 32 and as a consequence the algorithm is implicitly vectorizable.

Samba, A. S.↗
NASA NTRS1985

Task granularity studies on a many-processor CRAY X-MP

A hybrid granularity model is proposed for general concurrent solution. It is applied to the triangular factorization of a dense matrix ranging in size from 4 to 1024. Concurrency is achieved at two levels: (1) with small (micro) task granularity and (2) with large (blocked) task granularity. Relevance to a many-processor CRAY X-MP is demonstrated by simulation.

Calahan, D. A.↗
NASA NTRS1984

The baseband processor in future satellite communication systems

This paper provides a description of a baseband processor planned for satellite communication systems operating in Ka band. The satellite based interconnection of individual earth terminals is described in terms of uplink and downlink message formats, and the on-board processing signal flow. Advanced technology requirements and developments are reviewed including current activity in custom large scale integrated circuit development.

Thomas, R. E.↗
NASA NTRS1986

Negative base encoding in optical linear algebra processors

In the digital multiplication by analog convolution algorithm, the bits of two encoded numbers are convolved to form the product of the two numbers in mixed binary representation; this output can be easily converted to binary. Attention is presently given to negative base encoding, treating base -2 initially, and then showing that the negative base system can be readily extended to any radix. In general, negative base encoding in optical linear algebra processors represents a more efficient technique than either sign magnitude or 2's complement encoding, when the additions of digitally encoded products are performed in parallel.

Perlee, C.↗
NASA NTRS1986

Twos-complement data processing form improved encoded matrix-vector processors

A new method for handling bipolar data by twos-complement representation is detailed. This technique requires fewer bits, uses simpler optical processor devices (fewer channels), and provides a higher processing rate and throughput. It is directly extendable to more complex matrix operations because of its data flow property and requires only a modest increase in the complexity of the digital support system.

Taylor, B. K.↗
NASA NTRS1986

Application of a VLSI vector quantization processor to real-time speech coding

Attention is given to a working vector quantization processor for speech coding that is based on a first-generation VLSI chip which efficiently performs the pattern-matching operation needed for the codebook search process (CPS). Using this chip, the CPS architecture has been successfully incorporated into a compact, single-board Vector PCM implementation operating at 7-18 kbits/sec. A real time Adaptive Vector Predictive Coder system using the CPS has also been implemented.

Davidson, G.↗
NASA NTRS1985

Extended testing of a general contextual classifier using the massively parallel processor - Preliminary results and test plans

Earlier encouraging test results of a contextual classifier that combines spatial and spectral information employing a general statistical approach are expanded. The earlier results were of limited meaning because they were produced from small (50-by-50 pixel) data sets. An implementation of the contextual classifier on NASA Goddard's Massively Parallel Processor (MPP) is presented; for the first time the MPP makes feasible the testing of the classifier on large data sets (a 12-hour test on a VAX-11/780 minicomputer now takes 5 minutes on the MPP). The MPP is a Single-Instruction, Multiple Data Stream computer, consisting of 16,384 bit serial microprocessors connected in a 128-by-128 mesh array with each element having data transfer connections with its four nearest neighbors so that the MPP is capable of billions of operations per second. Preliminary results are given (with more expected for the conference) and plans are mentioned for extended testing of the contextual classifier on Thematic Mapper data sets.

Tilton, J. C.↗
NASA NTRS1985

High-speed, automatic controller design considerations for integrating array processor, multi-microprocessor, and host computer system architectures

Modern control systems must typically perform real-time identification and control, as well as coordinate a host of other activities related to user interaction, online graphics, and file management. This paper discusses five global design considerations which are useful to integrate array processor, multimicroprocessor, and host computer system architectures into versatile, high-speed controllers. Such controllers are capable of very high control throughput, and can maintain constant interaction with the nonreal-time or user environment. As an application example, the architecture of a high-speed, closed-loop controller used to actively control helicopter vibration is briefly discussed. Although this system has been designed for use as the controller for real-time rotorcraft dynamics and control studies in a wind tunnel environment, the controller architecture can generally be applied to a wide range of automatic control applications.

Jacklin, S. A.↗
NASA NTRS1985

Concurrent system-level error detection using a watchdog processor

This paper describes the design of a watchdog coprocessor for detecting hardware and software errors. The watchdog executes assertions about the process running on the main computer. Both general purpose an special purpose (used to check systems such as digital signal processors, telephone switching systems, or digital flight controllers) watchdog designs are described. The improvement of error coverage by adding control flow checking facilities is discussed. The implementation of the watchdog as a software process is presented.

Mahmood, A.↗
NASA NTRS1986

Frequency domain laser velocimeter signal processor

A laser velocimeter frequency domain signal processor is described which utilizes smart instrumentation to configure itself to maximize measurement accuracy based on the determined characteristics of the input signals. The stystem provides the same measurement capabilities as the high-speed burst counter in instantaneous measurements of signal frequency, the same automatic gain control and automatic frequency control as the frequency tracker, and the same immunity to signal-to-noise derived errors as the photon correlator. Simulation results demonstrate measurement accuracies of better than 0.2 percent for signal frequencies up to 100 MHz.

Meyers, J. F.↗
NASA NTRS1987

Parallel Analog-to-Digital Image Processor

Proposed integrated-circuit network of many identical units convert analog outputs of imaging arrays of x-ray or infrared detectors to digital outputs. Converter located near imaging detectors, within cryogenic detector package. Because converter output digital, lends itself well to multiplexing and to postprocessing for correction of gain and offset errors peculiar to each picture element and its sampling and conversion circuits. Analog-to-digital image processor is massively parallel system for processing data from array of photodetectors. System built as compact integrated circuit located near local plane. Buffer amplifier for each picture element has different offset.

Lokerson, D. C.↗
NASA NTRS1987

Central Processor Acts as High-Speed DMA Controller

Computer-system architecture enables system host central processor (CP) to make high-speed, direct-memory-access (DMA) data transfers without cost and complexity of adding dedicated DMA controller. New system, CCP used as DMA controller, obviating need for dedicated DMA controller; yet maximum transfer rates equivalent to those obtained with dedicated DMA controller. Useful wherever dedicated DMA controller desired because of required data-transfer rates.

Blaha, Matthew S.↗
NASA NTRS1986

Numerical algorithms for finite element computations on concurrent processors

The work of several graduate students which relate to the NASA grant is briefly summarized. One student has worked on a detailed analysis of the so-called ijk forms of Gaussian elemination and Cholesky factorization on concurrent processors. Another student has worked on the vectorization of the incomplete Cholesky conjugate method on the CYBER 205. Two more students implemented various versions of Gaussian elimination and Cholesky factorization on the FLEX/32.

Ortega, J. M.↗
NASA NTRS1986

Roundoff noise analysis for digital Doppler processors in radar scatterometers

The noise due to finite word length effects for digital Doppler processors (DPP) in radar scatterometers, is analyzed. The roundoff noise-to-signal ratio in the measurement of the radar return signal power is derived. Computer simulations which validate the analytical results are presented. The results can be used in tradeoff studies of hardware design such as number of bits required at each processing stage. The results are used in the design of a DPP for the NASA scatterometer planned to be launched in 1990.

Chi, Chong-Yung↗
NASA NTRS1987

A dual-processor multi-frequency implementation of the FINDS algorithm

This report presents a parallel processing implementation of the FINDS (Fault Inferring Nonlinear Detection System) algorithm on a dual processor configured target flight computer. First, a filter initialization scheme is presented which allows the no-fail filter (NFF) states to be initialized using the first iteration of the flight data. A modified failure isolation strategy, compatible with the new failure detection strategy reported earlier, is discussed and the performance of the new FDI algorithm is analyzed using flight recorded data from the NASA ATOPS B-737 aircraft in a Microwave Landing System (MLS) environment. The results show that low level MLS, IMU, and IAS sensor failures are detected and isolated instantaneously, while accelerometer and rate gyro failures continue to take comparatively longer to detect and isolate. The parallel implementation is accomplished by partitioning the FINDS algorithm into two parts: one based on the translational dynamics and the other based on the rotational kinematics. Finally, a multi-rate implementation of the algorithm is presented yielding significantly low execution times with acceptable estimation and FDI performance.

Godiwala, Pankaj M.↗
NASA NTRS1987

Analysis of the Continuous Stellar Tracking Attitude Reference (CSTAR) attitude rate processor

The Continuous Stellar Tracking Attitude Reference (CSTAR) system is an in-house project for Space Station to provide high accuracy, drift free attitude and angular rate information for the GN&C system. The outputs of the solid state star trackers are processed to provide attitude information; rate data is then derived from the attitude. Rate derivation is based on discrete time polynomial approximation techniques. This gives simple algorithms which allow for interpolation by other users. Attitude rate is modeled as a constant with low amplitude, low frequency sinusoids superimposed. The rate processor is parameterized to account for the effects of random errors, sample rate, data processing rate and perturbation frequency. The baseline system may be characterized as follows: the three sigma attitude accuracy is 0.01 degrees, the three sigma rate accuracy is 0.0001 degrees per second, the sample rate is 100 Hertz, the sampled signal is bandlimited to 0.5 Hertz, and the data processing rate is 10 Hertz. The above system requires a differentiator of length 127. This will track rate perturbations of frequencies less than 0.01 Hertz with low systematic errors.

Uhde-Lacovara, J.↗
NASA NTRS1987

Block iterative restoration of astronomical images with the massively parallel processor

A method is described for algebraic image restoration capable of treating astronomical images. For a typical 500 x 500 image, direct algebraic restoration would require the solution of a 250,000 x 250,000 linear system. The block iterative approach is used to reduce the problem to solving 4900 121 x 121 linear systems. The algorithm was implemented on the Goddard Massively Parallel Processor, which can solve a 121 x 121 system in approximately 0.06 seconds. Examples are shown of the results for various astronomical images.

Heap, Sara R.↗