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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 541 records · Page 30
All sourcesNASA NTRSDOE OSTI
NASA NTRS1987

Maximum likelihood identification using an array processor

Maximum likelihood estimation (MLE) is a method used to calculate the parameters of a dynamic system. It can be applied to a large class of problems and has good statistical properties. The main disadvantage of the MLE method is the amount of computation required. This paper describes how the computation time can be reduced significantly by using an array processor. The estimation of the parameters of a dynamic model of the Space Station is used as an example to evaluate the method.

Sridhar, Banavar↗
NASA NTRS1987

Processor tradeoffs in distributed real-time systems

The problem of the optimization of the design of real-time distributed systems is examined with reference to a class of computer architectures similar to the continuously reconfigurable multiprocessor flight control system structure, CM2FCS. Particular attention is given to the impact of processor replacement and the burn-in time on the probability of dynamic failure and mean cost. The solution is obtained numerically and interpreted in the context of real-time applications.

Krishna, C. M.↗
NASA NTRS1988

Stereoscopic Optical Signal Processor

Optical signal processor produces two-dimensional cross correlation of images from steroscopic video camera in real time. Cross correlation used to identify object, determines distance, or measures movement. Left and right cameras modulate beams from light source for correlation in video detector. Switch in position 1 produces information about range of object viewed by cameras. Position 2 gives information about movement. Position 3 helps to identify object.

Graig, Glenn D.↗
NASA NTRS1987

Interferometry theory for the block 2 processor

Presented is the interferometry theory for the Block 2 processor, including a high-level functional description and a discussion of data structure. The analysis covers the major processing steps: cross-correlation, fringe counter-rotation, transformation to the frequency domain, phase calibration, bandwidth synthesis, and extraction of the observables of amplitude, phase, phase rate, and delay. Also included are analyses for fractional bitshift correction, station clock error, ionosphere correction, and effective frequencies for the observables.

Thomas, J. B.↗
NASA NTRS1987

Estimating the distribution of fault latency in a digital processor

Presented is a statistical approach to measuring fault latency in a digital processor. The method relies on the use of physical fault injection where the duration of the fault injection can be controlled. Although a specific fault's latency period is never directly measured, the method indirectly determines the distribution of fault latency.

Ellis, Erik L.↗
NASA NTRS1988

Investigations on the usefulness of the Massively Parallel Processor for study of electronic properties of atomic and condensed matter systems

The usefulness of the Massively Parallel Processor (MPP) for investigation of electronic structures and hyperfine properties of atomic and condensed matter systems was explored. The major effort was directed towards the preparation of algorithms for parallelization of the computational procedure being used on serial computers for electronic structure calculations in condensed matter systems. Detailed descriptions of investigations and results are reported, including MPP adaptation of self-consistent charge extended Hueckel (SCCEH) procedure, MPP adaptation of the first-principles Hartree-Fock cluster procedure for electronic structures of large molecules and solid state systems, and MPP adaptation of the many-body procedure for atomic systems.

Das, T. P.↗
NASA NTRS1988

The PC/AT compatible computer as a mission control center display processor at Ames-Dryden Flight Research Facility

Since 1982, the Western Aeronautical Test Range of the Ames-Dryden Flight Research Facility has been separating the data acquisition and processing function required on all telemetry pulse code modulation (PCM) data and the display processing function required in the flight research mission control centers (MCCs). These two functions historically have been done on the same set of superminicomputers remote from the MCCs. Removing the display processing function from the realm of the superminis or telemetry-radar acquisition and processing system (TRAPS) and out into the MCCs will allow the research engineers the flexibility to configure their own display processing system to optimize performance during a flight research mission. Meanwhile, the TRAPS will have more time to acquire data. One of the processors chosen is an IBM PC/AT compatible rack-mounted personal computer. This class and type machine will not only allow the transfer of the display processing function into the MCCs, but also allow the research engineers a personalized set of analytic and display tools for use on their own unique sets of data.

Hammons, Kevin R.↗
NASA NTRS1988

The proposal entry processor: Telescience applications for Hubble Space Telescope science operations

The Proposal Entry Processor (PEP) System supports the submission, entry, technical evaluation review, selection and implementation of Hubble Space Telescope (HST) observing proposals. The PEP system is described concentrating on features which illustrate principles of telescience as applied to the HST. These principles are applicable to other observatories, both space and ground based. The PEP proposal forms allow a scientist to specify scientific objectives without becoming needlessly involved in implementation details. The Remote Proposal Submission System (RPSS) allows proposers to submit proposals electronically via Telenet, SPAN, and other networks. The RPSS performs syntax and sematic checks on proposals. The PEP uses a fourth generation database system to store proposal information and to allow general queries and reports. The Transformation subsystem uses an expert system written in OPS5 to cast a scientific description of an observing program into parameters used by the planning and scheduling system. The TACOS system is a natural language database which supports the proposal selection process. Technical evaluations for resource usage and duplicate science are performed using rulebased systems.

Jackson, Robert↗
NASA NTRS1987

Evaluation of a dual processor implementation for a fault inferring nonlinear detection system

The design of a modified fault inferring nonlinear detection system (FINDS) algorithm for a dual-processor configured flight computer is described. The algorithm was changed in order to divide it into its translational dynamics and rotational kinematics and to use it for parallel execution on the flight computer. The FINDS consists of: (1) a no-fail filter (NFF), (2) a set of test-of-mean detection tests, (3) a bank of first order filters to estimate failure levels in individual sensors, and (4) a decision function. NFF filter performance using flight recorded sensor data is analyzed using a filter autoinitialization routine. The failure detection and isolation capability of the partitioned algorithm is evaluated. A multirate implementation for the bias-free and bias filter gain and covariance matrices is discussed.

Godiwala, P. M.↗
NASA NTRS1987

Computation of subsonic base flow on a vector processor

Two-dimensional subsonic laminar compressible base flow has been studied using numerical solutions of the time-dependent Navier-Stokes equations. These solutions were obtained using an explicit finite-difference scheme which is highly efficient on a vector processor. The organization of the code for a CDC CYBER-205 computer is described. Solutions were obtained for Mach 0.4 and 0.6 flows past a slender blunt-based model at moderately high Reynolds numbers. The flow in the wake is unsteady with periodic shedding of vortices from the trailing edge. The computed shedding frequency was found to increase with increasing Reynolds number.

Rudy, D. H.↗
NASA NTRS1988

Direct finite element solution on an optical laboratory matrix-vector processor

The first optical laboratory system results employing a direct LU decomposition solution of a system of linear algebraic equations are presented for a finite element problem solution. This also represents the first laboratory demonstration of the use of sign-magnitude negative number representation as well as new bit partitioning techniques to increase the accuracy of an optical encoded processor beyond the number of bit channels available.

Casasent, David↗
NASA NTRS1988

The PC/AT compatible computer as a mission control center display processor at Ames-Dryden Flight Research Facility

The NASA Ames-Dryden Flight Research Facility's Western Aeronautical Test Range will assign the flight test data display processing function to Mission Control Centers in order to allow research engineers to flexibly configure their own display-processing system to optimize performance during a flight research mission. This will leave the Telemetry Radar Acquisition and Processing System more time to acquire data. One of the processors chosen to handle the display-processing function is an IBM PC/AT-compatible, rack-mounted PC giving engineers a personalized set of analytic and display tools, developed on the basis of off-the-shelf PC/AT-compatible engineering hardware and software items.

Hammons, Kevin R.↗
NASA NTRS1989

Eight-Bit-Slice GaAs General Processor Circuit

Novel GaAs 8-bit slice enables quick and efficient implementation of variety of fast GaAs digital systems ranging from central processing units of computers to special-purpose processors for communications and signal-processing applications. With GaAs 8-bit slice, designers quickly configure and test hearts of many digital systems that demand fast complex arithmetic, fast and sufficient register storage, efficient multiplexing and routing of data words, and ease of control.

Weissman, John↗
NASA NTRS1989

Integrated Semiconductor/Optical Information Processors

Optical information processors made of integrated three-dimensional devices which include optical, electro-optical, and electronic devices. Integration achieved by combination and extension of advanced semiconductor (integrated-circuit) and integrated-optics technology. In integrated device, spatial light modulator fabricated on surface of chip. Leads to miniaturization of sophisticated optical information-processing systems.

Cheng, Li-Jen↗
NASA NTRS1989

Digital Doppler Processor For Spaceborne Scatterometer

Report describes conceptual digital Doppler processor for NASA scatterometer (NSCAT), advanced version of SEASAT spaceborne radar scatterometer used to measure winds near surface of ocean. In NSCAT design, six antennas illuminate surface of ocean with fanshaped beams.

LONG. D. G.↗
NASA NTRS1987

Advanced data management design for autonomous telerobotic systems in space using spaceborne symbolic processors

The use of computers in autonomous telerobots is reaching the point where advanced distributed processing concepts and techniques are needed to support the functioning of Space Station era telerobotic systems. Three major issues that have impact on the design of data management functions in a telerobot are covered. It also presents a design concept that incorporates an intelligent systems manager (ISM) running on a spaceborne symbolic processor (SSP), to address these issues. The first issue is the support of a system-wide control architecture or control philosophy. Salient features of two candidates are presented that impose constraints on data management design. The second issue is the role of data management in terms of system integration. This referes to providing shared or coordinated data processing and storage resources to a variety of telerobotic components such as vision, mechanical sensing, real-time coordinated multiple limb and end effector control, and planning and reasoning. The third issue is hardware that supports symbolic processing in conjunction with standard data I/O and numeric processing. A SSP that currently is seen to be technologically feasible and is being developed is described and used as a baseline in the design concept.

Goforth, Andre↗
NASA NTRS1986

An Ada implementation for fault detection, isolation and reconfiguration using a fault-tolerant processor

The design and implementation, in Ada, of the Fault Detection, Isolation, and Reconfiguration (FDIR) Manager for the triply redundant, tightly synchronized, Fault Tolerant Processor (FTP) are covered. It also examines the suitability of Ada, in the context of the FTP, for real time control tasks. The operational concepts behind the FTP are explained, and the structure of the resultant Ada code is discussed.

Greeley, Gregory L.↗
NASA NTRS1989

Impact of device level faults in a digital avionic processor

This study describes an experimental analysis of the impact of gate and device-level faults in the processor of a Bendix BDX-930 flight control system. Via mixed mode simulation, faults were injected at the gate (stuck-at) and at the transistor levels and, their propagation through the chip to the output pins was measured. The results show that there is little correspondence between a stuck-at and a device-level fault model, as far as error activity or detection within a functional unit is concerned. In so far as error activity outside the injected unit and at the output pins are concerned, the stuck-at and device models track each other. The stuck-at model, however, overestimates, by over 100 percent, the probability of fault propagation to the output pins. An evaluation of the Mean Error Durations and the Mean Time Between Errors at the output pins shows that the stuck-at model significantly underestimates (by 62 percent) the impact of an internal chip fault on the output pins. Finally, the study also quantifies the impact of device fault by location, both internally and at the output pins.

Suk, Ho Kim↗