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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 541 records · Page 30

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NASA NTRS1981

Army/NASA small turboshaft engine digital controls research program

The emphasis of a program to conduct digital controls research for small turboshaft engines is on engine test evaluation of advanced control logic using a flexible microprocessor based digital control system designed specifically for research on advanced control logic. Control software is stored in programmable memory. New control algorithms may be stored in a floppy disk and loaded directly into memory. This feature facilitates comparative evaluation of different advanced control modes. The central processor in the digital control is an Intel 8086 16 bit microprocessor. Control software is programmed in assembly language. Software checkout is accomplished prior to engine test by connecting the digital control to a real time hybrid computer simulation of the engine. The engine currently installed in the facility has a hydromechanical control modified to allow electrohydraulic fuel metering and VG actuation by the digital control. Simulation results are presented which show that the modern control reduces the transient rotor speed droop caused by unanticipated load changes such as cyclic pitch or wind gust transients.

Sellers, J. F.↗

NASA NTRS1982

Recent developments of NASTRAN pre- amd post-processors: Response spectrum analysis (RESPAN) and interactive graphics (GIFTS)

Two specific NASTRAN preprocessors and postprocessors are examined. A postprocessor for dynamic analysis and a graphical interactive package for model generation and review of resuls are presented. A computer program that provides response spectrum analysis capability based on data from NASTRAN finite element model is described and the GIFTS system, a graphic processor to augment NASTRAN is introduced.

Hirt, E. F.↗

DOE OSTI2017

An automatic input/output test experience of FPGA-based logic controller with I/O stimulator - 282

This paper describes an automatic testing approach instead of a traditional manual test for an FPGA-based Logic Controller (FLC). It mainly describes an automatic testing of FLC using an I/O stimulator with the initiated manual action. The FLC was developed by Doosan Heavy Industry and KAERI in S. Korea. We also developed a test-bed like I/O stimulator for a burning test based on the operational scenario. Signal sources from the I/O stimulator contain an analog input, an analog output, a digital input and a digital output, a programmable power supply, an RS232C serial interface, and a dual port Ethernet interface. LabVIEW Programming was used for the automatic testing. The FLC consists of a general processor module (FPM-01), a complex processor module (FPM-02), analog input modules (FAI-01), analog output modules (FAO-01), digital input modules (FDI-01), digital output modules (FDO-01), a data link module (FDL-01), and a network module (FNW-01). Among these, in this paper, automatic digital I/O testing and automatic analog I/O testing are described. In addition, for the accuracy of the automatic testing, two graphic recorders are used. One is the output results of general processor based testing, and the other is the output results of complex processor based testing. These are different company products. Redundancy recording was found in the test results. The test results were synchronized internally with the existing I/O stimulator and externally with two graphic recorders. Calibrations of all of the equipment were made before the system testing. Before the testing started, a test plan and the test procedure were set up in advance, and we performed test scenario-based automatic functional testing for the FLC as the qualification process. It can be several executed depending on the scenario and conditional parameters of the test. For validation of the accuracy and reliability in our automated test, manual testing was also performed. Manual tests were conducted in two ways. The first one was a manual test using Fluke 754 and Fluke 715. The other one was using embedded manual features of the I/O stimulator. By performing the automatic input and output testing using the I/O stimulator, the time and expense of FLC testing can be reduced significantly compared with a conventional manual test. We rechecked the automatic test results using Fluke754 manually. (authors)

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2015

Trinity Benchmarks on the Intel Xeon Phi (Knights Corner)

This report documents the early experiences with porting and performance analysis of the Tri-Lab Trinity benchmark applications on Intel Xeon Phi (Knights Corner) (KNC) processor. KNC, the second generation of the Intel Many Integrated Core (MIC) architectures, uses a large number of small P54C-x86 cores with wide vector units and is deployed as PCI bus attached process accelerators. Sandia has experimental test beds of small InifiniBand clusters and workstations to investigate the performance of the MIC architecture. On these experimental test beds the programming models that may be investigated are "offload", "symmetric" and "native". Among these program usage models our primary interest is in the so called "native" mode, because the planned Trinity system to be deployed in 2016 using the next generation MIC processor architecture called Knights Landing would be self-hosted. Trinity / NERSC-8 benchmark programs cover a variety of scientific disciplines and they were used to guide the procurement of these systems. Architectures such as the Intel MIC are well suited to study evolving processor architectures and a usage model commonly referred to as MPI + X that facilitates migration of our applications to use both coarse grain and fine grain parallelism. Our focus with the applications selected is on the efficacy of algorithms in these applications to take advantage of features like: large number of cores, wide vector units, higher-bandwidth and deeper memory sub-system. This is a first step towards understanding applications, algorithms and programming environments for Trinity and future exascale computing systems.

97 MATHEMATICS AND COMPUTING↗

NASA NTRS1998

Performance of a Bounce-Averaged Global Model of Super-Thermal Electron Transport in the Earth's Magnetic Field

In this paper, we report the results of our recent research on the application of a multiprocessor Cray T916 supercomputer in modeling super-thermal electron transport in the earth's magnetic field. In general, this mathematical model requires numerical solution of a system of partial differential equations. The code we use for this model is moderately vectorized. By using Amdahl's Law for vector processors, it can be verified that the code is about 60% vectorized on a Cray computer. Speedup factors on the order of 2.5 were obtained compared to the unvectorized code. In the following sections, we discuss the methodology of improving the code. In addition to our goal of optimizing the code for solution on the Cray computer, we had the goal of scalability in mind. Scalability combines the concepts of portabilty with near-linear speedup. Specifically, a scalable program is one whose performance is portable across many different architectures with differing numbers of processors for many different problem sizes. Though we have access to a Cray at this time, the goal was to also have code which would run well on a variety of architectures.

McGuire, Tim↗

DOE OSTI2015

Clover: Compiler directed lightweight soft error resilience

This paper presents Clover, a compiler directed soft error detection and recovery scheme for lightweight soft error resilience. The compiler carefully generates soft error tolerant code based on idem-potent processing without explicit checkpoint. During program execution, Clover relies on a small number of acoustic wave detectors deployed in the processor to identify soft errors by sensing the wave made by a particle strike. To cope with DUE (detected unrecoverable errors) caused by the sensing latency of error detection, Clover leverages a novel selective instruction duplication technique called tail-DMR (dual modular redundancy). Once a soft error is detected by either the sensor or the tail-DMR, Clover takes care of the error as in the case of exception handling. To recover from the error, Clover simply redirects program control to the beginning of the code region where the error is detected. Lastly, the experiment results demonstrate that the average runtime overhead is only 26%, which is a 75% reduction compared to that of the state-of-the-art soft error resilience technique.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2015

Accelerated application development: The ORNL Titan experience

The use of computational accelerators such as NVIDIA GPUs and Intel Xeon Phi processors is now widespread in the high performance computing community, with many applications delivering impressive performance gains. However, programming these systems for high performance, performance portability and software maintainability has been a challenge. In this paper we discuss experiences porting applications to the Titan system. Titan, which began planning in 2009 and was deployed for general use in 2013, was the first multi-petaflop system based on accelerator hardware. To ready applications for accelerated computing, a preparedness effort was undertaken prior to delivery of Titan. In this paper we report experiences and lessons learned from this process and describe how users are currently making use of computational accelerators on Titan.

97 MATHEMATICS AND COMPUTING↗

NASA NTRS2011

CoNNeCT Baseband Processor Module

A document describes the CoNNeCT Baseband Processor Module (BPM) based on an updated processor, memory technology, and field-programmable gate arrays (FPGAs). The BPM was developed from a requirement to provide sufficient computing power and memory storage to conduct experiments for a Software Defined Radio (SDR) to be implemented. The flight SDR uses the AT697 SPARC processor with on-chip data and instruction cache. The non-volatile memory has been increased from a 20-Mbit EEPROM (electrically erasable programmable read only memory) to a 4-Gbit Flash, managed by the RTAX2000 Housekeeper, allowing more programs and FPGA bit-files to be stored. The volatile memory has been increased from a 20-Mbit SRAM (static random access memory) to a 1.25-Gbit SDRAM (synchronous dynamic random access memory), providing additional memory space for more complex operating systems and programs to be executed on the SPARC. All memory is EDAC (error detection and correction) protected, while the SPARC processor implements fault protection via TMR (triple modular redundancy) architecture. Further capability over prior BPM designs includes the addition of a second FPGA to implement features beyond the resources of a single FPGA. Both FPGAs are implemented with Xilinx Virtex-II and are interconnected by a 96-bit bus to facilitate data exchange. Dedicated 1.25- Gbit SDRAMs are wired to each Xilinx FPGA to accommodate high rate data buffering for SDR applications as well as independent SpaceWire interfaces. The RTAX2000 manages scrub and configuration of each Xilinx.

Yamamoto, Clifford K↗

DOE OSTI2017

A Latency Tolerant Runtime System for Mass Market Computer Systems

Grappa is a latency tolerant runtime system for mass market computer systems comprised of multiple nodes having x86 multicore processors and infiniband interconnect. Grappa is designed to enable in-memory irregular applications written in the C++ programming language to scale up on multiprocessor systems. Grappa addresses the load balance, communication, and synchronization challenges posed by running applications that do not partition evenly across large systems. Two mechanisms are essential to its success: fast task switching and message aggregation. Fast task switching enables processors to tolerate communication and synchronization delays; aggregation sustains high bandwidth on low injection rate networks.

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DOE OSTI2013

A Latency Tolerant Runtime System for Mass Market Computer Systems

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NASA NTRS2015

The NASA Electronic Parts and Packaging (NEPP) Program: Overview and the New Tenets for Cost Conscious Mission Assurance on Electrical, Electronic, and Electromechanical (EEE) Parts

The NEPP Program focuses on the reliability aspects of electronic devices (integrated circuits such as a processor in a computer). There are three principal aspects of this reliability: 1) Lifetime, inherent failure and design issues related to the EEE parts technology and packaging; 2) Effects of space radiation and the space environment on these technologies, and; 3) Creation and maintenance of the assurance support infrastructure required for mission success. The NEPP mission is to provide guidance to NASA for the selection and application of microelectronics technologies, to improve understanding of the risks related to the use of these technologies in the space environment, and to ensure that appropriate EEE parts research is performed to meet NASA mission assurance needs. NEPPs FY15 goals are to represent the NASA voice to the greater aerospace EEE parts community including supporting anti-counterfeit and trust, provide relevant guidance to cost-effective missions, aid insertion of advanced (and commercial) technologies, resolve unexpected parts issues, ensure access to appropriate radiation test facilities, and collaborate as widely as possible with external entities. In accordance with the changing mission profiles throughout NASA, the NEPP Program has developed a balanced portfolio of efforts to provide agency-wide assurance for not only traditional spacecraft developments, but also those in-line with the new philosophies emerging worldwide. In this presentation, we shall present an overview of this program and considerations for EEE parts assurance as applied to cost conscious missions.

space radiation↗

DOE OSTI2013

Massively parallel implementations of coupled-cluster methods for electron spin resonance spectra. I. Isotropic hyperfine coupling tensors in large radicals

Coupled cluster (CC) methods provide highly accurate predictions of molecular properties, but their high computational cost has precluded their routine application to large systems. Fortunately, recent computational developments in the ACES III program by the Bartlett group [the OED/ERD atomic integral package, the super instruction processor, and the super instruction architecture language] permit overcoming that limitation by providing a framework for massively parallel CC implementations. In that scheme, we are further extending those parallel CC efforts to systematically predict the three main electron spin resonance (ESR) tensors (A-, g-, and D-tensors) to be reported in a series of papers. In this paper inaugurating that series, we report our new ACES III parallel capabilities that calculate isotropic hyperfine coupling constants in 38 neutral, cationic, and anionic radicals that include the {sup 11}B, {sup 17}O, {sup 9}Be, {sup 19}F, {sup 1}H, {sup 13}C, {sup 35}Cl, {sup 33}S,{sup 14}N, {sup 31}P, and {sup 67}Zn nuclei. Present parallel calculations are conducted at the Hartree-Fock (HF), second-order many-body perturbation theory [MBPT(2)], CC singles and doubles (CCSD), and CCSD with perturbative triples [CCSD(T)] levels using Roos augmented double- and triple-zeta atomic natural orbitals basis sets. HF results consistently overestimate isotropic hyperfine coupling constants. However, inclusion of electron correlation effects in the simplest way via MBPT(2) provides significant improvements in the predictions, but not without occasional failures. In contrast, CCSD results are consistently in very good agreement with experimental results. Inclusion of perturbative triples to CCSD via CCSD(T) leads to small improvements in the predictions, which might not compensate for the extra computational effort at a non-iterative N{sup 7}-scaling in CCSD(T). The importance of these accurate computations of isotropic hyperfine coupling constants to elucidate experimental ESR spectra, to interpret spin-density distributions, and to characterize and identify radical species is illustrated with our results from large organic radicals. Those include species relevant for organic chemistry, petroleum industry, and biochemistry, such as the cyclo-hexyl, 1-adamatyl, and Zn-porphycene anion radicals, inter alia.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗

DOE OSTI2012

ROSE::FTTransform - A Source-to-Source Translation Framework for Exascale Fault-Tolerance Research

Exascale computing systems will require sufficient resilience to tolerate numerous types of hardware faults while still assuring correct program execution. Such extreme-scale machines are expected to be dominated by processors driven at lower voltages (near the minimum 0.5 volts for current transistors). At these voltage levels, the rate of transient errors increases dramatically due to the sensitivity to transient and geographically localized voltage drops on parts of the processor chip. To achieve power efficiency, these processors are likely to be streamlined and minimal, and thus they cannot be expected to handle transient errors entirely in hardware. Here we present an open, compiler-based framework to automate the armoring of High Performance Computing (HPC) software to protect it from these types of transient processor errors. We develop an open infrastructure to support research work in this area, and we define tools that, in the future, may provide more complete automated and/or semi-automated solutions to support software resiliency on future exascale architectures. Results demonstrate that our approach is feasible, pragmatic in how it can be separated from the software development process, and reasonably efficient (0% to 30% overhead for the Jacobi iteration on common hardware; and 20%, 40%, 26%, and 2% overhead for a randomly selected subset of benchmarks from the Livermore Loops [1]).

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2015

New Platform Provides Innovation

Sky Bridge is the primary unclassified scientific computing platform at Sandia, serving all Mission Areas within the Laboratories. At the formal ribbon cutting in December 2014, Laboratories Director Paul Hommert emphasized the importance of the Institutional Computing Program in providing a critical core Laboratories capability. The deployment of Sky Bridge more than doubled the computing cycles available in Sandia’s restricted computing environment, while incorporating the same underlying architecture as the existing ASC/TLCC2 compute clusters, thus allowing many existing computer codes to run on the system without any major modifications. Sky Bridge immediately addressed the shortfall in projected computing cycles for Sandia’s programs of energy and environment, nuclear weapons life expectancy program (NW LEP), and Applied Laboratory Technology (ALT). From a technological perspective, Sky Bridge is contributing to the readiness of the data center facility and operations personnel for a transition to liquid cooling in future HPC systems and other high-density systems. By comparing the performance and energy costs of Sky Bridge to similar systems (e.g., Dark Bridge) that are air-cooled rather than liquid-cooled, it will also provide valuable data for making return on investment decisions for future purchases. Installation of Sky Bridge enables decommissioning of the Red Sky supercomputer, reduce energy and support costs, and make room for future HPC systems already planned through the ASC and Institutional Computing programs. Sky Bridge’s use of liquid cooling (cold plate to the systems processors) and more efficient power distribution (480 V direct to the rack) saved over $\$$700, 000 in construction costs while reducing annual operating costs by $\$$120,000.

97 MATHEMATICS AND COMPUTING↗

NASA NTRS1973

Integrated Digital Flight Control System for the Space Shuttle Orbiter

The objectives of the integrated digital flight control system (DFCS) is to provide rotational and translational control of the space shuttle orbiter in all phases of flight: from launch ascent through orbit to entry and touchdown, and during powered horizontal flights. The program provides a versatile control system structure while maintaining uniform communications with other programs, sensors, and control effectors by using an executive routine/functional subroutine format. The program reads all external variables at a single point, copies them into its dedicated storage, and then calls the required subroutines in the proper sequence. As a result, the flight control program is largely independent of other programs in the computer complex and is equally insensitive to characteristics of the processor configuration. The integrated structure is described of the control system and the DFCS executive routine which embodies that structure. The input and output, including jet selection are included. Specific estimation and control algorithm are shown for the various mission phases: cruise (including horizontal powered flight), entry, on-orbit, and boost. Attitude maneuver routines that interface with the DFCS are included.

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NASA NTRS1982

A floating-point/multiple-precision processor for airborne applications

A compact input output (I/O) numerical processor capable of performing floating-point, multiple precision and other arithmetic functions at execution times which are at least 100 times faster than comparable software emulation is described. The I/O device is a microcomputer system containing a 16 bit microprocessor, a numerical coprocessor with eight 80 bit registers running at a 5 MHz clock rate, 18K random access memory (RAM) and 16K electrically programmable read only memory (EPROM). The processor acts as an intelligent slave to the host computer and can be programmed in high order languages such as FORTRAN and PL/M-86.

Yee, R.↗

NASA NTRS1981

Data base manipulation for assessment of multiresource suitability and land change

Progress is reported in three tasks which support the overall objectives of renewable resources inventory task of the AgRISTARS program. In the first task, the geometric correction algorithms of the Master Data Processor were investigated to determine the utility of data corrected by this processor for U.S. Forest Service uses. The second task involved investigation of logic to form blobs as a precursor step to automatic change detection involving two dates of LANDSAT data. Some routine procedures for selecting BLOB (spatial averaging) parameters were developed. In the third task, a major effort was made to develop land suitability modeling approches for timber, grazing, and wildlife habitat in support of resource planning efforts on the San Juan National Forest.

Colwell, J.↗

NASA NTRS1983

Measurement of fault latency in a digital avionic mini processor, part 2

The results of fault injection experiments utilizing a gate-level emulation of the central processor unit of the Bendix BDX-930 digital computer are described. Several earlier programs were reprogrammed, expanding the instruction set to capitalize on the full power of the BDX-930 computer. As a final demonstration of fault coverage an extensive, 3-axis, high performance flght control computation was added. The stages in the development of a CPU self-test program emphasizing the relationship between fault coverage, speed, and quantity of instructions were demonstrated.

Mcgough, J.↗