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NASA NTRS2012

Flexible Architecture for FPGAs in Embedded Systems

Commonly, field-programmable gate arrays (FPGAs) being developed in cPCI embedded systems include the bus interface in the FPGA. This complicates the development because the interface is complicated and requires a lot of development time and FPGA resources. In addition, flight qualification requires a substantial amount of time be devoted to just this interface. Another complication of putting the cPCI interface into the FPGA being developed is that configuration information loaded into the device by the cPCI microprocessor is lost when a new bit file is loaded, requiring cumbersome operations to return the system to an operational state. Finally, SRAM-based FPGAs are typically programmed via specialized cables and software, with programming files being loaded either directly into the FPGA, or into PROM devices. This can be cumbersome when doing FPGA development in an embedded environment, and does not have an easy path to flight. Currently, FPGAs used in space applications are usually programmed via multiple space-qualified PROM devices that are physically large and require extra circuitry (typically including a separate one-time programmable FPGA) to enable them to be used for this application. This technology adds a cPCI interface device with a simple, flexible, high-performance backend interface supporting multiple backend FPGAs. It includes a mechanism for programming the FPGAs directly via the microprocessor in the embedded system, eliminating specialized hardware, software, and PROM devices and their associated circuitry. It has a direct path to flight, and no extra hardware and minimal software are required to support reprogramming in flight. The device added is currently a small FPGA, but an advantage of this technology is that the design of the device does not change, regardless of the application in which it is being used. This means that it needs to be qualified for flight only once, and is suitable for one-time programmable devices or an application specific integrated circuit (ASIC). An application programming interface (API) further reduces the development time needed to use the interface device in a system.

Clark, Duane I.↗

NASA NTRS2013

Extraction and Separation Modeling of Orion Test Vehicles with ADAMS Simulation

The Capsule Parachute Assembly System (CPAS) project has increased efforts to demonstrate the performance of fully integrated parachute systems at both higher dynamic pressures and in the presence of wake fields using a Parachute Compartment Drop Test Vehicle (PCDTV) and a Parachute Test Vehicle (PTV), respectively. Modeling the extraction and separation events has proven challenging and an understanding of the physics is required to reduce the risk of separation malfunctions. The need for extraction and separation modeling is critical to a successful CPAS test campaign. Current PTV-alone simulations, such as Decelerator System Simulation (DSS), require accurate initial conditions (ICs) drawn from a separation model. Automatic Dynamic Analysis of Mechanical Systems (ADAMS), a Commercial off the Shelf (COTS) tool, was employed to provide insight into the multi-body six degree of freedom (DOF) interaction between parachute test hardware and external and internal forces. Components of the model include a composite extraction parachute, primary vehicle (PTV or PCDTV), platform cradle, a release mechanism, aircraft ramp, and a programmer parachute with attach points. Independent aerodynamic forces were applied to the mated test vehicle/platform cradle and the separated test vehicle and platform cradle. The aero coefficients were determined from real time lookup tables which were functions of both angle of attack ( ) and sideslip ( ). The atmospheric properties were also determined from a real time lookup table characteristic of the Yuma Proving Grounds (YPG) atmosphere relative to the planned test month. Representative geometries were constructed in ADAMS with measured mass properties generated for each independent vehicle. Derived smart separation parameters were included in ADAMS as sensors with defined pitch and pitch rate criteria used to refine inputs to analogous avionics systems for optimal separation conditions. Key design variables were dispersed in a Monte Carlo analysis to provide the maximum expected range of the state variables at programmer deployment to be used as ICs in DSS. Extensive comparisons were made with Decelerator System Simulation Application (DSSA) to validate the mated portion of the ADAMS extraction trajectory. Results of the comparisons improved the fidelity of ADAMS with a ramp pitch profile update from DSSA. Post-test reconstructions resulted in improvements to extraction parachute drag area knock-down factors, extraction line modeling, and the inclusion of ball-to-socket attachments used as a release mechanism on the PTV. Modeling of two Extraction parachutes was based on United States Air Force (USAF) tow test data and integrated into ADAMS for nominal and Monte Carlo trajectory assessments. Video overlay of ADAMS animations and actual C-12 chase plane test videos supported analysis and observation efforts of extraction and separation events. The COTS ADAMS simulation has been integrated with NASA based simulations to provide complete end to end trajectories with a focus on the extraction, separation, and programmer deployment sequence. The flexibility of modifying ADAMS inputs has proven useful for sensitivity studies and extraction/separation modeling efforts. 1

Fraire, Usbaldo, Jr.↗

NASA NTRS2013

FPGA-Based X-Ray Detection and Measurement for an X-Ray Polarimeter

This technology enables detection and measurement of x-rays in an x-ray polarimeter using a field-programmable gate array (FPGA). The technology was developed for the Gravitational and Extreme Magnetism Small Explorer (GEMS) mission. It performs precision energy and timing measurements, as well as rejection of non-x-ray events. It enables the GEMS polarimeter to detect precisely when an event has taken place so that additional measurements can be made. The technology also enables this function to be performed in an FPGA using limited resources so that mass and power can be minimized while reliability for a space application is maximized and precise real-time operation is achieved. This design requires a low-noise, charge-sensitive preamplifier; a highspeed analog to digital converter (ADC); and an x-ray detector with a cathode terminal. It functions by computing a sum of differences for time-samples whose difference exceeds a programmable threshold. A state machine advances through states as a programmable number of consecutive samples exceeds or fails to exceed this threshold. The pulse height is recorded as the accumulated sum. The track length is also measured based on the time from the start to the end of accumulation. For track lengths longer than a certain length, the algorithm estimates the barycenter of charge deposit by comparing the accumulator value at the midpoint to the final accumulator value. The design also employs a number of techniques for rejecting background events. This innovation enables the function to be performed in space where it can operate autonomously with a rapid response time. This implementation combines advantages of computing system-based approaches with those of pure analog approaches. The result is an implementation that is highly reliable, performs in real-time, rejects background events, and consumes minimal power.

Gregory, Kyle↗

NASA NTRS2005

Characterization and recovery of Deep Sub Micron (DSM) technologies behavior under radiation

This paper serves a twofold purpose: characterize the behavior of a reconfigurable chip exposed to radiation; and demonstrate a method for functionality recovery due to Total Ionizing Dose (TID) effects. The experiments are performed using a PL developed reconfigurable device, a Field Programmable Transistor Array (FPTA). The paper initially describes experiments on the characterization of the NMOS transistor behavior for TID values up to 300krad. The behavior of analog and digital circuits downloaded onto the FPTA chip is also assessed for TID effects. This paper also presents a novel approach for circuit functionality recovery due to radiation effects based on Evolvable Hardware. The key idea is to reconfigure a programmable device, in-situ, to compensate, or bypass its degraded or damaged components. Experiments with total radiation dose up to 300kRad show that while the functionality of a variety of circuits, including digital gates, a rectifier and a Digital to Analog Converter implemented on a FPTA-2 chip is degraded/lost at levels before 200kRad, the correct functionality can be recovered through the proposed evolutionary approach and the chips are able to survive higher radiation, for several functions in excess of total radiation dose of 250kRad.

evolvable hardware↗

NASA NTRS1972

Interactive graphics system for IBM 1800 computer

A FORTRAN compatible software system that has been developed to provide an interactive graphics capability for the IBM 1800 computer is described. The interactive graphics hardware consists of a Hewlett-Packard 1300A cathode ray tube, Sanders photopen, digital to analog converters, pulse counter, and necessary interface. The hardware is available from IBM as several related RPQ's. The software developed permits the application programmer to use IBM 1800 FORTRAN to develop a display on the cathode ray tube which consists of one or more independent units called pictures. The software permits a great deal of flexibility in the manipulation of these pictures and allows the programmer to use the photopen to interact with the displayed data and make decisions based on information returned by the photopen.

Carleton, T. P.↗

NASA NTRS1970

Syntax-directed documentation for PL360

PL360 is a phrase-structured programming language which provides the facilities of a symbolic machine language for the IBM 360 computers. An automatic process, syntax-directed documentation, is described which acquires programming documentation through the syntactical analysis of a program, followed by the interrogation of the originating programmer. This documentation can be dispensed through reports of file query replies when other programmers later need to know the program structure and its details. A key principle of the programming documentation process is that it is managed solely on the basis of the syntax of programs.

Mills, H. D.↗

NASA NTRS1973

Software approach to automatic patching of analog computer

The Automatic Patching Verification program (APV) is described which provides the hybrid computer programmer with a convenient method of performing a static check of the analog portion of his study. The static check insures that the program is patched as specified, and that the computing components being used are operating correctly. The APV language the programmer uses to specify his conditions and interconnections is similar to the FORTRAN language in syntax. The APV control program reads APV source program statements from an assigned input device. Each source program statement is processed immediately after it is read. A statement may select an analog console, set an analog mode, set a potentiometer or DAC, or read from the analog console and perform a test. Statements are read and processed sequentially. If an error condition is detected, an output occurs on an assigned output device. When an end statement is read, the test is terminated.

Source record↗

NASA NTRS1975

Evaluation of several navigation algorithms for application to general aviation

Using data obtained in flight, three position determining algorithms for use by general aviation aircraft were evaluated representing increasing software requirements. These were a DME only, DME/air data and blended DME/air data. Although each step represented additional software with resultant increase in position accuracy, all could be performed on a programmable electronic desk calculator. Results from the computation of aircraft position using the three algorithms are presented. The algorithms employed can be extended to accept VOR, TACAN bearing, ADF, or other NAVAID Data. To obtain the flight data an experimental system was configured and flown on a general aviation aircraft. Principal hardware elements (all with low-cost potential) were a programmable calculator, a single DME receiver (multiplexed for multiple DME use) and a low-cost air speed sensor (shed-vortex principle). The flight test demonstrated satisfactory performance of these principal elements.

Conrad, B.↗

NASA NTRS1976

Hardware additions to microprocessor architecture aid software development

An address trap (breakpoint) mechanism and last-in-first-out (LIFO) address stack are suggested as two additions to the basic microprocessor architecture whose functions are solely to aid the programmer. These devices provide the programmer with the ability to specify address breakpoints and to trace program execution back through N instructions, where N is the depth of the stack. Both devices, plus interface logic and buffering, have been designed for an INTEL 8080-based system using approximately 25 integrated-circuit packages.

Sievers, M. W.↗

NASA NTRS1977

Ergometer

The bicycle ergometer was designed for use in experiments M171 and M093 and for use in optional exercise by the crewmen. The ergometer allows a crewman to exercise in zero-gravity using either his hands or his feet. It provides a precisely calibrated and, if needed, a programmable standard of work rate for the crewman. The ergometer operates in any of three selectable modes. The set heart rate mode varies the ergometer work rate, as necessary, to achieve and maintain a preselected heart rate. The sequenced heart rate mode is similar to the set heart rate mode except that the heart rate is programmable through five preset levels with a period of time for each level. The set work rate mode delivers a preset work load to the subject.

Lem, J. D.↗

NASA NTRS1978

A cycle timer for testing electric vehicles

A cycle timer was developed to assist the driver of an electric vehicle in more accurately following and repeating SAE driving schedules. These schedules require operating an electric vehicle in a selected stop-and-go driving cycle and repeating this cycle pattern until the vehicle ceases to meet the requirements of the cycle. The heart of the system is a programmable read-only memory (PROM) that has the required test profiles permanently recorded on plug-in cards, one card for each different driving schedule. The PROM generates a direct current analog signal that drives a speedometer displayed on one scale of a dual movement meter. The second scale of the dual movement meter displays the actual speed of the vehicle as recorded by the fifth wheel. The vehicle operator controls vehicle speed to match the desired profile speed. The PROM controls the recycle start time as well as the buzzer activation. The cycle programmer is powered by the test vehicle's 12-volt accessory battery, through a 5-volt regulator and a 12-volt dc-to-dc converter.

Soltis, R. F.↗

NASA NTRS1978

Operational manual for two-dimensional transonic code TSFOIL

This code solves the two-dimensional, transonic, small-disturbance equations for flow past lifting airfoils in both free air and various wind-tunnel environments by using a variant of the finite-difference method. A description of the theoretical and numerical basis of the code is provided, together with complete operating instructions and sample cases for the general user. In addition, a programmer's manual is also presented to assist the user interested in modifying the code. Included in the programmer's manual are a dictionary of subroutine variables in common and a detailed description of each subroutine.

Stahara, S. S.↗

NASA NTRS1978

Improvements of the gravity field from satellite techniques as proposed to the European Space Agency

A summary of the European Earth Sciences Space Programme and the requirements for each gravity field mapping resulting from this programme are given. Three satellite experiments for gravity field improvement proposed to the European Space Agency in the last years are shortly characterized. One of these experiments, the low-low-SST-SLALOM experiment, based on laser interferometry for a "two target-one Spacelab telescope" configuration, is discussed in more detail. Reasons for the low-low concept selection are given and some mission aspects and a possible system concept for a compact ranging, acquisition and tracking system are presented.

Reigber, C.↗

NASA NTRS1978

Advanced systems requirements for ocean observations via microwave radiometers

A future microwave spectroradiometer operating in several frequency bands will have the capability to step or sweep frequencies on an adaptable or programmable basis. The on-board adaptable frequency shifting can make the systems immune from radio interference. Programmable frequency sweeping with on-board data inversion by high speed computers would provide for instantaneous synoptic measurements or sea surface temperature and salinity, water surface and volume pollution, ice thickness, ocean surface winds, snow depth, and soil moisture. Large structure satellites will allow an order of magnitude improvement in the present radiometric measurement spacial resolution.

Blume, H.-J. C.↗

NASA NTRS1979

Microcomputer programming skills

Some differences in skill and techniques required for conversion from programmer to microprogrammer are discussed. The primary things with which the programmer should work are hardware architecture, hardware/software trade off, and interfacing. The biggest differences, however, will stem from the differences in applications than from differences in machine size. The change to real-time programming is the most important of these differences, particularly on dedicated microprocessors. Another primary change is programming with a more computer-naive user in mind, and dealing with his limitations and expectations.

Barth, C. W.↗

NASA NTRS1980

Process development for automated solar cell and module production. Task 4: Automated array assembly

A process sequence which can be used in conjunction with automated equipment for the mass production of solar cell modules for terrestrial use was developed. The process sequence was then critically analyzed from a technical and economic standpoint to determine the technological readiness of certain process steps for implementation. The steps receiving analysis were: back contact metallization, automated cell array layup/interconnect, and module edge sealing. For automated layup/interconnect, both hard automation and programmable automation (using an industrial robot) were studied. The programmable automation system was then selected for actual hardware development.

Source record↗

NASA NTRS1981

Controller for computer control of brushless dc motors

A motor speed and torque controller for brushless d.c. motors provides an unusually smooth torque control arrangement. The controller provides a means for controlling a current waveform in each winding of a brushless dc motor by synchronization of an excitation pulse train from a programmable oscillator. Sensing of torque for synchronization is provided by a light beam chopper mounted on the motor rotor shaft. Speed and duty cycle are independently controlled by controlling the frequency and pulse width output of the programmable oscillator. A means is also provided so that current transitions from one motor winding to another is effected without abrupt changes in output torque.

Hieda, L. S.↗

NASA NTRS1980

Universal delta modulation receivers using the bit slice approach

The architecture of programmable processors is described, with particular reference to the design of a programmable delta-modulation decoder capable of receiving DM encoders employing different schemes. A switching receiver implementation, allowing communication between different DM algorithms, is designed and shown.

Apelewicz, T.↗