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At least 559 records · Page 31

A High-Throughput Processor for Flight Control Research Using Small UAVs

There are numerous autopilot systems that are commercially available for small (<100 lbs) UAVs. However, they all share several key disadvantages for conducting aerodynamic research, chief amongst which is the fact that most utilize older, slower, 8- or 16-bit microcontroller technologies. This paper describes the development and testing of a flight control system (FCS) for small UAV s based on a modern, high throughput, embedded processor. In addition, this FCS platform contains user-configurable hardware resources in the form of a Field Programmable Gate Array (FPGA) that can be used to implement custom, application-specific hardware. This hardware can be used to off-load routine tasks such as sensor data collection, from the FCS processor thereby further increasing the computational throughput of the system.

Klenke, Robert H.↗

Application-Controlled Parallel Asynchronous Input/Output Utility

A software utility tool has been designed to alleviate file system I/O performance bottlenecks to which many high-end computing (HEC) applications fall prey because of the relatively large volume of data generated for a given amount of computational work. In an effort to reduce computing resource waste, and to improve sustained performance of these HEC applications, a lightweight software utility has been designed to circumvent bandwidth limitations of typical HEC file systems by exploiting the faster inter-processor bandwidth to move output data from compute nodes to designated I/O nodes as quickly as possible, thereby minimizing the I/O wait time. This utility has successfully demonstrated a significant performance improvement within a major NASA weather application.

Clune, Thomas↗

Applications of satellite data relay to problems of field seismology

A seismic signal processor was developed and tested for use with the NOAA-GOES satellite data collection system. Performance tests on recorded, as well as real time, short period signals indicate that the event recognition technique used is nearly perfect in its rejection of cultural signals and that data can be acquired in many swarm situations with the use of solid state buffer memories. Detailed circuit diagrams are provided. The design of a complete field data collection platform is discussed and the employment of data collection platforms in seismic network is reviewed.

Webster, W. J., Jr.↗

Free-Space Optical Interconnect Employing VCSEL Diodes

Sensor signal processing is widely used on aircraft and spacecraft. The scheme employs multiple input/output nodes for data acquisition and CPU (central processing unit) nodes for data processing. To connect 110 nodes and CPU nodes, scalable interconnections such as backplanes are desired because the number of nodes depends on requirements of each mission. An optical backplane consisting of vertical-cavity surface-emitting lasers (VCSELs), VCSEL drivers, photodetectors, and transimpedance amplifiers is the preferred approach since it can handle several hundred megabits per second data throughput.The next generation of satellite-borne systems will require transceivers and processors that can handle several Gb/s of data. Optical interconnects have been praised for both their speed and functionality with hopes that light can relieve the electrical bottleneck predicted for the near future. Optoelectronic interconnects provide a factor of ten improvement over electrical interconnects.

Simons, Rainee N.↗

The image-processing system for the Earth Resources Technology Satellite.

Description of the image-processing system for the Earth Resources Technology Satellite (ERTS), which will process video-tape recordings received from the satellite into imagery and digitized video data suitable for earth-resource study and analysis. The system is made up of three subsystems. The bulk processor produces 70-mm images and digitized records, corrected for systematic geometric and radiometric errors as well as for sensor-calibration and other errors. The precision processor modifies the bulk images to significantly increase geometric precision. The special processor transfers either bulk or precision data to computer-compatible tape.

Johnson, R. H.↗

Three-dimensional radiative transfer on a massively parallel computer

We perform 3D radiative transfer calculations in non-local thermodynamic equilibrium (NLTE) in the simple two-level atom approximation on the Mas-Par MP-1, which contains 8192 processors and is a single instruction multiple data (SIMD) machine, an example of the new generation of massively parallel computers. On such a machine, all processors execute the same command at a given time, but on different data. To make radiative transfer calculations efficient, we must re-consider the numerical methods and storage of data. To solve the transfer equation, we adopt the short characteristic method and examine different acceleration methods to obtain the source function. We use the ALI method and test local and non-local operators. Furthermore, we compare the Ng and the orthomin methods of acceleration. We also investigate the use of multi-grid methods to get fast solutions for the NLTE case. In order to test these numerical methods, we apply them to two problems with and without periodic boundary conditions.

Vath, H. M.↗

Investigation into Cloud Computing for More Robust Automated Bulk Image Geoprocessing

Geospatial resource assessments frequently require timely geospatial data processing that involves large multivariate remote sensing data sets. In particular, for disasters, response requires rapid access to large data volumes, substantial storage space and high performance processing capability. The processing and distribution of this data into usable information products requires a processing pipeline that can efficiently manage the required storage, computing utilities, and data handling requirements. In recent years, with the availability of cloud computing technology, cloud processing platforms have made available a powerful new computing infrastructure resource that can meet this need. To assess the utility of this resource, this project investigates cloud computing platforms for bulk, automated geoprocessing capabilities with respect to data handling and application development requirements. This presentation is of work being conducted by Applied Sciences Program Office at NASA-Stennis Space Center. A prototypical set of image manipulation and transformation processes that incorporate sample Unmanned Airborne System data were developed to create value-added products and tested for implementation on the "cloud". This project outlines the steps involved in creating and testing of open source software developed process code on a local prototype platform, and then transitioning this code with associated environment requirements into an analogous, but memory and processor enhanced cloud platform. A data processing cloud was used to store both standard digital camera panchromatic and multi-band image data, which were subsequently subjected to standard image processing functions such as NDVI (Normalized Difference Vegetation Index), NDMI (Normalized Difference Moisture Index), band stacking, reprojection, and other similar type data processes. Cloud infrastructure service providers were evaluated by taking these locally tested processing functions, and then applying them to a given cloud-enabled infrastructure to assesses and compare environment setup options and enabled technologies. This project reviews findings that were observed when cloud platforms were evaluated for bulk geoprocessing capabilities based on data handling and application development requirements.

Brown, Richard B.↗

A fast, programmable hardware architecture for the processing of spaceborne SAR data

The development of high-throughput SAR processors (HTSPs) for the spaceborne SARs being planned by NASA, ESA, DFVLR, NASDA, and the Canadian Radarsat Project is discussed. The basic parameters and data-processing requirements of the SARs are listed in tables, and the principal problems are identified as real-operations rates in excess of 2 x 10 to the 9th/sec, I/O rates in excess of 8 x 10 to the 6th samples/sec, and control computation loads (as for range cell migration correction) as high as 1.4 x 10 to the 6th instructions/sec. A number of possible HTSP architectures are reviewed; host/array-processor (H/AP) and distributed-control/data-path (DCDP) architectures are examined in detail and illustrated with block diagrams; and a cost/speed comparison of these two architectures is presented. The H/AP approach is found to be adequate and economical for speeds below 1/200 of real time, while DCDP is more cost-effective above 1/50 of real time.

Bennett, J. R.↗

Acquisition and use of Orlando, Florida and Continental Airbus radar flight test data

Westinghouse is developing a lookdown pulse Doppler radar for production as the sensor and processor of a forward looking hazardous windshear detection and avoidance system. A data collection prototype of that product was ready for flight testing in Orlando to encounter low level windshear in corroboration with the FAA-Terminal Doppler Weather Radar (TDWR). Airborne real-time processing and display of the hazard factor were demonstrated with TDWR facilitated intercepts and penetrations of over 80 microbursts in a three day period, including microbursts with hazard factors in excess of .16 (with 500 ft. PIREP altitude loss) and the hazard factor display at 6 n.mi. of a visually transparent ('dry') microburst with TDWR corroborated outflow reflectivities of +5 dBz. Range gated Doppler spectrum data was recorded for subsequent development and refinement of hazard factor detection and urban clutter rejection algorithms. Following Orlando, the data collection radar was supplemental type certified for in revenue service on a Continental Airlines Airbus in an automatic and non-interferring basis with its ARINC 708 radar to allow Westinghouse to confirm its understanding of commercial aircraft installation, interface realities, and urban airport clutter. A number of software upgrades, all of which were verified at the Receiver-Transmitter-Processor (RTP) hardware bench with Orlando microburst data to produce desired advanced warning hazard factor detection, included some preliminary loads with automatic (sliding window average hazard factor) detection and annunciation recording. The current (14-APR-92) configured software is free from false and/or nuisance alerts (CAUTIONS, WARNINGS, etc.) for all take-off and landing approaches, under 2500 ft. altitude to weight-on-wheels, into all encountered airports, including Newark (NJ), LAX, Denver, Houston, Cleveland, etc. Using the Orlando data collected on hazardous microbursts, Westinghouse has developed a lookdown pulse Doppler radar product with signal and data processing algorithms which detect realistic microburst hazards and has demonstrated those algorithms produce no false alerts (or nuisance alerts) in urban airport ground moving vehicle (GMTI) and/or clutter environments.

Eide, Michael C.↗

Database for LDV signal processor performance analysis

A technique for the direct comparison of LDV signal processors is developed, based on the use of a data base of digitized signal bursts obtained from an LDV under various configurations. This data base can be used to evaluate the response of signal processors and processor algorithms to specific signal characteristics and not to generalized simplistic waveforms. Examples from such a data base are presented to illustrate the capabilities of the proposed method. This data base includes signal ensembles obtained with three laser power settings at two transmitted focal lengths.

Baker, Glenn D.↗

Computer simulation of a space SAR using a range-sequential processor for soil moisture mapping

The ability of a spaceborne synthetic aperture radar (SAR) to detect soil moisture was evaluated by means of a computer simulation technique. The computer simulation package includes coherent processing of the SAR data using a range-sequential processor, which can be set up through hardware implementations, thereby reducing the amount of telemetry involved. With such a processing approach, it is possible to monitor the earth's surface on a continuous basis, since data storage requirements can be easily met through the use of currently available technology. The Development of the simulation package is described, followed by an examination of the application of the technique to actual environments. The results indicate that in estimating soil moisture content with a four-look processor, the difference between the assumed and estimated values of soil moisture is within + or - 20% of field capacity for 62% of the pixels for agricultural terrain and for 53% of the pixels for hilly terrain. The estimation accuracy for soil moisture may be improved by reducing the effect of fading through non-coherent averaging.

Fujita, M.↗

Real-time computer data system for the 40- by 80-foot wind tunnel facility at Ames Research Center

The background material and operational concepts of a computer-based system for an operating wind tunnel are described. An on-line real-time computer system was installed in a wind tunnel facility to gather static and dynamic data. The computer system monitored aerodynamic forces and moments of periodic and quasi-periodic functions, and displayed and plotted computed results in real time. The total system is comprised of several off-the-shelf, interconnected subsystems that are linked to a large data processing center. The system includes a central processor unit with 32,000 24-bit words of core memory, a number of standard peripherals, and several special processors; namely, a dynamic analysis subsystem, a 256-channel PCM-data subsystem and ground station, a 60-channel high-speed data acquisition subsystem, a communication link, and static force and pressure subsystems. The role of the test engineer as a vital link in the system is also described.

Cambra, J. M.↗

Application of microprocessors to spacecraft synthetic aperture radar processing

A ground-based digital synthetic aperture radar (SAR) processor capable of correlating images from raw spacecraft data at real-time rates is currently under development. The processor design requirements are particularly formidable due to (1) range migration effects resulting from planetary curvature and rotation, (2) antenna beam pointing errors, and (3) variation of the Doppler reference function with changing orbital parameters. Based upon the current effort, this paper describes a candidate real-time on-board SAR processing implementation approach that might evolve for future spacecraft applications. Key features include the use of custom large scale integration (LSI) charge-coupled device (CCD) technology to accomplish the correlation functions and microprocessor technology to effect control.

Arens, W. E.↗

Optimality Of Variable-Length Codes

Report presents analysis of performances of conceptual Rice universal noiseless coders designed to provide efficient compression of data over wide range of source-data entropies. Includes predictive preprocessor that maps source data into sequence of nonnegative integers and variable-length-coding processor, which adapts to varying entropy of source data by selecting whichever one of number of optional codes yields shortest codeword.

Yeh, Pen-Shu↗

Advanced End-to-end Simulation for On-board Processing (AESOP)

Developers of data compression algorithms typically use their own software together with commercial packages to implement, evaluate and demonstrate their work. While convenient for an individual developer, this approach makes it difficult to build on or use another's work without intimate knowledge of each component. When several people or groups work on different parts of the same problem, the larger view can be lost. What's needed is a simple piece of software to stand in the gap and link together the efforts of different people, enabling them to build on each other's work, and providing a base for engineers and scientists to evaluate the parts as a cohesive whole and make design decisions. AESOP (Advanced End-to-end Simulation for On-board Processing) attempts to meet this need by providing a graphical interface to a developer-selected set of algorithms, interfacing with compiled code and standalone programs, as well as procedures written in the IDL and PV-Wave command languages. As a proof of concept, AESOP is outfitted with several data compression algorithms integrating previous work on different processors (AT&T DSP32C, TI TMS320C30, SPARC). The user can specify at run-time the processor on which individual parts of the compression should run. Compressed data is then fed through simulated transmission and uncompression to evaluate the effects of compression parameters, noise and error correction algorithms. The following sections describe AESOP in detail. Section 2 describes fundamental goals for usability. Section 3 describes the implementation. Sections 4 through 5 describe how to add new functionality to the system and present the existing data compression algorithms. Sections 6 and 7 discuss portability and future work.

Mazer, Alan S.↗

Adoption of Test Driven Development and Continuous Integration for the Development of the Trick Simulation Toolkit

This paper describes the adoption of a Test Driven Development approach and a Continuous Integration System in the development of the Trick Simulation Toolkit, a generic simulation development environment for creating high fidelity training and engineering simulations at the NASA/Johnson Space Center and many other NASA facilities. It describes what was learned and the significant benefits seen, such as fast, thorough, and clear test feedback every time code is checked-in to the code repository. It also describes a system that encourages development of code that is much more flexible, maintainable, and reliable. The Trick Simulation Toolkit development environment provides a common architecture for user-defined simulations. Trick builds executable simulations using user-supplied simulation-definition files (S_define) and user supplied "model code". For each Trick-based simulation, Trick automatically provides job scheduling, checkpoint / restore, data-recording, interactive variable manipulation (variable server), and an input-processor. Also included are tools for plotting recorded data and various other supporting tools and libraries. Trick is written in C/C++ and Java and supports both Linux and MacOSX. Prior to adopting this new development approach, Trick testing consisted primarily of running a few large simulations, with the hope that their complexity and scale would exercise most of Trick's code and expose any recently introduced bugs. Unsurprising, this approach yielded inconsistent results. It was obvious that a more systematic, thorough approach was required. After seeing examples of some Java-based projects that used the JUnit test framework, similar test frameworks for C and C++ were sought. Several were found, all clearly inspired by JUnit. Googletest, a freely available Open source testing framework, was selected as the most appropriate and capable. The new approach was implemented while rewriting the Trick memory management component, to eliminate a fundamental design flaw. The benefits became obvious almost immediately, not just in the correctness of the individual functions and classes but also in the correctness and flexibility being added to the overall design. Creating code to be testable, and testing as it was created resulted not only in better working code, but also in better-organized, flexible, and readable (i.e., articulate) code. This was, in essence the Test-driven development (TDD) methodology created by Kent Beck. Seeing the benefits of Test Driven Development, other Trick components were refactored to make them more testable and tests were designed and implemented for them.

Penn, John M.↗

CoNNeCT Baseband Processor Module

A document describes the CoNNeCT Baseband Processor Module (BPM) based on an updated processor, memory technology, and field-programmable gate arrays (FPGAs). The BPM was developed from a requirement to provide sufficient computing power and memory storage to conduct experiments for a Software Defined Radio (SDR) to be implemented. The flight SDR uses the AT697 SPARC processor with on-chip data and instruction cache. The non-volatile memory has been increased from a 20-Mbit EEPROM (electrically erasable programmable read only memory) to a 4-Gbit Flash, managed by the RTAX2000 Housekeeper, allowing more programs and FPGA bit-files to be stored. The volatile memory has been increased from a 20-Mbit SRAM (static random access memory) to a 1.25-Gbit SDRAM (synchronous dynamic random access memory), providing additional memory space for more complex operating systems and programs to be executed on the SPARC. All memory is EDAC (error detection and correction) protected, while the SPARC processor implements fault protection via TMR (triple modular redundancy) architecture. Further capability over prior BPM designs includes the addition of a second FPGA to implement features beyond the resources of a single FPGA. Both FPGAs are implemented with Xilinx Virtex-II and are interconnected by a 96-bit bus to facilitate data exchange. Dedicated 1.25- Gbit SDRAMs are wired to each Xilinx FPGA to accommodate high rate data buffering for SDR applications as well as independent SpaceWire interfaces. The RTAX2000 manages scrub and configuration of each Xilinx.

Yamamoto, Clifford K↗