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At least 559 records · Page 31

RTMPL: A structured programming and documentation utility for real-time multiprocessor simulations

The NASA Lewis Research Center is developing and evaluating experimental hardware and software systems to help meet future needs for real time simulations of air-breathing propulsion systems. The Real Time Multiprocessor Simulator (RTMPS) project is aimed at developing a prototype simulator system that uses multiple microprocessors to achieve the desired computing speed and accuracy at relatively low cost. Software utilities are being developed to provide engineering-level programming and interactive operation of the simulator. Two major software development efforts were undertaken in the RTMPS project. A real time multiprocessor operating system was developed to provide for interactive operation of the simulator. The second effort was aimed at developing a structured, high-level, engineering-oriented programming language and translator that would facilitate the programming of the simulator. The Real Time Multiprocessor Programming Language (RTMPL) allows the user to describe simulation tasks for each processor in a straight-forward, structured manner. The RTMPL utility acts as an assembly language programmer, translating the high-level simulation description into time-efficient assembly language code for the processors. The utility sets up all of the interfaces between the simulator hardware, firmware, and operating system.

Arpasi, D. J.↗

Supercomputing on massively parallel bit-serial architectures

Research on the Goodyear Massively Parallel Processor (MPP) suggests that high-level parallel languages are practical and can be designed with powerful new semantics that allow algorithms to be efficiently mapped to the real machines. For the MPP these semantics include parallel/associative array selection for both dense and sparse matrices, variable precision arithmetic to trade accuracy for speed, micro-pipelined train broadcast, and conditional branching at the processing element (PE) control unit level. The preliminary design of a FORTRAN-like parallel language for the MPP has been completed and is being used to write programs to perform sparse matrix array selection, min/max search, matrix multiplication, Gaussian elimination on single bit arrays and other generic algorithms. A description is given of the MPP design. Features of the system and its operation are illustrated in the form of charts and diagrams.

Iobst, Ken↗

Reducing space overhead for independendent checkpointing

The main disadvantages of independent checkpointing are the possible domino effect and the associated storage space overhead for maintaining multiple checkpoints. In most previous work, it has been assumed that only the checkpoints older than the current global recovery line can be discarded. Here, we generalize a notion of recovery line to potential recovery line. Only the checkpoints belonging to at least one of the potential recovery lines cannot be discarded. By using the model of maximum-sized antichains on a partially ordered set, an efficient algorithm is developed for finding all non-discardable checkpoints, and we show that the number of non-discardable checkpoints cannot exceed N(N+1)/2, where N is the number of processors. Communication trace driven simulation for several hypercube programs is performed to show the benefit of the proposed algorithm for real applications.

Wang, Yi-Min↗

Servomotor and Controller Having Large Dynamic Range

A recently developed micro-commanding rotational-position-control system offers advantages of less mechanical complexity, less susceptibility to mechanical resonances, less power demand, less bulk, less weight, and lower cost, relative to prior rotational-position-control systems based on stepping motors and gear drives. This system includes a digital-signal- processor (DSP)-based electronic controller, plus a shaft-angle resolver and a servomotor mounted on the same shaft. Heretofore, micro-stepping has usually been associated with stepping motors, but in this system, the servomotor is micro-commanded in response to rotational-position feedback from the shaft-angle resolver. The shaft-angle resolver is of a four-speed type chosen because it affords four times the resolution of a single-speed resolver. A key innovative aspect of this system is its position-feedback signal- conditioning circuits, which condition the resolver output signal for multiple ranges of rotational speed. In the preferred version of the system, two rotational- speed ranges are included, but any number of ranges could be added to expand the speed range or increase resolution in particular ranges. In the preferred version, the resolver output is conditioned with two resolver-to-digital converters (RDCs). One RDC is used for speeds from 0.00012 to 2.5 rpm; the other RDC is used for speeds of 2.5 to 6,000 rpm. For the lower speed range, the number of discrete steps of RDC output per revolution was set at 262,144 (4 quadrants at 16 bits per quadrant). For the higher speed range, the number of discrete steps per revolution was set at 4,096 (4 quadrants at 10 bits per quadrant).

Alhorn, Dean C.↗

A Multi-Mission Space Avionics Architecture

As the budget for the space industry is dwindling, a reusable avionics architecture applicable across multiple missions is urgently needed to reduce the development and production costs of flight projects. This paper presents a multi-mission avionics architecture which employs interface standards extensively, sot hat avionics systems can be built rapidly by assembling subsystems and instruments in a plug-and-play manner. The key feature of this architecture is a "backbone" standard parallel bus which can accommodate various standard interfaces through a repertoire of I/O modules. Hence, specific ;mission requirements can be met by selecting and integrating the appropriate subsystems and instruments into the system. This architecture can also adopt different "backbone" buses, implement redundant processors, and support distributed processing. An example of the architecture using the MOPS6000 from the Southwest Research Institute is also described. Experiments will be done in the Flight System Testbed (FST) of the Jet Propulsion Laboratory to benchmark the MOPS6000 and to demonstrate its multi-mission capability.

Avionics↗

Parallel Processing of Broad-Band PPM Signals

A parallel-processing algorithm and a hardware architecture to implement the algorithm have been devised for timeslot synchronization in the reception of pulse-position-modulated (PPM) optical or radio signals. As in the cases of some prior algorithms and architectures for parallel, discrete-time, digital processing of signals other than PPM, an incoming broadband signal is divided into multiple parallel narrower-band signals by means of sub-sampling and filtering. The number of parallel streams is chosen so that the frequency content of the narrower-band signals is low enough to enable processing by relatively-low speed complementary metal oxide semiconductor (CMOS) electronic circuitry. The algorithm and architecture are intended to satisfy requirements for time-varying time-slot synchronization and post-detection filtering, with correction of timing errors independent of estimation of timing errors. They are also intended to afford flexibility for dynamic reconfiguration and upgrading. The architecture is implemented in a reconfigurable CMOS processor in the form of a field-programmable gate array. The algorithm and its hardware implementation incorporate three separate time-varying filter banks for three distinct functions: correction of sub-sample timing errors, post-detection filtering, and post-detection estimation of timing errors. The design of the filter bank for correction of timing errors, the method of estimating timing errors, and the design of a feedback-loop filter are governed by a host of parameters, the most critical one, with regard to processing very broadband signals with CMOS hardware, being the number of parallel streams (equivalently, the rate-reduction parameter).

Gray, Andrew↗

A Tool for Automatic Data Distribution for CFD Applications on Structured Grids

Development of HPF versions of NPB and ARC3D has shown that HPF provides an efficient, concise way to express parallelism and to organize data traffic. The use of HPF, as noted in the papers, requires an intimate knowledge of the applications and a detailed analysis of data affinity, data movement, and data granularity. To simplify and accelerate the task of developing HPF versions of existing CFD applications we have designed and implemented ADAPT (Automatic Data Alignment and Placement Tool). ADAPT analyzes a CFD application working on a single structured grid and generates HPF TEMPLATE, (RE)DISTRIBUTION, ALIGNMENT, and INDEPENDENT directives. The directives can be generated on the nest level, subroutine level, application level, or on the application interface level. ADAPT annotates an existing CFD FORTRAN application, performing computations on single or multiple grids. On each grid the application is considered as a sequence of operators, each applied to a set of variables defined in a particular grid domain. ADAPT automatically detects implicit operators (i.e., having data dependences) and explicit operators (without data dependences). For parallelization of an explicit operator ADAPT creates a template for the operator domain, aligns arrays used in the operator with the template, distributes the template, and declares the loops over the distributed dimensions as INDEPENDENT. For parallelization of an implicit operator, the distribution of the operator's domain should be consistent with the operator's dependences. Any dependence between sections distributed on different processors would preclude parallelization if the compiler does not have an ability to pipeline computations. If a data distribution is "orthogonal" to the dependences of an implicit operator, then the loop which implements the operator can be declared as INDEPENDENT. ADAPT starts with an analysis of array index expressions of the loop nests. For each pair of arrays referenced in an assignment statement, it generates an arc in the alignment graph and annotates it with an affinity relation. The template, alignment, and distribution directives for a particular loop nest are then derived from a transitive closure of the affinity relation. A compromise of data distributions in different nests and subroutines is achieved by merging annotated alignment graphs for adjacent nests/stibroutine calls in the nest/call graph of the application in the process called distribution lifting. ADAPT has been implemented as a C++ program running in conjunction with a parallelization tool called CAPTools. ADAPT uses the parse tree, interprocedural analysis and application database generated by CAPTools. It also uses the Directed Graph class, initially implemented in p2d2 (parallel debugger oi distributed programs), and some other classes supporting symbolic computations. ADAPT uses data distribution techniques described. ADAPT was tested with ARC3D and the FT benchmark and has demonstrated a code performance within a factor of 1.5 of handwritten versions.

Frumkin, Michael↗

Application handbook for a Standardized Control Module (SCM) for DC-DC converters, volume 1

The standardized control module (SCM) was developed for application in the buck, boost and buck/boost DC-DC converters. The SCM used multiple feedback loops to provide improved input line and output load regulation, stable feedback control system, good dynamic transient response and adaptive compensation of the control loop for changes in open loop gain and output filter time constraints. The necessary modeling and analysis tools to aid the design engineer in the application of the SCM to DC-DC Converters were developed. The SCM functional block diagram and the different analysis techniques were examined. The average time domain analysis technique was chosen as the basic analytical tool. The power stage transfer functions were developed for the buck, boost and buck/boost converters. The analog signal and digital signal processor transfer functions were developed for the three DC-DC Converter types using the constant on time, constant off time and constant frequency control laws.

Lee, F. C.↗

Computational Issues in Damping Identification for Large Scale Problems

Two damping identification methods are tested for efficiency in large-scale applications. One is an iterative routine, and the other a least squares method. Numerical simulations have been performed on multiple degree-of-freedom models to test the effectiveness of the algorithm and the usefulness of parallel computation for the problems. High Performance Fortran is used to parallelize the algorithm. Tests were performed using the IBM-SP2 at NASA Ames Research Center. The least squares method tested incurs high communication costs, which reduces the benefit of high performance computing. This method's memory requirement grows at a very rapid rate meaning that larger problems can quickly exceed available computer memory. The iterative method's memory requirement grows at a much slower pace and is able to handle problems with 500+ degrees of freedom on a single processor. This method benefits from parallelization, and significant speedup can he seen for problems of 100+ degrees-of-freedom.

Pilkey, Deborah L.↗

Synthetic-aperture-radar imaging of the ocean surface using the slightly-rough facet model and a full surface-wave spectrum

A new model of synthetic-aperture-radar (SAR) imaging of ocean waves is described. The model is based on mapping individual, slightly-rough surface facets through the SAR processor into the image and responses of the facets in the image domain are added together coherently to give the composite image. A windowing technique allows both the orbital motion and the phase velocity of the long waves to be included. It is determined that the azimuthal cut-off is due to a smearing of the response of the facets in the image induced by the random orbital motion of the intermediate large-scale waves and that the focus adjustment that gives the greatest image contrast is half the phase velocity of the dominant long wave. The optimal processing technique, however, may consist of spatially offsetting the multiple looks on the image domain to compensate the propagation of long waves during the integration time of the SAR.

West, James C.↗

Implementation of a digital optical matrix-vector multiplier using a holographic look-up table and residue arithmetic

The design and implementation of a digital (numerical) optical matrix-vector multiplier are presented. The objective is to demonstrate the operation of an optical processor designed to minimize computation time in performing a practical computing application. This is done by using the large array of processing elements in a Hughes liquid crystal light valve, and relying on the residue arithmetic representation, a holographic optical memory, and position coded optical look-up tables. In the design, all operations are performed in effectively one light valve response time regardless of matrix size. The features of the design allowing fast computation include the residue arithmetic representation, the mapping approach to computation, and the holographic memory. In addition, other features of the work include a practical light valve configuration for efficient polarization control, a model for recording multiple exposures in silver halides with equal reconstruction efficiency, and using light from an optical fiber for a reference beam source in constructing the hologram. The design can be extended to implement larger matrix arrays without increasing computation time.

Habiby, Sarry F.↗

Mode-multiplexed photonic integrated vector dot-product core from inverse design

Photonic computing has the potential to harness the full degrees of freedom (DOFs) of the light field, including the wavelength, spatial mode, spatial location, phase quadrature, and polarization, to achieve a higher level of computing parallelism and scalability than digital electronic processors. While multiplexing using the wavelength and other DOFs can be readily integrated on silicon photonics platforms with compact footprints, conventional mode-division multiplexed (MDM) photonic designs occupy areas exceeding tens to hundreds of microns for a few spatial modes, significantly limiting their scalability. Here, we utilize inverse design to demonstrate an ultracompact photonic computing core that calculates vector dot products based on MDM coherent mixing. Our dot-product core integrates the functionalities of two-mode multiplexers and one multimode coherent mixer within a nominal footprint of 5 μm x 3 μm . We have experimentally demonstrated computing examples on the fabricated dot-product core, including complex number multiplication and motion estimation using optical flow. The compact dot-product core design enables large-scale on-chip integration in a parallel photonic computing primitive cluster for high-throughput scientific computing and computer vision tasks.

97 MATHEMATICS AND COMPUTING↗

Digitally Calibrated TR Modules Enabling Real-Time Beamforming SweepSAR Architectures

SweepSAR, a novel radar architecture that depends on a DBF (digital beamforming) array, requires calibration accuracies that are order(s) of magnitude greater than is possible with traditional techniques, such as a priori characterization of TR (transmit/receive) modules in thermal vacuum chambers, or simple loop-back of the calibration signal. The advantages of a SweepSAR architecture are so great that it is worth applying significant resources to calibration efforts. Due to the nature of the DBF, each channel contains a digitizer and very powerful digital processor. Each channel can independently digitize (with the digitizer) and analyze (with the processor) its channel's unique calibration signal, and extract the relevant calibration parameters, namely channel gain and channel phase delay commonly referred to as the gain (or amplitude) and phase of the channel. Using the processor, each channel's gain and phase can theoretically be estimated with arbitrary precision through averaging a sufficiently large number of samples. Systematic errors and the changing gain and phase of the channels, typically due to temperature drifts, limits how long the averaging can occur, which limits the precision of the calibration estimate. However, results indicate that calibration knowledge of both the transmit and receive chains of each TR module can be improved by one or two orders of magnitude. Due to the digital nature of the receiver data, the channel's gain and phase may be corrected by a similar amount, while the transmit chain can only be corrected in a traditional manner. To implement Sweep SAR, the order of magnitude improvement in the knowledge of the channel's gain and phase is needed, and the control of the receiver to a similar level is required. Inherent to the DBF array is the individual digitization of each of the array's receiver channels. Current systems typically combine all of the analog signals in the array into one or two analog channels, which are then digitized and processed. All signal conditioning performed prior to digitization is done using analog hardware (which is less precise than digital signal conditioning and dependent on temperature). The DBF digitizes every signal prior to combining, and can therefore analyze and correct received signals, as well as analyze signals that are being transmitted through analog hardware (by sampling a copy and digitizing). Each channel of a DBF also has a powerful processor. With this combination, one is able to digitize, analyze, and correct each channel prior to its being combined. A unique factor is the ability to digitize and analyze (in real time) each of the array's channels independently, allowing one to achieve unprecedented knowledge of each channel's performance (gain and phase), and since the combining is done digitally, each receive channel can be corrected prior to combining. This enables an unprecedented level of accuracy and control through onboard processing. SweepSAR promises significant increases in instrument capability for solid earth and biomass remote sensing, while reducing mission mass and cost. This new instrument concept requires new methods for calibrating the multiple channels, which must be combined onboard, in real time. New methods are being developed for digitally calibrating digital beam-forming arrays to reduce development time, risk, and cost of precision calibrated TR modules for array architectures by accurately tracking modules' characteristics through closed-loop digital calibration, thus tracking systematic changes regardless of temperature.-

Hoffman, James P.↗

Adapting the Reconfigurable SpaceCube Processing System for Multiple Mission Applications

This paper will detail the use of SpaceCube in multiple space flight applications including the Hubble Space Telescope Servicing Mission 4 (HST-SM4), an International Space Station (ISS) radiation test bed experiment, and the main avionics subsystem for two separate ISS attached payloads. Each mission has had varying degrees of data processing complexities, performance requirements, and external interfaces. We will show the methodology used to minimize the changes required to the physical hardware, FPGA designs, embedded software interfaces, and testing.This paper will summarize significant results as they apply to each mission application. In the HST-SM4 application we utilized the FPGA resources to accelerate portions of the image processing algorithms more than 25 times faster than a standard space processor in order to meet computational speed requirements. For the ISS radiation on-orbit demonstration, the main goal is to show that we can rely on the commercial FPGAs and processors in a space environment. We describe our FPGA and processor radiation mitigation strategies that have resulted in our eight PowerPCs being available and error free for more than 99.99 of the time over the period of four years. This positive data and proven reliability of the SpaceCube on ISS resulted in the Department of Defense (DoD) selecting SpaceCube, which is replacing an older and slower computer currently used on ISS, as the main avionics for two upcoming ISS experiment campaigns. This paper will show how we quickly reconfigured the SpaceCube system to meet the more stringent reliability requirements

SpaceCube↗

Automatic Data Distribution for CFD Applications on Structured Grids

Development of HPF versions of NPB and ARC3D showed that HPF has potential to be a high level language for parallelization of CFD applications. The use of HPF requires an intimate knowledge of the applications and a detailed analysis of data affinity, data movement and data granularity. Since HPF hides data movement from the user even with this knowledge it is easy to overlook pieces of the code causing low performance of the application. In order to simplify and accelerate the task of developing HPF versions of existing CFD applications we have designed and partially implemented ADAPT (Automatic Data Distribution and Placement Tool). The ADAPT analyzes a CFD application working on a single structured grid and generates HPF TEMPLATE, (RE)DISTRIBUTION, ALIGNMENT and INDEPENDENT directives. The directives can be generated on the nest level, subroutine level, application level or inter application level. ADAPT is designed to annotate existing CFD FORTRAN application performing computations on single or multiple grids. On each grid the application can considered as a sequence of operators each applied to a set of variables defined in a particular grid domain. The operators can be classified as implicit, having data dependences, and explicit, without data dependences. In order to parallelize an explicit operator it is sufficient to create a template for the domain of the operator, align arrays used in the operator with the template, distribute the template, and declare the loops over the distributed dimensions as INDEPENDENT. In order to parallelize an implicit operator, the distribution of the operator's domain should be consistent with the operator's dependences. Any dependence between sections distributed on different processors would preclude parallelization if compiler does not have an ability to pipeline computations. If a data distribution is "orthogonal" to the dependences of an implicit operator then the loop which implements the operator can be declared as INDEPENDENT.

Frumkin, Michael↗

Certified randomness using a trapped-ion quantum processor

Although quantum computers can perform a wide range of practically important tasks beyond the abilities of classical computers, realizing this potential remains a challenge. An example is to use an untrusted remote device to generate random bits that can be certified to contain a certain amount of entropy. Certified randomness has many applications but is impossible to achieve solely by classical computation. Here we demonstrate the generation of certifiably random bits using the 56-qubit Quantinuum H2-1 trapped-ion quantum computer accessed over the Internet. Our protocol leverages the classical hardness of recent random circuit sampling demonstrations: a client generates quantum ‘challenge’ circuits using a small randomness seed, sends them to an untrusted quantum server to execute and verifies the results of the server. We analyse the security of our protocol against a restricted class of realistic near-term adversaries. Using classical verification with measured combined sustained performance of 1.1 × 10 18 floating-point operations per second across multiple supercomputers, we certify 71,313 bits of entropy under this restricted adversary and additional assumptions. Our results demonstrate a step towards the practical applicability of present-day quantum computers.

computer science↗

Parallel Wavefront Analysis for a 4D Interferometer

This software provides a programming interface for automating data collection with a PhaseCam interferometer from 4D Technology, and distributing the image-processing algorithm across a cluster of general-purpose computers. Multiple instances of 4Sight (4D Technology s proprietary software) run on a networked cluster of computers. Each connects to a single server (the controller) and waits for instructions. The controller directs the interferometer to several images, then assigns each image to a different computer for processing. When the image processing is finished, the server directs one of the computers to collate and combine the processed images, saving the resulting measurement in a file on a disk. The available software captures approximately 100 images and analyzes them immediately. This software separates the capture and analysis processes, so that analysis can be done at a different time and faster by running the algorithm in parallel across several processors. The PhaseCam family of interferometers can measure an optical system in milliseconds, but it takes many seconds to process the data so that it is usable. In characterizing an adaptive optics system, like the next generation of astronomical observatories, thousands of measurements are required, and the processing time quickly becomes excessive. A programming interface distributes data processing for a PhaseCam interferometer across a Windows computing cluster. A scriptable controller program coordinates data acquisition from the interferometer, storage on networked hard disks, and parallel processing. Idle time of the interferometer is minimized. This architecture is implemented in Python and JavaScript, and may be altered to fit a customer s needs.

Rao, Shanti R.↗

NOR Flash Memory Scrubbing Application for Boot File Preservation of NASA’s Descent and Landing Computer (DLC)

Progress on NASA’s Safe and Precise Landing Integrated Capabilities Evolution (SPLICE)project continues, specifically with this development of the Descent and Landing Computer(DLC). One of the DLC’s primary contributions as a SPLICE technology is its implementationof algorithms and operation of sensors to autonomously guide a spacecraft in performing moreprecise and safer landings on celestial bodies such as the Moon and Mars. The second iterationof the DLC is known as the Engineering Test Unit (ETU) and one of its desired functionalitiesis the ability to preserve the fidelity of the system’s boot file through the use of memoryscrubbing. The ETU has two primary boards, one for housing a Multi-Processor System ona Chip (MPSoC) and the other for housing a Xilinx Kintex Ultrascale FPGA3. To emulate amemory scrubbing function implemented on the ETU’s FPGA board, the design and testingof a software application was performed on a Xilinx KCU105 FPGA evaluation board. Thememory scrubbing application had to meet certain key criteria such as (1) properly utilize withthe flash memory’s Serial Peripheral Interface (SPI) to read, write, and erase flash memoryproperly, (2) be able to detect arbitrarily large or small amounts of bit-errors, (3) be able tocorrect all detected errors, and (4) perform memory scrubbing indefinitely and autonomously.A prototype implementation was constructed and tested, demonstrating successful detectionand correction of bit errors in multiple configurations. In the form of burst errors or singularbit flips, and in amounts of errors ranging from one to fifteen (per 256 Bytes), the applicationwas successful in preserving memory fidelity.

Radiation tolerant↗