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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 559 records · Page 31

All sources NASA NTRS DOE OSTI

DOE OSTI2017

System on chip module configured for event-driven architecture

A system on chip (SoC) module is described herein, wherein the SoC modules comprise a processor subsystem and a hardware logic subsystem. The processor subsystem and hardware logic subsystem are in communication with one another, and transmit event messages between one another. The processor subsystem executes software actors, while the hardware logic subsystem includes hardware actors, the software actors and hardware actors conform to an event-driven architecture, such that the software actors receive and generate event messages and the hardware actors receive and generate event messages.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2017

Computing an operating parameter of a unified power flow controller

A Unified Power Flow Controller described herein comprises a sensor that outputs at least one sensed condition, a processor that receives the at least one sensed condition, a memory that comprises control logic that is executable by the processor; and power electronics that comprise power storage, wherein the processor causes the power electronics to selectively cause the power storage to act as one of a power generator or a load based at least in part upon the at least one sensed condition output by the sensor and the control logic, and wherein at least one operating parameter of the power electronics is designed to facilitate maximal transmittal of electrical power generated at a variable power generation system to a grid system while meeting power constraints set forth by the electrical power grid.

24 POWER TRANSMISSION AND DISTRIBUTION↗

DOE OSTI2018

Near-memory data reorganization engine

A memory subsystem package is provided that has processing logic for data reorganization within the memory subsystem package. The processing logic is adapted to reorganize data stored within the memory subsystem package. In some embodiments, the memory subsystem package includes memory units, a memory interconnect, and a data reorganization engine ("DRE"). The data reorganization engine includes a stream interconnect and DRE units including a control processor and a load-store unit. The control processor is adapted to execute instructions to control a data reorganization. The load-store unit is adapted to process data move commands received from the control processor via the stream interconnect for loading data from a load memory address of a memory unit and storing data to a store memory address of a memory unit.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2018

Producing EGS4 Shower Displays with the Unified Graphics System

The EGS4 Code System has been coupled with the SLAC Unified Graphics System in such a manner as to provide a means for displaying showers on UGS77-supported devices. This is most easily accomplished by attaching an auxiliary subprogram package (SHOWGRAF) t o existing EGS4 User Codes and making use of a graphics display or a post-processor code called EGS4PL. SHOWGRAF shower displays directly on interactive ing three-dimensional rotations, translations, may be used to create IBM 5080 color display devices, support- and zoom features, and providing illustration of particle types and energies by color and/or intensity. Alternatively, SHOWGRAF may be used to record a two-dimensional projection of the shower in a device-independent graphics file. The EGS4PL post-processor may then be used to convert this file into device-dependent graphics code for any UGS77-supported device. Options exist within EGS4PL that allow for two-dimensional translations and zoom, for creating line structure to indicate particle types and energies, and for optional display of particles by type. All of this is facilitated by means of the command processor EGS4PL EXEC together with new options (5080 and PDEV) with the standard EGS4IN EXEC routine for running EGS4 interactively under VM/SP.

Cowan, R.↗

DOE OSTI2018

Hardware accuracy counters for application precision and quality feedback

Methods, devices, and systems for capturing an accuracy of an instruction executing on a processor. An instruction may be executed on the processor, and the accuracy of the instruction may be captured using a hardware counter circuit. The accuracy of the instruction may be captured by analyzing bits of at least one value of the instruction to determine a minimum or maximum precision datatype for representing the field, and determining whether to adjust a value of the hardware counter circuit accordingly. The representation may be output to a debugger or logfile for use by a developer, or may be output to a runtime or virtual machine to automatically adjust instruction precision or gating of portions of the processor datapath.

47 OTHER INSTRUMENTATION↗

DOE OSTI2018

Apparatus, system, and method for sensor authentication

A method includes receiving an output signal from a sensor, recovering a noise signal from the output signal, comparing the noise signal with a stored baseline noise signature, and reporting authentication of the sensor if the comparison is within a pre-determined error limit. A sensor authentication apparatus, comprises a processor and a memory operably coupled with the processor. Instructions, when executed, cause the processor to separate a noise signal from a measured signal, and detect a noise signature match by comparing the noise signal with at least one stored baseline noise signature associated with the sensor. A sensor authentication system comprises a sensor authentication unit and a data acquisition unit. At least one of the sensor authentication unit and the data acquisition unit is configured to compare a noise signal with a baseline noise signature to authenticate the at least one sensor from among a plurality of sensors.

Svoboda, John M.↗

DOE OSTI2018

System on chip module configured for event-driven architecture

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2018

System and method for groundwater detection and evaluation

A system for mapping a depth of an aquifer and determining the presence and salinity of water from the aquifer and methods for using the making/using the same includes a central processor. One or more horizontal loop transmitters can be coupled to the central processor, wherein said one or more horizontal loop transmitters produce a first half-sine pulse of magnetic field at a first pulse duration for measuring the resistivity of a ground surface. The one or more horizontal loop transmitters can produce a second sequence of half-sine pulses at a second frequency for creating an excitation field for magnetic resonance sounding. A multi-turn receiver loop antenna can also be coupled to the central processor, wherein said multi-turn receiver loop antenna receives an induced magnetic field from said one or more horizontal loop transmitters that is representative of the depth of an aquifer and the salinity of the water.

47 OTHER INSTRUMENTATION↗

DOE OSTI2019

Device and method for the location and identification of a radiation source

A handheld device for the location and identification of a radiation source, including: a radiation transparent housing; a radiation locator device disposed within the radiation transparent housing operable for determining the location of the radiation source, wherein the radiation locator device includes a plurality of gamma detection crystals arranged in a geometric pattern and separated by a gamma shielding material, a plurality of detectors coupled to the plurality of gamma detection crystals, and a processor module coupled to the plurality of detectors; one or more of a neutron detection crystal and a gamma spectroscopy crystal disposed within the radiation transparent housing adjacent to the radiation locator device; and one or more detectors coupled to the one or more of the neutron detection crystal and the gamma spectroscopy crystal and the processor module; wherein the one or more of the neutron detection crystal and the gamma spectroscopy crystal, the one or more detectors, and the processor module are collectively operable for identifying the radiation source.

Vencelj, Matjaz↗

DOE OSTI2015

Ground-referenced single-ended signaling connected graphics processing unit multi-chip module

A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a graphics processing cluster (GPC) chip, and an MCM package configured to include the first processor chip, the GPC chip, and an interconnect circuit. The first processor chip is configured to include a first ground-referenced single-ended signaling interface circuit. A first set of electrical traces fabricated within the MCM package and configured to couple the first single-ended signaling interface circuit to the interconnect circuit. The GPC chip is configured to include a second single-ended signaling interface circuit and to execute shader programs. A second set of electrical traces fabricated within the MCM package and configured to couple the second single-ended signaling interface circuit to the interconnect circuit. In one embodiment, each single-ended signaling interface advantageously implements ground-referenced single-ended signaling.

Dally, William J.↗

DOE OSTI2015

Ground-referenced single-ended signaling connected graphics processing unit multi-chip module

A system of interconnected chips comprising a multi-chip module (MCM) includes a processor chip, a system functions chip, and an MCM package configured to include the processor chip, the system functions chip, and an interconnect circuit. The processor chip is configured to include a first ground-referenced single-ended signaling interface circuit. A first set of electrical traces manufactured within the MCM package and configured to couple the first single-ended signaling interface circuit to the interconnect circuit. The system functions chip is configured to include a second single-ended signaling interface circuit and a host interface. A second set of electrical traces manufactured within the MCM package and configured to couple the host interface to at least one external pin of the MCM package. In one embodiment, each single-ended signaling interface advantageously implements ground-referenced single-ended signaling.

Dally, William J.↗

DOE OSTI2016

System, method, and computer program product for scheduling tasks associated with continuation thread blocks

A system, method, and computer program product for scheduling tasks associated with continuation thread blocks. The method includes the steps of generating a first task metadata data structure in a memory, generating a second task metadata data structure in the memory, executing a first task corresponding to the first task metadata data structure in a processor, generating state information representing a continuation task related to the first task and storing the state information in the second task metadata data structure, executing the continuation task in the processor after the one or more child tasks have finished execution, and indicating that the first task has logically finished execution once the continuation task has finished execution. The second task metadata data structure is related to the first task metadata data structure, and at least one instruction in the first task causes one or more child tasks to be executed by the processor.

Ricketts, Scott↗

DOE OSTI2019

System and method for adaptive range 3D scanning

A scanner system is configured for acquiring three dimensional image information of an object. The scanner includes a projector, a camera, a graphics processing device, and a processor. The projector projects one of several pre-defined patterns upon the object. The camera captures an image from the object, which is received by the processor. The processor approximates mutual information from the object and the pattern using the graphics processing device, and selects a second pattern for projecting on the object.

Rosman, Guy↗

DOE OSTI2019

Real time feedback-based optimization of distributed energy resources

An example device includes a processor configured to receive a plurality of voltage values corresponding to voltage nodes in a first portion of a power system and determine, for each voltage node, a respective value of first and second voltage-constraint coefficients. The processor is also configured to receive a power value corresponding to a connection point of the first portion of the power system with a second portion of the power system and determine for the connection point, a respective value of first and second power-constraint coefficients. The processor is also configured to cause at least one energy resource connected to the first portion of the power system to modify an output power of the at least one energy resource based on the value of the first and second voltage-constraint coefficients for each voltage node and the value of the first and second power-constraint coefficients.

24 POWER TRANSMISSION AND DISTRIBUTION↗

DOE OSTI2020

Dynamically adapting mechanism for translation lookaside buffer shootdowns

An operating system (OS) of a processing system having a plurality of processor cores determines a cost associated with different mechanisms for performing a translation lookaside buffer (TLB) shootdown in response to, for example, a virtual address being remapped to a new physical address, and selects a TLB shootdown mechanism to purge outdated or invalid address translations from the TLB based on the determined cost. In some embodiments, the OS selects an inter-processor interrupt (IPI) as the TLB shootdown mechanism if the cost associated with sending an IPI is less than a threshold cost. In some embodiments, the OS compares the cost of using an IPI as the TLB shootdown mechanism versus the cost of sending a hardware broadcast to all processor cores of the processing system as the shootdown mechanism and selects the shootdown mechanism having the lower cost.

42 ENGINEERING↗

DOE OSTI2020

Constructing a conforming Voronoi mesh for an arbitrarily-shaped enclosed geometric domain

A computing system is described herein, where the computing system includes a processor and memory storing instructions that, when executed by the processor, cause the processor to perform the following acts: 1) receiving a computer-implemented definition of an enclosed geometric domain, wherein the geometric domain is two-dimensional; 2) determining locations of seeds for the enclosed geometric domain; 3) decomposing the enclosed geometric domain into a conforming Voronoi mesh based on the locations of the seeds, wherein the conforming Voronoi mesh comprises Voronoi cells, and further wherein the conforming Voronoi mesh is bounded by the enclosed domain; and 4) performing a numerical simulation to generate simulation results, wherein the numerical simulation is based on at least one Voronoi cell in the Voronoi cells of the conforming Voronoi mesh.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2020

Constructing a conforming voronoi mesh for an arbitrarily-shaped enclosed geometric domain

A computing system is described herein, where the computing system includes a processor and memory storing instructions that, when executed by the processor, cause the processor to perform the following acts: 1) receiving a computer-implemented definition of an enclosed geometric domain, wherein the geometric domain is three-dimensional; 2) determining locations of seeds for the enclosed geometric domain; 3) decomposing the enclosed geometric domain into a conforming Voronoi mesh based on the locations of the seeds, wherein the conforming Voronoi mesh comprises Voronoi cells, and further wherein the conforming Voronoi mesh is bounded by the enclosed domain; and 4) performing a numerical simulation to generate simulation results, wherein the numerical simulation is based on at least one Voronoi cell in the Voronoi cells of the conforming Voronoi mesh.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2020

Device and method for cache utilization aware data compression

A processing device is provided which includes memory and at least one processor. The memory includes main memory and cache memory in communication with the main memory via a link. The at least one processor is configured to receive a request for a cache line and read the cache line from main memory. The at least one processor is also configured to compress the cache line according to a compression algorithm and, when the compressed cache line includes at least one byte predicted not to be accessed, drop the at least one byte from the compressed cache line based on whether the compression algorithm is determined to successfully compress the cache line according to a compression parameter.

Das, Shomit N.↗