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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 559 records · Page 31
All sourcesNASA NTRSDOE OSTI
NASA NTRS1976

The autocorrelation structure of Tausworthe pseudorandom number generators

An algorithm for determining the autocorrelation structure of a new sequence generated from an original sequence by proper decimation (a shift with each q-th term of the original sequence used) is presented, once autocorrelations for any repeating number sequence are known. The autocorrelation structure of the Tausworthe random number generator (RNG), based on proper decimation by q, is accepted as a RNG structure in which a proper decimation generates a long interval over which autocorrelations are small for all shifts. It is shown that if L bits of an N-bit Tausworthe RNG are L-bit binary numbers, L + 1 levels of correlation will exist, and L levels of correlation will each occur twice per RNG cycle length.

Neuman, F.↗
NASA NTRS1977

Development of a high capacity bubble domain memory element and related epitaxial garnet materials for application in spacecraft data recorders. Item 1: Development of a high capacity memory element

Several versions of the 100K bit chip, which is configured as a single serial loop, were designed, fabricated and evaluated. Design and process modifications were introduced into each succeeding version to increase device performance and yield. At an intrinsic field rate of 150 KHz the final design operates from -10 C to +60 C with typical bias margins of 12 and 8 percent, respectively, for continuous operation. Asynchronous operation with first bit detection on start-up produces essentially the same margins over the temperature range. Cost projections made from fabrication yield runs on the 100K bit devices indicate that the memory element cost will be less than 10 millicents/bit in volume production.

Besser, P. J.↗
NASA NTRS1976

Performance of convolutionally encoded noncoherent MFSK modem in fading channels

The performance of a convolutionally encoded noncoherent multiple-frequency shift-keyed (MFSK) modem utilizing Viterbi maximum-likelihood decoding and operating on a fading channel is described. Both the lognormal and classical Rician fading channels are considered for both slow and time-varying channel conditions. Primary interest is in the resulting bit error rate as a function of the ratio between the energy per transmitted information bit and noise spectral density, parameterized by both the fading channel and code parameters. Fairly general upper bounds on bit error probability are provided and compared with simulation results in the two extremes of zero and infinite channel memory. The efficacy of simple block interleaving in combatting channel memory effects are thoroughly explored. Both quantized and unquantized receiver outputs are considered.

Modestino, J. W.↗
NASA NTRS1976

High-density digital data recording/reproducing system

Problems associated with reliably recording and reproducing digital data at densities of 10 to 30 kilobits per inch and the solutions to these problems are discussed. The three problems are skew, dc offset, and tape imperfections. The solutions are to use a 14-track, wideband II tape recorder; record NRZ-L; use a 24-bit sync word, 504-bit frame length, and odd parity in every 8-bit byte; and to employ circuit design techniques that minimize the effects of the remaining dc offset and tape imperfections.

Leighou, R. O.↗
NASA NTRS1979

Efficient digital encoding scheme

Modified NRZ (non-return-to-zero) code immunizes record and playback systems against dc drift and bit slippage. In order to maximize bit packing density improved code called J-NRZ gives 100 percent NRZ efficiently and solves DC drift problem by adding check bits in specified format when long string is encountered. Remainder of data stream is encoded in NRZ format.

Obrien, D. E., III↗
NASA NTRS1978

FPLA mechanization of arithmetic elements to produce A + B or to pass A only

A 4-bit and a 3-bit adder are described which can be implemented under special hardware restrictions. The chip to be used is field-programmable logic array (FPLA) with 12 input lines, 50 AND gates inside, and output through only 6 OR gates. The context in which it is being used requires an enable function which can suppress one of the two numbers to be added. The 3-bit enabled adder is compatible with lookahead-carry mechanizations using the 74S182.

Wallis, D. E.↗
NASA NTRS1979

NASF transposition network: A computing network for unscrambling p-ordered vectors

The viewpoints of design, programming, and application of the transportation network (TN) is presented. The TN is a programmable combinational logic network that connects 521 memory modules to 512 processors. The unscrambling of p-ordered vectors to 1-ordered vectors in one cycle is described. The TN design is based upon the concept of cyclic groups from abstract algebra and primitive roots and indices from number theory. The programming of the TN is very simple, requiring only 20 bits: 10 bits for offset control and 10 bits for barrel switch shift control. This simple control is executed by the control unit (CU), not the processors. Any memory access by a processor must be coordinated with the CU and wait for all other processors to come to a synchronization point. These wait and synchronization events can be a degradation in performance to a computation. The TN application is for multidimensional data manipulation, matrix processing, and data sorting, and can also perform a perfect shuffle. Unlike other more complicated and powerful permutation networks, the TN cannot, if possible at all, unscramble non-p-ordered vectors in one cycle.

Lim, R. S.↗
NASA NTRS1978

The feasibility of inflight measurement of lightning strike parameters

The appearance of nonmetallic structural materials and microelectronics in aircraft design has resulted in a need for better knowledge of hazardous environments such as lightning and the effects these environments have on the aircraft. This feasibility study was performed to determine the lightning parameters in the greatest need of clarification and the performance requirements of equipment necessary to sense and record these parameters on an instrumented flight research aircraft. It was found that electric field rate of change, lightning currents, and induced voltages in aircraft wiring are the parameters of greatest importance. Flat-plate electric field sensors and resistive current shunts are proposed for electric field and current sensors, to provide direct measurements of these parameters. Six bit analog-to-digital signal conversion at a 5 nanosecond sampling rate, short-term storage of 85000 bits and long term storage of 5 x 10 to the 7th power bits of electric field, current and induced voltage data on the airplane are proposed, with readout and further analysis to be accomplished on the ground. A NASA F-106B was found to be suitable for use as the research aircraft because it has a minimum number of possible lightning attachment points, space for the necessary instrumentation, and appears to meet operational requirements. Safety considerations are also presented.

Crouch, K. E.↗
NASA NTRS1978

Video encoding using adaptive delta modulation

Research work is described that was carried out to develop adaptive delta modulators (ADM) capable of encoding black-and-white and color video signals in the presence of high bit error rates. These were a one-dimensional ADM capable of encoding black-and-white pictures and transmitting digitally encoded voice without increase in bandwidth; an ADM capable of encoding color video signals; and an ADM capable of encoding field-sequential color. For each of these three units, the bit rate could be adjusted within the range from 6 to 24 Mbits/sec. The effects of the bit rate and channel errors on the response of the picture are examined.

Schilling, D. L.↗
NASA NTRS1978

Comparison of video fields and frames for transform compression

Because of the interlaced television scan, the two fields that form an interlaced video frame are generated 1/60 of a second apart. If the two fields are compressed independently, the correlation between adjacent lines is unused. The transmission rate can be reduced by using a field memory to form an interlaced frame. Four test images were processed as fields and as interlaced frames, using both theoretical and experimental compression designs. For comparable mean-square error and subjective appearance, field compression requires about one-half bit per sample more than frame compression. However, the overall transmission rate - the number of bits per image times the number of images per second - is more meaningful than the number of bits per sample. When transform compression at low transmission rates merges the adjacent lines, frame compression becomes similar to field repeating, and the memory can be reduced.

Jones, H. W., Jr.↗
NASA NTRS1979

Digital Image Display Control System, DIDCS

DIDCS is an interactive image display and manipulation system that is used for a variety of astronomical image reduction and analysis operations. The hardware system consists of a PDP 11/40 main frame with 32K of 16-bit core memory; 96K of 16-bit MOS memory; two 9 track 800 BPI tape drives; eight 2.5 million byte RKO5 type disk packs, three user terminals, and a COMTAL 8000-S display system which has sufficient memory to store and display three 512 x 512 x 8 bit images along with an overlay plane and function table for each image, a pseudo color table and the capability for displaying true color. The software system is based around the language FORTH, which will permit an open ended dictionary of user level words for image analyses and display. A description of the hardware and software systems will be presented along with examples of the types of astronomical research that are being performed. Also a short discussion of the commonality and exchange of this type of image analysis system will be given.

Fischel, D.↗
NASA NTRS1980

Microprocessor-controlled data synchronizer

Versatile receiver processes data at variety of rates and code formats. Functions performed are: bit detection, NRZ-L conversion, frame synchronization (with programmable word length), bit-sync acquisition and tracking, error-curve normalization, lock detection, half-bit-ambiguity resolution, and data-rate tracking.

Houston, S. W.↗
NASA NTRS1979

The suitability of the ILLIAC IV architecture for image processing

The major architectural features of the ILLIAC IV large scale, array processor are summarized along with their applicability to image processing. Several image processing algorithms are considered, including multispectral classification, texture feature extraction, two-dimensional Fourier transform, and synthetic aperture radar processing. The basic parallelism of the ILLIAC IV (64 processing elements acting in lock-step) is usually fully utilized by the image processing applications. The major architectural aspect of the system with respect to image processing is the relatively small local scratch-pad memory and the long latency time to access the main storage device. The major precision used for the image processing applications is the 32-bit floating point, given a choice of 8-bit integers and 64-bit floating point.

Stevenson, D. K.↗
NASA NTRS1980

Design of a massively parallel processor

The massively parallel processor (MPP) system is designed to process satellite imagery at high rates. A large number (16,384) of processing elements (PE's) are configured in a square array. For optimum performance on operands of arbitrary length, processing is performed in a bit-serial manner. On 8-bit integer data, addition can occur at 6553 million operations per second (MOPS) and multiplication at 1861 MOPS. On 32-bit floating-point data, addition can occur at 430 MOPS and multiplication at 216 MOPS.

Batcher, K. E.↗
NASA NTRS1981

The effect of noisy carrier reference on telemetry with baseband arraying

Imperfect carrier reference causes a degradation in detection performance in coherent communication systems. A measure of this degradation is the radio loss, which is the amount of increase in data signal to noise ratio (SNR) per bit required to achieve the same bit error rate when carrier reference is perfect. Performance analysis and numerical results are obtained for the Voyager high rate telemetry link with maximum likelihood convolutional decoding. The arraying of antennas provides not only improved performance due to an increase in effective antenna aperture, but also a decrease in radio loss with respect to a single antenna. This telemetry link performance improvement is a function of the carrier loop SNR and data bit error rate. When the carrier loop SNR's are low, it provides a significant improvement in the telemetry link performance since the decrease in radio loss with respect to a single station is substantial.

Divsalar, D.↗
NASA NTRS1982

Evaluation of the SPAR thermal analyzer on the CYBER-203 computer

The use of the CYBER 203 vector computer for thermal analysis is investigated. Strengths of the CYBER 203 include the ability to perform, in vector mode using a 64 bit word, 50 million floating point operations per second (MFLOPS) for addition and subtraction, 25 MFLOPS for multiplication and 12.5 MFLOPS for division. The speed of scalar operation is comparable to that of a CDC 7600 and is some 2 to 3 times faster than Langley's CYBER 175s. The CYBER 203 has 1,048,576 64-bit words of real memory with an 80 nanosecond (nsec) access time. Memory is bit addressable and provides single error correction, double error detection (SECDED) capability. The virtual memory capability handles data in either 512 or 65,536 word pages. The machine has 256 registers with a 40 nsec access time. The weaknesses of the CYBER 203 include the amount of vector operation overhead and some data storage limitations. In vector operations there is a considerable amount of time before a single result is produced so that vector calculation speed is slower than scalar operation for short vectors.

Robinson, J. C.↗
NASA NTRS1982

A generalized memory test algorithm

A general algorithm for testing digital computer memory is presented. The test checks that (1) every bit can be cleared and set in each memory work, and (2) bits are not erroneously cleared and/or set elsewhere in memory at the same time. The algorithm can be applied to any size memory block and any size memory word. It is concise and efficient, requiring the very few cycles through memory. For example, a test of 16-bit-word-size memory requries only 384 cycles through memory. Approximately 15 seconds were required to test a 32K block of such memory, using a microcomputer having a cycle time of 133 nanoseconds.

Milner, E. J.↗
NASA NTRS1982

A compact presentation of DSN array telemetry performance

The telemetry performance of an arrayed receiver system, including radio losses, is often given by a family of curves giving bit error rate vs bit SNR, with tracking loop SNR at one receiver held constant along each curve. This study shows how to process this information into a more compact, useful format in which the minimal total signal power and optimal carrier suppression, for a given fixed bit error rate, are plotted vs data rate. Examples for baseband-only combining are given. When appropriate dimensionless variables are used for plotting, receiver arrays with different numbers of antennas and different threshold tracking loop bandwidths look much alike, and a universal curve for optimal carrier suppression emerges.

Greenhall, C. A.↗