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At least 559 records · Page 31

Probabilistic Nanomagnetic Memories for Uncertain and Robust Machine Learning

This project evaluated the use of emerging spintronic memory devices for robust and efficient variational inference schemes. Variational inference (VI) schemes, which constrain the distribution for each weight to be a Gaussian distribution with a mean and standard deviation, are a tractable method for calculating posterior distributions of weights in a Bayesian neural network such that this neural network can also be trained using the powerful backpropagation algorithm. Our project focuses on domain-wall magnetic tunnel junctions (DW-MTJs), a powerful multi-functional spintronic synapse design that can achieve low power switching while also opening the pathway towards repeatable, analog operation using fabricated notches. Our initial efforts to employ DW-MTJs as an all-in-one stochastic synapse with both a mean and standard deviation didn’t end up meeting the quality metrics for hardware-friendly VI. In the future, new device stacks and methods for expressive anisotropy modification may make this idea still possible. However, as a fall back that immediately satisfies our requirements, we invented and detailed how the combination of a DW-MTJ synapse encoding the mean and a probabilistic Bayes-MTJ device, programmed via a ferroelectric or ionically modifiable layer, can robustly and expressively implement VI. This design includes a physics-informed small circuit model, that was scaled up to perform and demonstrate rigorous uncertainty quantification applications, up to and including small convolutional networks on a grayscale image classification task, and larger (Residual) networks implementing multi-channel image classification. Lastly, as these results and ideas all depend upon the idea of an inference application where weights (spintronic memory states) remain non-volatile, the retention of these synapses for the notched case was further interrogated. These investigations revealed and emphasized the importance of both notch geometry and anisotropy modification in order to further enhance the endurance of written spintronic states. In the near future, these results will be mapped to effective predictions for room temperature and elevated operation DW-MTJ memory retention, and experimentally verified when devices become available.

77 NANOSCIENCE AND NANOTECHNOLOGY↗

New Results on Communication- and Memory-Aware Load Balancing Model and Algorithms

While load balancing in distributed-memory computing has been well-studied, we present an innovative approach to this problem: a unified, reduced-order model that combines three key components to describe “work” in a distributed system: computation, communication, and memory. Our model enables an optimizer to explore complex tradeoffs in task placement, such as augmented parallelism, at the expense of data replication increasing memory usage. We propose a fully distributed, heuristic-based load balancing optimization algorithm, and demonstrate that it quickly finds close-to-optimal solutions. We formalize the complex optimization problem as a mixed-integer linear program, and compare it to our strategy. Finally, we show that when applied to an electromagnetics code, our approach obtains up to 2.3x speedups for the imbalanced execution.

97 MATHEMATICS AND COMPUTING↗

Loss of Mitochondrial Tusc2/Fus1 Triggers a Brain Pro-Inflammatory Microenvironment and Early Spatial Memory Impairment

Brain pathological changes impair cognition early in disease etiology. There is an urgent need to understand aging-linked mechanisms of early memory loss to develop therapeutic strategies and prevent the development of cognitive impairment. Tusc2 is a mitochondrial-resident protein regulating Ca 2+ fluxes to and from mitochondria impacting overall health. We previously reported that Tusc2 –/– female mice develop chronic inflammation and age prematurely, causing age- and sex-dependent spatial memory deficits at 5 months old. Therefore, we investigated Tusc2-dependent mechanisms of memory impairment in 4-month-old mice, comparing changes in resident and brain-infiltrating immune cells. Interestingly, Tusc2 –/– female mice demonstrated a pro-inflammatory increase in astrocytes, expression of IFN-γ in CD4 + T cells and Granzyme-B in CD8 + T cells. We also found fewer FOXP3 + T-regulatory cells and Ly49G + NK and Ly49G + NKT cells in female Tusc2 –/– brains, suggesting a dampened anti-inflammatory response. Moreover, Tusc2 –/– hippocampi exhibited Tusc2- and sex-specific protein changes associated with brain plasticity, including mTOR activation, and Calbindin and CamKII dysregulation affecting intracellular Ca2 + dynamics. Overall, the data suggest that dysregulation of Ca 2+ -dependent processes and a heightened pro-inflammatory brain microenvironment in Tusc2 –/– mice could underlie cognitive impairment. Thus, strategies to modulate the mitochondrial Tusc2- and Ca 2+ - signaling pathways in the brain should be explored to improve cognitive health.

59 BASIC BIOLOGICAL SCIENCES↗

Dual redundant core memory systems

Electronic memory system consisting of series redundant drive switch circuits, triple redundant majority voted memory timing functions, and two data registers to provide functional dual redundancy is described. Signal flow through the circuits is illustrated and equence of events which occur within the memory system is explained.

Hull, F. E.↗

Apollo guidance, navigation and control: Guidance system operations plans for manned LM earth orbital and lunar missions using Program COLOSSUS 3. Section 7: Erasable memory programs

Erasable-memory programs (EMPs) designed for the guidance computers used in the command (CMC) and lunar modules (LGC) are described. CMC programs are designated COLOSSUS 3, and the associated EMPs are identified by a three-digit number beginning with 5. LGC programs are designated LUMINARY 1E, and the associated EMPs are identified, with one exception, by a three-digit number beginning with 1. The exception is EMP 99. The EMPs vary in complexity from a simple flagbit setting to a long and intricate logical structure. They all, however, cause the computer to behave in a way not intended in the original design of the programs; they accomplish this off-nominal behavior by some alteration of erasable memory to interface with existing fixed-memory programs to effect a desired result.

Hamilton, M. H.↗

Sequential behavior and its inherent tolerance to memory faults.

Representation of a memory fault of a sequential machine M by a function mu on the states of M and the result of the fault by an appropriately determined machine M(mu). Given some sequential behavior B, its inherent tolerance to memory faults can then be measured in terms of the minimum memory redundancy required to realize B with a state-assigned machine having fault tolerance type tau and fault tolerance level t. A behavior having maximum inherent tolerance is exhibited, and it is shown that behaviors of the same size can have different inherent tolerance.

Meyer, J. F.↗

Development of a monolithic ferrite memory array

The results of the development and testing of ferrite monolithic memory arrays are presented. This development required the synthesis of ferrite materials having special magnetic and physical characteristics and the development of special processes; (1) for making flexible sheets (laminae) of the ferrite composition, (2) for embedding conductors in ferrite, and (3) bonding ferrite laminae together to form a monolithic structure. Major problems encountered in each of these areas and their solutions are discussed. Twenty-two full-size arrays were fabricated and fired during the development of these processes. The majority of these arrays were tested for their memory characteristics as well as for their physical characteristics and the results are presented. The arrays produced during this program meet the essential goals and demonstrate the feasibility of fabricating monolithic ferrite memory arrays by the processes developed.

Heckler, C. H., Jr.↗

A simulation model for a memory organization for a multiprocessor.

A model for a memory organization for a multiprocessor with look-ahead and interleaved multimodule main memory is presented. The model is used to determine the extent of look-ahead and depth of interleaving that provide the most prolific speed match between processors and main memory.

Eubank, J. B.↗

Plated wire memory subsystem

The design, construction, and test history of a 4096 word by 18 bit random access NDRO Plated Wire Memory for use in conjunction with a spacecraft input/output and central processing unit is reported. A technical and functional description is given along with diagrams illustrating layout and systems operation. Test data is shown on the procedures and results of system level and memory stack testing, and hybrid circuit screening. A comparison of the most significant physical and performance characteristics of the memory unit versus the specified requirements is also included.

Carpenter, K. H.↗

Magnetic bubble domain memories

Some attractive features of Bubble Domain Memory and its relation to existing technologies are discussed. Two promising applications are block access mass memory and tape recorder replacement. The required chip capabilities for these uses are listed, and the specifications for a block access mass memory designed to fit between core and HPT disk are presented. A feasibility model for a tape recorder replacement is introduced.

Ypma, J. E.↗

Main memory unit

The development of a main memory unit (MMU) for the space ultrareliable module computer (SUMC) model HTC is discussed. The design, fabrication, and test of basic memory modules (BMM) which were to be used in the design and construction of the MMU are described. The BMM was designed from state-of-the-art technologies which included large scale integration devices mounted and interconnected on a substrate to form a functional module to be utilized in the MMU development. A SUMC memory system design study is discussed which addressed itself to the BMM design and analysis to be conducted to determine the most efficient organization of the BMM in order to establish such modularity features as: word length expandability without redesign, high reliability, and fault tolerance. One MMU was designed, fabricated, tested, and delivered which will be electrical and mechanically compatible with the hybrid technology computer (HTC) model of the SUMC family of computers. The MMU will contain a storage capacity of 8196 36 bit words which includes a parity bit for each 8 bit byte of data.

Source record↗

Quasi-perfect FIFO: Synchronous or asynchronous with application in controller design for the UNICON laser memory

The first-in-first-out memory buffer (FIFO), is an elastic digital memory whose main application is in data buffering between devices operating at different rates. Data written into the top is moved autonomously down toward the bottom of the FIFO to the lowest unoccupied location, and data read from the bottom of the FIFO will cause data from the top to move autonomously down toward the bottom. The FIFO is available in MOS LSI asynchronous form with data rate in the 1 MHz region. The FIFO described yields a simple high-speed iterative implementation, either synchronous of asynchronous. Because of this simple iterative structure, the FIFO is expandable in both number of words and bits per word, and it is attractive from the viewpoint of integrated-circuit production. For the synchronous FIFO, a model was built and successfully used in the controller for the UNICON laser memory. For the asynchronous FIFO, a model was built and also successfully used in a high-performance magnetic tape controller.

Lim, R. S.↗

Effect of virtual memory on efficient solution of two model problems

Computers with virtual memory architecture allow programs to be written as if they were small enough to be contained in memory. Two types of problems are investigated to show that this luxury can lead to quite an inefficient performance if the programmer does not interact strongly with the characteristics of the operating system when developing the program. The two problems considered are the simultaneous solutions of a large linear system of equations by Gaussian elimination and a model three-dimensional finite-difference problem. The Control Data STAR-100 computer runs are made to demonstrate the inefficiencies of programming the problems in the manner one would naturally do if the problems were indeed, small enough to be contained in memory. Program redesigns are presented which achieve large improvements in performance through changes in the computational procedure and the data base arrangement.

Lambiotte, J. J., Jr.↗

Memory device for two-dimensional radiant energy array computers

A memory device for two dimensional radiant energy array computers was developed, in which the memory device stores digital information in an input array of radiant energy digital signals that are characterized by ordered rows and columns. The memory device contains a radiant energy logic storing device having a pair of input surface locations for receiving a pair of separate radiant energy digital signal arrays and an output surface location adapted to transmit a radiant energy digital signal array. A regenerative feedback device that couples one of the input surface locations to the output surface location in a manner for causing regenerative feedback is also included

Schaefer, D. H.↗

Optical memories in digital computing

High capacity optical memories with relatively-high data-transfer rate and multiport simultaneous access capability may serve as basis for new computer architectures. Several computer structures that might profitably use memories are: a) simultaneous record-access system, b) simultaneously-shared memory computer system, and c) parallel digital processing structure.

Alford, C. O.↗

Some optimal partial-unit-memory codes

A class of time-invariant binary convolutional codes is defined, called partial-unit-memory codes. These codes are optimal in the sense of having maximum free distance for given values of R, k (the number of encoder inputs), and mu (the number of encoder memory cells). Optimal codes are given for rates R = 1/4, 1/3, 1/2, and 2/3, with mu not greater than 4 and k not greater than mu + 3, whenever such a code is better than previously known codes. An infinite class of optimal partial-unit-memory codes is also constructed based on equidistant block codes.

Lauer, G. S.↗

Memory effects in turbulence

Experimental investigations of the wake flow of a hemisphere and cylinder show that such memory effects can be substantial and have a significant influence on momentum transport. Memory effects are described in terms of suitable memory functions.

Hinze, J. O.↗