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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 577 records · Page 32

Efficient Modeling of HIL Multi-Grid System for Scalability & Concurrency in CPS Security Testbed

Cyber-event-triggered power grid blackout compels utility operators to intensify cyber-aware and physics-constrained recovery and restoration process. Recently, coordinated cyber attacks on the Ukrainian grid witnessed such a cyber-event-triggered power system blackout. Various cyber-physical system (CPS) testbeds have attempted with multitude designs to analyze such interdependent events and evaluate remedy measures. However, resource constraints and modular integration designs have been significant barriers while modeling large-scale grid models (scalability) and multi-grid isolated models (concurrency) under a single real-time execution environment for the hardware-in-the-loop (HIL) CPS security testbeds. This paper proposes a meticulous design and effective modeling for simulating large-scale grid models and multi-grid isolated models in a HIL realtime digital simulator environment integrated with industry-grade hardware and software systems. We have used our existing HIL CPS security testbed to demonstrate scalability by the realtime performance of a Texas-2000 bus US synthetic grid model and concurrency by the real-time performance of simultaneous ten IEEE-39 bus grid models and an IEEE-118 bus grid model. The experiments demonstrated significant results by 100% realtime performance with zero overruns, low latency while receiving and executing control signals from SEL Relays via IEC-61850 protocol and low latency while computing and transmitting grid data streams including stability measures via IEEE C37.118 synchrophasor data protocol to SEL Phasor Data Concentrators.

24 POWER TRANSMISSION AND DISTRIBUTION↗

Dynamic Adaptable Asynchronous Progress Model for MPI RMA Multiphase Applications

Casper is a process-based asynchronous progress model for MPI one-sided communication on multi-and many-core architectures. The one-sided communication is not truly one-sided in most MPI implementations: the target process still relies on software progress to complete incoming operations. Casper allows the user to specify an arbitrary number of cores dedicated to background ghost processes and transparently redirects the RMA operations to ghost processes by utilizing the PMPI redirection and MPI-3 shared-memory technologies. Although Casper benefits applications that suffer from lack of asynchronous progress, the operation redirection design might not support complex multiphase applications effectively, which often involve dynamically changing communication density and computing workloads. In this paper, we present an adaptive mechanism in Casper to address the limitation of static asynchronous progress in multiphase applications. For this we exploit two adaptive strategies, a user-guided strategy and a fully transparent and automatic strategy based on self-profiling and prediction, to dynamically reconfigure the asynchronous progress in Casper according to real-time performance characteristics during multiphase execution. We evaluate the adaptive approaches in both microbenchmarks and a real quantum chemistry application suite, NWChem, on the Cray XC30 supercomputer and an Intel Omni-Path cluster.

97 MATHEMATICS AND COMPUTING↗

Characterizing and mitigating coherent errors in a trapped ion quantum processor using hidden inverses

Quantum computing testbeds exhibit high-fidelity quantum control over small collections of qubits, enabling performance of precise, repeatable operations followed by measurements. Currently, these noisy intermediate-scale devices can support a sufficient number of sequential operations prior to decoherence such that near term algorithms can be performed with proximate accuracy (like chemical accuracy for quantum chemistry problems). While the results of these algorithms are imperfect, these imperfections can help bootstrap quantum computer testbed development. Demonstrations of these algorithms over the past few years, coupled with the idea that imperfect algorithm performance can be caused by several dominant noise sources in the quantum processor, which can be measured and calibrated during algorithm execution or in post-processing, has led to the use of noise mitigation to improve typical computational results. Conversely, benchmark algorithms coupled with noise mitigation can help diagnose the nature of the noise, whether systematic or purely random. Here, we outline the use of coherent noise mitigation techniques as a characterization tool in trapped-ion testbeds. We perform model-fitting of the noisy data to determine the noise source based on realistic physics focused noise models and demonstrate that systematic noise amplification coupled with error mitigation schemes provides useful data for noise model deduction. Further, in order to connect lower level noise model details with application specific performance of near term algorithms, we experimentally construct the loss landscape of a variational algorithm under various injected noise sources coupled with error mitigation techniques. This type of connection enables application-aware hardware codesign, in which the most important noise sources in specific applications, like quantum chemistry, become foci of improvement in subsequent hardware generations.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

OSCAR-Mike: Why not ATAK?

The Office of Nuclear Smuggling Detection and Deterrence (NSDD) is evaluating methods to increase the probability that international partners will detect radioactive materials. One proposed method to accomplish this goal is to improve communications within teams operating in challenging environments. The goal of these improvements would be to enable remote monitoring of detection equipment, share data among end users in the field and subject matter experts, and integrate data from radiation detectors with other types of sensors and camera systems. Accomplishing this goal has the potential to improve the capabilities of currently deployed NSDD equipment. During FY 2021, Oak Ridge National Laboratory demonstrated some core and expanded capabilities of the Android Team Awareness Kit (ATAK), a situational awareness application developed by the US Department of Defense, to enable precision targeting, navigation, and data sharing. During FY 2022, Oak Ridge National Laboratory developed software requirements for an NSDD team awareness kit–based system. The requirements were developed by liaising with NSDD management and subject matter experts to determine NSDD’s needs and by reviewing available software and hardware solutions with US Department of Defense team awareness kit program managers and developers and radiation detection equipment vendors.

97 MATHEMATICS AND COMPUTING↗

A practical approach to determine minimal quantum gate durations using amplitude-bounded quantum controls

Here, we present an iterative scheme to estimate the minimal duration in which a quantum gate can be realized while satisfying hardware constraints on the control pulse amplitudes. The scheme performs a sequence of unconstrained numerical optimal control cycles that each minimize the gate fidelity for a given gate duration alongside an additional penalty term for the control pulse amplitudes. After each cycle, the gate duration is adjusted based on the inverse of the resulting maximum control pulse amplitudes by re-scaling the dynamics to a new duration where control pulses satisfy the amplitude constraints. Those scaled controls then serve as an initial guess for the next unconstrained optimal control cycle, using the adjusted gate duration. We provide multiple numerical examples that each demonstrate fast convergence of the scheme toward a gate duration that is close to the quantum speed limit, given the control pulse amplitude bound. The proposed technique is agnostic to the underlying system and control Hamiltonian models, as well as the target unitary gate operation, making the time-scaling iteration an easy to implement and practically useful scheme for reducing the durations of quantum gate operations.

97 MATHEMATICS AND COMPUTING↗

MetaStrider: Architectures for Scalable Memory-centric Reduction of Sparse Data Streams

Reduction is an operation performed on the values of two or more key-value pairs that share the same key. Reduction of sparse data streams finds application in a wide variety of domains such as data and graph analytics, cybersecurity, machine learning, and HPC applications. However, these applications exhibit low locality of reference, rendering traditional architectures and data representations inefficient. This article presents MetaStrider, a significant algorithmic and architectural enhancement to the state-of-the-art, SuperStrider. Furthermore, these enhancements enable a variety of parallel, memory-centric architectures that we propose, resulting in demonstrated performance that scales near-linearly with available memory-level parallelism.

97 MATHEMATICS AND COMPUTING↗

UPC++ as_eager Working Group Draft, Revision 2020.6.2

This draft proposes an extension for a new future-based completion variant that can be more effectively streamlined for RMA and atomic access operations that happen to be satisfied at runtime using purely node-local resources. Many such operations are most efficiently performed synchronously using load/store instructions on shared-memory mappings, where the actual access may only require a few CPU instructions. In such cases we believe it’s critical to minimize the overheads imposed by the UPC++ runtime and completion queues, in order to enable efficient operation on hierarchical node hardware using shared-memory bypass. The new upcxx::{source,operation}_cx::as_eager_future() completion variant accomplishes this goal by relaxing the current restriction that future-returning access operations must return a non-ready future whose completion is deferred until a subsequent explicit invocation of user-level progress. This relaxation allows access operations that are completed synchronously to instead return a ready future, thereby avoiding most or all of the runtime costs associated with deferment of future completion and subsequent mandatory entry into the progress engine. We additionally propose to make this new as_eager_future() completion variant the new default completion for communication operations that currently default to returning a future. This should encourage use of the streamlined variant, and may provide performance improvements to some codes without source changes. A mechanism is proposed to restore the legacy behavior on-demand for codes that might happen to rely on deferred completion for correctness. Finally, we propose a new as_eager_promise() completion variant that extends analogous improvements to promise-based completion, and corresponding changes to the default behavior of as_promise().

97 MATHEMATICS AND COMPUTING↗

Improving Schrödinger Equation Implementations with Gray Code for Adiabatic Quantum Computers

We reformulate the continuous-space Schrödinger equation in terms of spin Hamiltonians. For the kinetic energy operator, the critical concept facilitating the reduction in model complexity is the idea of position encoding. A binary encoding of position produces a spin-1/2 Heisenberg-like model and yields exponential improvement in space complexity when compared to classical computing. Encoding with a binary reflected Gray code (BRGC), and a Hamming-distance-2 Gray code (H2GC) reduces the model complexity down to the 𝑋⁢𝑍 and transverse Ising model, respectively. For 𝐴 qubits BRGC yields 2 𝐴 positions and is reduced to its 2-local form with O⁡(𝐴) ancillary qubits. H2GC yields 2 𝐴/2+1 positions with O⁡(𝐴 2 ) three-local penalty terms. We also identify the bijective mapping between diagonal unitaries and the Walsh series, producing the mapping of any real potential to a series of 𝑘 -local Ising models through the fast Walsh transform. Finally, in a finite volume, we provide some numerical evidence to support the claim that the total time needed for adiabatic evolution is protected by the infrared cutoff of the system. As a result, initial state preparation from a free-field wave function to an interacting system is expected to exhibit polynomial time complexity with volume and constant scaling with respect to lattice discretization for all encodings. For H2GC, if the evolution starts with the transverse Hamiltonian due to hardware restrictions, then penalties are dynamically introduced such that the low-lying spectrum reproduces the energy levels of the Laplacian. The adiabatic evolution of the penalty Hamiltonian is therefore sensitive to the ultraviolet scale. It is expected to exhibit polynomial time complexity with lattice discretization, or exponential time complexity with respect to the number of qubits given a fixed volume.

97 MATHEMATICS AND COMPUTING↗

Lion Cub: Minimizing Communication Overhead in Distributed Lion

Communication overhead is a key challenge in distributed deep learning, especially on slower Ethernet intercon nects, and given current hardware trends, communication is likely to become a major bottleneck. While gradient compression techniques have been explored for SGD and Adam, the Lion optimizer has the distinct advantage that its update vectors are the output of a sign operation, enabling straightforward quantization. However, simply compressing updates for communication and using techniques like majority voting fails to lead to end-to-end speedups due to inefficient communication algorithms and reduced convergence. We analyze three factors critical to distributed learning with Lion: optimizing communication methods, identifying effective quantization methods, and assessing the necessity of momentum synchronization. Our findings show that quantization techniques adapted to Lion and selective momentum synchronization can significantly reduce communication costs while maintaining convergence. We combine these into Lion Cub, which enables up to 5x speedups in end-to-end training compared to Lion. This highlights Lion’s potential as a communication-efficient solution for distributed training.

97 MATHEMATICS AND COMPUTING↗

A domain wall-magnetic tunnel junction artificial synapse with notched geometry for accurate and efficient training of deep neural networks

Inspired by the parallelism and efficiency of the brain, several candidates for artificial synapse devices have been developed for neuromorphic computing, yet a nonlinear and asymmetric synaptic response curve precludes their use for backpropagation, the foundation of modern supervised learning. Spintronic devices—which benefit from high endurance, low power consumption, low latency, and CMOS compatibility—are a promising technology for memory, and domain-wall magnetic tunnel junction (DW-MTJ) devices have been shown to implement synaptic functions such as long-term potentiation and spike-timing dependent plasticity. In this work, we propose a notched DW-MTJ synapse as a candidate for supervised learning. Using micromagnetic simulations at room temperature, we show that notched synapses ensure the non-volatility of the synaptic weight and allow for highly linear, symmetric, and reproducible weight updates using either spin transfer torque (STT) or spin–orbit torque (SOT) mechanisms of DW propagation. We use lookup tables constructed from micromagnetics simulations to model the training of neural networks built with DW-MTJ synapses on both the MNIST and Fashion-MNIST image classification tasks. Accounting for thermal noise and realistic process variations, the DW-MTJ devices achieve classification accuracy close to ideal floating-point updates using both STT and SOT devices at room temperature and at 400 K. Our work establishes the basis for a magnetic artificial synapse that can eventually lead to hardware neural networks with fully spintronic matrix operations implementing machine learning.

42 ENGINEERING↗

TEMPI: An Interposed MPI Library with Canonical Representation of MPI Datatypes [Poster]

TEMPI provides a transparent non-contiguous data-handling layer compatible with various MPIs. MPI Datatypes are a powerful abstraction for allowing an MPI implementation to operate on non-contiguous data. CUDA-aware MPI implementations must also manage transfer of such data between the host system and GPU. The non-unique and recursive nature of MPI datatypes mean that providing fast GPU handling is a challenge. The same noncontiguous pattern may be described in a variety of ways, all of which should be treated equivalently by an implementation. This work introduces a novel technique to do this for strided datatypes. Methods for transferring non-contiguous data between the CPU and GPU depends on the properties of the data layout. This work shows that a simple performance model can accurately select the fastest method. Unfortunately, the combination of MPI software and system hardware available may not provide sufficient performance. The contributions of this work are deployed on OLCF Summit through an interposer library which does not require privileged access to the system to use

97 MATHEMATICS AND COMPUTING↗

A propagation-based fault detection and discrimination method and the optimization of sensor deployment

Industrial processes can be affected by faults having a serious impact on operation when not promptly detected and diagnosed. Here in this paper, a propagation-based fault detection and discrimination(PFDD) method is proposed to develop a strategy for fault diagnosis while in the design phase of a system. The PFDD method constructs the system model using the Integrated System Fault Analysis(ISFA) technique. Based on the system model, the propagation of hardware and software faults are simulated qualitatively. Given the results of the simulation, the process by which a fault propagates can be characterized using the qualitative features of system variables including the deviation of the system variables from their expected values, the variation of the system variables over time, and the order in which each variable is influenced during the propagation of the fault. The strategy by which a fault can be detected and discriminated is defined using those features. The PFDD method supports the detection and discrimination of faults in both steady states and transient states. Based on the PFDD method, the optimization of sensor deployment in a system is discussed. A brute force algorithm is developed to examine the system’s capability at diagnosing faults and the cost of sensor deployment for all possible configurations of sensors. The optimal sensor deployment strategy can be derived accordingly. However, the brute force method is only applicable to small-scale systems due to its high computational cost. A genetic algorithm is used to optimize sensor deployment in large-scale systems. The PFDD and sensor deployment optimization methods are applied to the Experimental Breeder Reactor II (EBR-II) for verification.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

SD-WAN Evaluation Criteria for a Defense Information Systems Network Expeditionary Customer Edge

The Defense Information Systems Agency (DISA) has identified a service provision gap midway between the capacity and capability of a Defense Information Systems Network (DISN) transport Edge Points of Presence (POP) and U.S. Department of Defense (DoD) Enterprise Classified Travel Kit (DECTK). Some deployed force 100-user Tactical Operations Centers are in field locations far removed from the DISN transport core, in challenging environmental conditions with limitations on space, weight, power, and cooling for network equipment. As part of a multi-phase project, Pacific Northwest National Laboratory (PNNL) will gather and analyze requirements, design, develop, prototype, and test a miniaturized and ruggedized DISN Customer Edge POP scaled to support approximately 100 users in a field Tactical Operations Center. An Expeditionary Customer Edge (ECE) will be more suitable for field deployment than a DISN transport Edge POP, using ruggedized hardware and network function virtualization (NFV) to operate in challenging field environmental conditions, plus reduce weight, power, and cooling requirements. A key enabling technology for ECE is Software Defined Wide Area Networking (SD-WAN). This document provides: • A brief overview of SD-WAN use cases and how they apply to ECE • How SD-WAN technology compares to existing networks like DISN that use Optical Transport Networking (OTN) and Multiprotocol Label Switching (MPLS) • SD-WAN functional requirements relevant to ECE • A description of an ECE Virtual Prototype, including simulated wide area network paths and a DISN-representative implementation of MPLS, in Cisco Modeling Labs • Detailed network flow walkthroughs • Evaluation criteria based on ECE-relevant SD-WAN functional requirements Finally, an appendix provides an informal evaluation of Speedify—a commercial retail Virtual Private Network service—against the ECE SD-WAN evaluation criteria.

42 ENGINEERING↗

Experimental Pressure Measurements on Hydropower Turbine Runners

The range of hydrodynamic operating conditions to which the turbine is exposed results in significant pressure fluctuations on both the pressure and suction sides of the blades. Understanding these dynamic pressures has a range of applications. Structurally, the resulting dynamic loads are significant in understanding the design life and maintenance schedule of the bearing, shafts and runner components. The pulsing pressures have also been seen to have a detrimental effect on the surface condition of the blades. Biologically, the pressure gradients and pressure extremes are the primary driver of barotrauma for fish passing through hydroturbines. Improvements in computational fluid dynamics (CFD) can be used to simulate such unsteady pressures in the regions of concern. High frequency model scale and prototype measurements of pressures at the blade are important in the validation of these models. Experimental characterization of pressure fields over hydroturbine blades has been demonstrated by a number of studies which using multiple pressure transducers to map the pressure contours on the runner blades. These have been performed at both model and prototype scales, often to validate computational models of the pressure and flow fields over the blades. This report provides a review of existing studies in which the blade pressure was measured in situ. The report assesses the technology for both model and prototype scale testing. The details of the primary studies in this field are reported and used to inform the types of hardware required for similar experiments based on the Ice Harbor Dam owned by the US Corps of Engineers on the Snake River, WA, USA. Such a study would be used to validate the CFD performed for the BioPA.

13 HYDRO ENERGY↗

Tikiri—Towards a lightweight blockchain for IoT

Internet of Things (IoT) platforms have been deployed in several domains to enhance efficiency of business process and improve productivity. Most IoT platforms comprise of heterogeneous software and hardware components which can potentially introduce security and privacy challenges. Blockchain technology has been proposed as one of the solutions to realize IoT security by leveraging the (a) Immutable ledger, (b) Decentralized architecture and (c) Strong cryptography primitives. However, integrating blockchain platforms with IoT based applications presents several challenges due to lack of (a) acceptable performance on resource-constrained devices, (b) high transaction throughput, (c) keyword-based search and retrieve, (d) transaction back pressure operations, and (e) real-time response. In this paper, we propose a lightweight blockchain platform, “Tikiri”, for resource-constrained IoT devices. Tikiri uses Apache Kafka for the consensus and proposes new blockchain architecture to handle real-time transaction execution on the blockchain. Tikiri is characterized by functional programming and actor-based smart contract platform that realizes concurrent execution of transactions in the blockchain. Tikiri realizes a lightweight and scalable blockchain that can provides performance on the resource-constrained IoT devices.

97 MATHEMATICS AND COMPUTING↗

An Innovative Approach to Bridge a Skill Gap and Grow a Workforce Pipeline: The Computer System, Cluster, and Networking Summer Institute

Sustainable and effective computing infrastructure depends critically on the skills and expertise of domain scientists and of committed and well-trained advanced computing professionals. But, in its ongoing High Performance Computing (HPC) work, Los Alamos National Laboratory noted a persistent shortage of well-prepared applicants, particularly for entry-level cluster administration, file systems administration, and high speed networking positions. Further, based upon recruiting efforts and interactions with universities graduating students in related majors of interest (e.g., computer science (CS)), there has been a long standing skillset gap, as focused training in HPC topics is typically lacking or absent in undergraduate and in even many graduate programs. Given that the effective operation and use of HPC systems requires specialized and often advanced training, that there is a recognized HPC skillset gap, and that there is intense global competition for computing and computational science talent, there is a long-standing and critical need for innovative approaches to help bridge the gap and create a well-prepared, next generation HPC workforce. Our paper places this need in the context of the HPC work and workforce requirements at Los Alamos National Laboratory (LANL) and presents one such innovative program conceived to address the need, bridge the gap, and grow an HPC workforce pipeline at LANL. The Computer System, Cluster, and Networking Summer Institute (CSCNSI) completed its 10th year in 2016. The story of the CSCNSI and its evolution is detailed below with a description of the design of its Boot Camp, and a summary of its success and some key factors that have enabled that success.

97 MATHEMATICS AND COMPUTING↗

Technical report: Design of the accessor

As we have seen the arithmetic power of hardware architectures growing much faster than the memory bandwidth, there is an urgent need to rethink the way we operate, communicate, and store data. A promising strategy for overcoming the “memory wall” is the decoupling of memory precision from arithmetic precision as proposed in Anzt et al. Such a decoupling of memory precision and arithmetic precision requires an “accessor” that handles the conversion between formats (resp. compression of the data) on the fly in registers. Such an accessor has to be general in the sense that it can handle a wide range of floating point formats and compression strategies, and still allows for further extension. At the same time, is important that the use of the accessor is not a burden for the developer. Therefore, it is important to abstract all implementation details from the user, hide the underlying storage format from the user, and make the accessor cross-platform portable. In this document we present the design of an accessor that aims at fulfilling all these requirements.

97 MATHEMATICS AND COMPUTING↗

Compiling Quantum Circuits for Dynamically Field-Programmable Neutral Atoms Array Processors

Dynamically field-programmable qubit arrays (DPQA) have recently emerged as a promising platform for quantum information processing. In DPQA, atomic qubits are selectively loaded into arrays of optical traps that can be reconfigured during the computation itself. Leveraging qubit transport and parallel, entangling quantum operations, different pairs of qubits, even those initially far away, can be entangled at different stages of the quantum program execution. Such reconfigurability and non-local connectivity present new challenges for compilation, especially in the layout synthesis step which places and routes the qubits and schedules the gates. In this paper, we consider a DPQA architecture that contains multiple arrays and supports 2D array movements, representing cutting-edge experimental platforms. Within this architecture, we discretize the state space and formulate layout synthesis as a satisfiability modulo theories problem, which can be solved by existing solvers optimally in terms of circuit depth. For a set of benchmark circuits generated by random graphs with complex connectivities, our compiler OLSQ-DPQA reduces the number of two-qubit entangling gates on small problem instances by 1.7x compared to optimal compilation results on a fixed planar architecture. To further improve scalability and practicality of the method, we introduce a greedy heuristic inspired by the iterative peeling approach in classical integrated circuit routing. Using a hybrid approach that combined the greedy and optimal methods, we demonstrate that our DPQA-based compiled circuits feature reduced scaling overhead compared to a grid fixed architecture, resulting in 5.1X less two-qubit gates for 90 qubit quantum circuits. These methods enable programmable, complex quantum circuits with neutral atom quantum computers, as well as informing both future compilers and future hardware choices.

Physics↗