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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 577 records · Page 32
All sourcesNASA NTRSDOE OSTI
NASA NTRS1987

Computation of subsonic base flow on a vector processor

Two-dimensional subsonic laminar compressible base flow has been studied using numerical solutions of the time-dependent Navier-Stokes equations. These solutions were obtained using an explicit finite-difference scheme which is highly efficient on a vector processor. The organization of the code for a CDC CYBER-205 computer is described. Solutions were obtained for Mach 0.4 and 0.6 flows past a slender blunt-based model at moderately high Reynolds numbers. The flow in the wake is unsteady with periodic shedding of vortices from the trailing edge. The computed shedding frequency was found to increase with increasing Reynolds number.

Rudy, D. H.↗
NASA NTRS1988

Direct finite element solution on an optical laboratory matrix-vector processor

The first optical laboratory system results employing a direct LU decomposition solution of a system of linear algebraic equations are presented for a finite element problem solution. This also represents the first laboratory demonstration of the use of sign-magnitude negative number representation as well as new bit partitioning techniques to increase the accuracy of an optical encoded processor beyond the number of bit channels available.

Casasent, David↗
NASA NTRS1988

The PC/AT compatible computer as a mission control center display processor at Ames-Dryden Flight Research Facility

The NASA Ames-Dryden Flight Research Facility's Western Aeronautical Test Range will assign the flight test data display processing function to Mission Control Centers in order to allow research engineers to flexibly configure their own display-processing system to optimize performance during a flight research mission. This will leave the Telemetry Radar Acquisition and Processing System more time to acquire data. One of the processors chosen to handle the display-processing function is an IBM PC/AT-compatible, rack-mounted PC giving engineers a personalized set of analytic and display tools, developed on the basis of off-the-shelf PC/AT-compatible engineering hardware and software items.

Hammons, Kevin R.↗
NASA NTRS1989

Eight-Bit-Slice GaAs General Processor Circuit

Novel GaAs 8-bit slice enables quick and efficient implementation of variety of fast GaAs digital systems ranging from central processing units of computers to special-purpose processors for communications and signal-processing applications. With GaAs 8-bit slice, designers quickly configure and test hearts of many digital systems that demand fast complex arithmetic, fast and sufficient register storage, efficient multiplexing and routing of data words, and ease of control.

Weissman, John↗
NASA NTRS1989

Integrated Semiconductor/Optical Information Processors

Optical information processors made of integrated three-dimensional devices which include optical, electro-optical, and electronic devices. Integration achieved by combination and extension of advanced semiconductor (integrated-circuit) and integrated-optics technology. In integrated device, spatial light modulator fabricated on surface of chip. Leads to miniaturization of sophisticated optical information-processing systems.

Cheng, Li-Jen↗
NASA NTRS1989

Digital Doppler Processor For Spaceborne Scatterometer

Report describes conceptual digital Doppler processor for NASA scatterometer (NSCAT), advanced version of SEASAT spaceborne radar scatterometer used to measure winds near surface of ocean. In NSCAT design, six antennas illuminate surface of ocean with fanshaped beams.

LONG. D. G.↗
NASA NTRS1987

Advanced data management design for autonomous telerobotic systems in space using spaceborne symbolic processors

The use of computers in autonomous telerobots is reaching the point where advanced distributed processing concepts and techniques are needed to support the functioning of Space Station era telerobotic systems. Three major issues that have impact on the design of data management functions in a telerobot are covered. It also presents a design concept that incorporates an intelligent systems manager (ISM) running on a spaceborne symbolic processor (SSP), to address these issues. The first issue is the support of a system-wide control architecture or control philosophy. Salient features of two candidates are presented that impose constraints on data management design. The second issue is the role of data management in terms of system integration. This referes to providing shared or coordinated data processing and storage resources to a variety of telerobotic components such as vision, mechanical sensing, real-time coordinated multiple limb and end effector control, and planning and reasoning. The third issue is hardware that supports symbolic processing in conjunction with standard data I/O and numeric processing. A SSP that currently is seen to be technologically feasible and is being developed is described and used as a baseline in the design concept.

Goforth, Andre↗
NASA NTRS1986

An Ada implementation for fault detection, isolation and reconfiguration using a fault-tolerant processor

The design and implementation, in Ada, of the Fault Detection, Isolation, and Reconfiguration (FDIR) Manager for the triply redundant, tightly synchronized, Fault Tolerant Processor (FTP) are covered. It also examines the suitability of Ada, in the context of the FTP, for real time control tasks. The operational concepts behind the FTP are explained, and the structure of the resultant Ada code is discussed.

Greeley, Gregory L.↗
NASA NTRS1989

Impact of device level faults in a digital avionic processor

This study describes an experimental analysis of the impact of gate and device-level faults in the processor of a Bendix BDX-930 flight control system. Via mixed mode simulation, faults were injected at the gate (stuck-at) and at the transistor levels and, their propagation through the chip to the output pins was measured. The results show that there is little correspondence between a stuck-at and a device-level fault model, as far as error activity or detection within a functional unit is concerned. In so far as error activity outside the injected unit and at the output pins are concerned, the stuck-at and device models track each other. The stuck-at model, however, overestimates, by over 100 percent, the probability of fault propagation to the output pins. An evaluation of the Mean Error Durations and the Mean Time Between Errors at the output pins shows that the stuck-at model significantly underestimates (by 62 percent) the impact of an internal chip fault on the output pins. Finally, the study also quantifies the impact of device fault by location, both internally and at the output pins.

Suk, Ho Kim↗
NASA NTRS1989

Parallel processors and nonlinear structural dynamics algorithms and software

A nonlinear structural dynamics finite element program was developed to run on a shared memory multiprocessor with pipeline processors. The program, WHAMS, was used as a framework for this work. The program employs explicit time integration and has the capability to handle both the nonlinear material behavior and large displacement response of 3-D structures. The elasto-plastic material model uses an isotropic strain hardening law which is input as a piecewise linear function. Geometric nonlinearities are handled by a corotational formulation in which a coordinate system is embedded at the integration point of each element. Currently, the program has an element library consisting of a beam element based on Euler-Bernoulli theory and trianglar and quadrilateral plate element based on Mindlin theory.

Belytschko, Ted↗
NASA NTRS1984

Feasibility of using the Massively Parallel Processor for large eddy simulations and other Computational Fluid Dynamics applications

The results of an investigation into the feasibility of using the MPP for direct and large eddy simulations of the Navier-Stokes equations is presented. A major part of this study was devoted to the implementation of two of the standard numerical algorithms for CFD. These implementations were not run on the Massively Parallel Processor (MPP) since the machine delivered to NASA Goddard does not have sufficient capacity. Instead, a detailed implementation plan was designed and from these were derived estimates of the time and space requirements of the algorithms on a suitably configured MPP. In addition, other issues related to the practical implementation of these algorithms on an MPP-like architecture were considered; namely, adaptive grid generation, zonal boundary conditions, the table lookup problem, and the software interface. Performance estimates show that the architectural components of the MPP, the Staging Memory and the Array Unit, appear to be well suited to the numerical algorithms of CFD. This combined with the prospect of building a faster and larger MMP-like machine holds the promise of achieving sustained gigaflop rates that are required for the numerical simulations in CFD.

Bruno, John↗
NASA NTRS1988

Programmable pipelined image processor

A pipelined image processor selectively interconnects modules in a column of a two-dimensional array to modules of the next column of the array of modules 1,1 through M,N, where M is the number of modules in one dimension and N is the number of modules in the other direction. Each module includes two input selectors for A and B inputs, two convolvers, a binary function operator, a neighborhood comparison operator which produces an A output and an output selector which may select as a B output the output of any one of the components in the module, including the A output of the neighborhood comparison operator. Each module may be connected to as many as eight modules in the next column, preferably with the majority always in a different row that is up (or down) in the array for a generally spiral data path around the torus thus formed. The binary function operator is implemented as a look-up table addressed by the most significant 8 bits of each 12-bit argument. The table output includes a function value and the slopes for interpolation of the two arguments by multiplying the 4 least significant bits in multipliers and adding the products to the function value through adders.

Donald B Gennery↗
NASA NTRS1987

The architecture of a video image processor for the space station

The architecture of a video image processor for space station applications is described. The architecture was derived from a study of the requirements of algorithms that are necessary to produce the desired functionality of many of these applications. Architectural options were selected based on a simulation of the execution of these algorithms on various architectural organizations. A great deal of emphasis was placed on the ability of the system to evolve and grow over the lifetime of the space station. The result is a hierarchical parallel architecture that is characterized by high level language programmability, modularity, extensibility and can meet the required performance goals.

Yalamanchili, S.↗
NASA NTRS1989

Assessment of SPAR elements and formulation of some basic 2-D and 3-D elements for use with testbed generic element processor

The initial Computational Structural Mechanics (CSM) Testbed was based on Level 13 of the SPAR finite element computer program. Until recently, the element library of the Testbed has been limited to those elements in Level 13 of SPAR. The development of a generic element processor has enabled element researchers to develop, implement and assess element formulations with relative ease. An assessment of new elements as well as the existing SPAR Level 13 elements has revealed some definite shortcomings with the SPAR Level 13 2-D and 3-D elements. The SPAR S81 solid element does not pass the patch test problem proposed by MacNeal-Harder. These deficiencies are identified here. The 2-D elements, however, seem to perform well taking into account the limitations imposed by the theory used to formulate them, (i.e., thin plates only). Common deficiencies of the 2-D and 3-D elements in SPAR have to do with their adaptability to the nonlinear analysis utilities developed by Lockheed Palo Alto Research Lab. Also, the EFIL format of the SPAR element data does not conform to the standard format of the Testbed.

Aminpour, Mohammad A.↗
NASA NTRS1988

Impact of device level faults in a digital avionic processor

This paper describes an experimental analysis of the impact of gate and device-level faults in the processor of a flight control system. Via mixed mode simulation faults were injected both at the gate (stuck-at) and at the transistor levels, and their propagation through the chip to the output pins was measured. The results show that there is little correspondence between a stuck-at and a device-level fault model insofar as error activity or detection within a functional unit is concerned. Insofar as error activity outside the injected unit and at the output pins are concerned, the stuck-at and device models track each other, although the stuck-at model overestimates, by over one hundred percent, the probability of fault propagation to the output pins. The stuck-at model significantly underestimates the impact of an internal chip fault on the output pins.

Kim, S.↗
NASA NTRS1988

General linear codes for fault-tolerant matrix operations on processor arrays

Various checksum codes have been suggested for fault-tolerant matrix computations on processor arrays. Use of these codes is limited due to potential roundoff and overflow errors. Numerical errors may also be misconstrued as errors due to physical faults in the system. In this a set of linear codes is identified which can be used for fault-tolerant matrix operations such as matrix addition, multiplication, transposition, and LU-decomposition, with minimum numerical error. Encoding schemes are given for some of the example codes which fall under the general set of codes. With the help of experiments, a rule of thumb for the selection of a particular code for a given application is derived.

Nair, V. S. S.↗
NASA NTRS1990

Assignment Of Finite Elements To Parallel Processors

Elements assigned approximately optimally to subdomains. Mapping algorithm based on simulated-annealing concept used to minimize approximate time required to perform finite-element computation on hypercube computer or other network of parallel data processors. Mapping algorithm needed when shape of domain complicated or otherwise not obvious what allocation of elements to subdomains minimizes cost of computation.

Salama, Moktar A.↗
NASA NTRS1990

Processor Would Find Best Paths On Map

Proposed very-large-scale integrated (VLSI) circuit image-data processor finds path of least cost from specified origin to any destination on map. Cost of traversal assigned to each picture element of map. Path of least cost from originating picture element to every other picture element computed as path that preserves as much as possible of signal transmitted by originating picture element. Dedicated microprocessor at each picture element stores cost of traversal and performs its share of computations of paths of least cost. Least-cost-path problem occurs in research, military maneuvers, and in planning routes of vehicles.

Eberhardt, Silvio P.↗