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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 577 records · Page 32
All sourcesNASA NTRSDOE OSTI
NASA NTRS1990

Study on fault-tolerant processors for advanced launch system

Issues related to the reliability of a redundant system with large main memory are addressed. The Fault-Tolerant Processor (FTP) for the Advanced Launch System (ALS) is used as a basis for the presentation. When the system is free of latent faults, the probability of system crash due to multiple channel faults is shown to be insignificant even when voting on the outputs of computing channels is infrequent. Using channel error maskers (CEMs) is shown to improve reliability more effectively than increasing redundancy or the number of channels for applications with long mission times. Even without using a voter, most memory errors can be immediately corrected by those CEMs implemented with conventional coding techniques. In addition to their ability to enhance system reliability, CEMs (with a very low hardware overhead) can be used to dramatically reduce not only the need of memory realignment, but also the time required to realign channel memories in case, albeit rare, such a need arises. Using CEMs, two different schemes were developed to solve the memory realignment problem. In both schemes, most errors are corrected by CEMs, and the remaining errors are masked by a voter.

Shin, Kang G.↗
NASA NTRS1991

Frequency domain laser velocimeter signal processor

A new scheme for processing signals from laser velocimeter systems is described. The technique utilizes the capabilities of advanced digital electronics to yield a signal processor capable of operating in the frequency domain maximizing the information obtainable from each signal burst. This allows a sophisticated approach to signal detection and processing, with a more accurate measurement of the chirp frequency resulting in an eight-fold increase in measurable signals over the present high-speed burst counter technology. Further, the required signal-to-noise ratio is reduced by a factor of 32, allowing measurements within boundary layers of wind tunnel models. Measurement accuracy is also increased up to a factor of five.

Meyers, James F.↗
NASA NTRS1989

Data compression for Eos on-board SAR processor

A lightweight, low-power, real-time data compressor design for the Earth Observing System (Eos) onboard synthetic aperture radar (SAR) processor is presented. The implementation is based on VLSI design of a pipelined binary tree-searched vector quantizer (VQ), utilizing space-qualifiable 1.25-micron CMOS technology. The implementation exploits VLSI system design principles such as the modularity, regular data flow, simple interconnection, localized communication, simple global control, and parallel/pipelined processing. The overall system requires 30 chips with only one VLSI processing element design. The total weight is about 1.2 lbs, with an estimated power dissipation of approximately 4 watts operating at the maximum input data rate. The projected throughput rate exceeds 5 MHz.

Chang, C. Y.↗
NASA NTRS1990

Fault-tolerant parallel processors for avionics with reduced maintenance

Architectural issues and approaches for implementing fault-tolerant parallel processors in avionics systems and other dedicated applications requiring high levels of dependability are discussed. For these systems it is desirable to provide both a high degree of fault tolerance and a system that can operate for extended periods of time without external maintenance. With current technology it is possible to operate dependably for months between maintenance events. The longer-term goal should be maintenance-free operation (a computer that outlasts its host system). It is argued that new high-density packaging techniques may make this type of long-life fault-tolerant design an attractive choice in controlling the life-cycle costs of the next generation of systems.

Rennels, David A.↗
NASA NTRS1992

Acousto-Optical/Electronic Processor For SAR

Lightweight, compact, low-power apparatus processes synthetic-aperture-radar (SAR) returns in real time, providing imagery aboard moving aircraft or spacecraft platform. Processor includes optical and electronic subsystems that, together, resolve range and azimuth coordinates of radar targets by combination of spatial and temporal integrations.

Bicknell, T. J.↗
NASA NTRS1992

Front-End Processor For Metrology-Information System

Front-end processor for NASA Metrology Information System (NMIS) is real-time relational data-base computer system designed to distribute processing for NMIS mainframe system or run as stand-alone local-area-network data-base system. System used in large calibration laboratories for work control and to maintain records of calibration, repair, costs, manpower usage, traceability, and other pertinent facts about instruments supported by laboratories. Provides enhancements to existing NASA Metrology Information System and batches upload to minimize mainframe I/O at times of heavy usage.

Muse, Walter S.↗
NASA NTRS1992

Hypercluster Parallel Processor

Hypercluster computer system includes multiple digital processors, operation of which coordinated through specialized software. Configurable according to various parallel-computing architectures of shared-memory or distributed-memory class, including scalar computer, vector computer, reduced-instruction-set computer, and complex-instruction-set computer. Designed as flexible, relatively inexpensive system that provides single programming and operating environment within which one can investigate effects of various parallel-computing architectures and combinations on performance in solution of complicated problems like those of three-dimensional flows in turbomachines. Hypercluster software and architectural concepts are in public domain.

Blech, Richard A.↗
NASA NTRS1990

JPL's Real-Time Weather Processor project (RWP) metrics and observations at system completion

As an integral part of the overall upgraded National Airspace System (NAS), the objective of the Real-Time Weather Processor (RWP) project is to improve the quality of weather information and the timeliness of its dissemination to system users. To accomplish this, an RWP will be installed in each of the Center Weather Service Units (CWSUs), located in 21 of the 23 Air Route Traffic Control Centers (ARTCCs). The RWP System is a prototype system. It is planned that the software will be GFE and that production hardware will be acquired via industry competitive procurement. The ARTCC is a facility established to provide air traffic control service to aircraft operating on Instrument Flight Rules (IFR) flight plans within controlled airspace, principally during the en route phase of the flight. Covered here are requirement metrics, Software Problem Failure Reports (SPFRs), and Ada portability metrics and observations.

Loesh, Robert E.↗
NASA NTRS1991

Autonomous space processor for orbital debris

The development of an Autonomous Space Processor for Orbital Debris (ASPOD) was the goal. The nature of this craft, which will process, in situ, orbital debris using resources available in low Earth orbit (LEO) is explained. The serious problem of orbital debris is briefly described and the nature of the large debris population is outlined. The focus was on the development of a versatile robotic manipulator to augment an existing robotic arm, the incorporation of remote operation of the robotic arms, and the formulation of optimal (time and energy) trajectory planning algorithms for coordinated robotic arms. The mechanical design of the new arm is described in detail. The work envelope is explained showing the flexibility of the new design. Several telemetry communication systems are described which will enable the remote operation of the robotic arms. The trajectory planning algorithms are fully developed for both the time optimal and energy optimal problems. The time optimal problem is solved using phase plane techniques while the energy optimal problem is solved using dynamic programming.

Ramohalli, Kumar↗
NASA NTRS1992

Distributed digital signal processors for multi-body flexible structures

Multi-body flexible structures, such as those currently under investigation in spacecraft design, are large scale (high-order) dimensional systems. Controlling and filtering such structures is a computationally complex problem. This is particularly important when many sensors and actuators are located along the structure and need to be processed in real time. This report summarizes research activity focused on solving the signal processing (that is, information processing) issues of multi-body structures. A distributed architecture is developed in which single loop processors are employed for local filtering and control. By implementing such a philosophy with an embedded controller configuration, a supervising controller may be used to process global data and make global decisions as the local devices are processing local information. A hardware testbed, a position controller system for a servo motor, is employed to illustrate the capabilities of the embedded controller structure. Several filtering and control structures which can be modeled as rational functions can be implemented on the system developed in this research effort. Thus the results of the study provide a support tool for many Control/Structure Interaction (CSI) NASA testbeds such as the Evolutionary model and the nine-bay truss structure.

Lee, Gordon K. F.↗
NASA NTRS1991

NASA/DOD Aerospace Knowledge Diffusion Research Project. Paper 20: Engineers as information processors: A survey of US aerospace engineering faculty and students

U.S. aerospace engineering faculty and students were surveyed as part of the NASA/DoD Aerospace Knowledge Research Project. Faculty and students were viewed as information processors within a conceptual framework of information seeking behavior. Questionnaires were received from 275 faculty members and 640 students, which were used to determine: (1) use and importance of information sources; (2) use of specific print sources and electronic data bases; (3) use of information technology; and (4) the influence of instruction on the use of information sources and the products of faculty and students. Little evidence was found to support the belief that instruction in library or engineering information use has significant impact either on broadening the frequency or range of information products and sources used by U.S. aerospace engineering students.

Holland, Maurita Peterson↗
NASA NTRS1991

A Markov model reduction technique for fault tolerant processor reliability analysis

A fault tolerant processor (FTP) plays a key role in many high performance, safety-critical control system applications. Realistic modeling of an FTP is crucial to gaining a high degree of confidence in the reliability and safety analysis of such a system. While fidelity is clearly a major consideration, a practical model must also be kept to a moderate size to allow its incorporation into the overall system model. This paper presents a systematic reduction technique that starts from a complex, detailed model of a triple, redundant FTP and produces a low order approximation of very high accuracy. The existence of two distinct time scales represents the key to the success of the technique. No eigenvalue solution or coordinate transformation are needed. The reduced model captures all the important features of the detailed model, is amenable to an analytical solution and provides insight into the reconfiguration behavior of an FTP.

Schor, Andrei L.↗
NASA NTRS1991

Computer simulation of water reclamation processors

The development of detailed simulation models of water reclamation processors based on the ASPEN PLUS simulation program is discussed. Individual models have been developed for vapor compression distillation, vapor phase catalytic ammonia removal, and supercritical water oxidation. These models are used for predicting the process behavior. Particular attention is given to methodology which is used to complete this work, and the insights which are gained by this type of model development.

Fisher, John W.↗
NASA NTRS1993

Biological Information Signal Processor

Biological Information Signal Processor (BISP) is computing system analyzing data on deoxyribonucleic acid (DNA) sequences for molecular genetic analysis. Includes coprocessors, specialized microprocessors complementing present and future computers by performing rapidly most-time-consuming DNA-sequence-analyzing functions, establishing relationships (alignments) between both global sequences and defining patterns in multiple sequences. Also includes state-of-art software and data-base systems on both conventional and parallel computer systems to augment analytical abilities of developmental coprocessors.

Chow, Edward T.↗
NASA NTRS1993

Computing Flow Transition On Parallel Processors

Parallel algorithm developed on multiple-microprocessor computer. Program initiated to develop computer codes capable of directly simulating and mathematically modeling transition process at mach numbers ranging from subsonic to hypersonic. Parallel computers potentially offer reduction of processing time; processing time inversely proportional to number of available processors.

Bokhari, S.↗
NASA NTRS1992

NASA experimental airborne doppler radar and real time processor for wind shear detection

The topics are presented in viewgraph form and include the following: experimental radar system capabilities; an experimental radar system block diagram; wind shear radar signal and data processor (WRSDP); WRSDP hardware architecture; WRSDP system design goals; DSP software development tools; OS-9 software development tools; WRSDP digital signal processing; WRSDP display operational modes; WRSDP division of functions; structure of WRSDP signal and data processing algorithms; and the wind shear radar flight experiment.

Schaffner, Philip H.↗
NASA NTRS1993

Neural-network dedicated processor for solving competitive assignment problems

A neural-network processor for solving first-order competitive assignment problems consists of a matrix of N x M processing units, each of which corresponds to the pairing of a first number of elements of (R sub i) with a second number of elements (C sub j), wherein limits of the first number are programmed in row control superneurons, and limits of the second number are programmed in column superneurons as MIN and MAX values. The cost (weight) W sub ij of the pairings is programmed separately into each PU. For each row and column of PU's, a dedicated constraint superneuron insures that the number of active neurons within the associated row or column fall within a specified range. Annealing is provided by gradually increasing the PU gain for each row and column or increasing positive feedback to each PU, the latter being effective to increase hysteresis of each PU or by combining both of these techniques.

Eberhardt, Silvio P.↗
NASA NTRS1993

Periodic Application of Concurrent Error Detection in Processor Array Architectures

Processor arrays can provide an attractive architecture for some applications. Featuring modularity, regular interconnection and high parallelism, such arrays are well-suited for VLSI/WSI implementations, and applications with high computational requirements, such as real-time signal processing. Preserving the integrity of results can be of paramount importance for certain applications. In these cases, fault tolerance should be used to ensure reliable delivery of a system's service. One aspect of fault tolerance is the detection of errors caused by faults. Concurrent error detection (CED) techniques offer the advantage that transient and intermittent faults may be detected with greater probability than with off-line diagnostic tests. Applying time-redundant CED techniques can reduce hardware redundancy costs. However, most time-redundant CED techniques degrade a system's performance.

Chen, Paul Peichuan↗