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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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All sourcesNASA NTRSDOE OSTI
NASA NTRS2018

Development of High Power Hall Thruster Systems to Enable the NASA Exploration Vision

The next phase of space exploration missions requires high power Solar Electric Propulsion (SEP) systems for large-scale science missions and cargo transportation. Development is underway at Aerojet Rocketdyne on Hall thruster systems that are intended to bracket the needs of future NASA SEP missions in support of space exploration. The Advanced Electric Propulsion System (AEPS) program is developing and qualifying a 13.3kW Hall thruster system to be demonstrated on the Power and Propulsion Element (PPE), which is intended to be the first element of a Lunar Outpost Platform - Gateway (LOP-G). The NextSTEP program is integrating a nested Hall thruster into a 100kW system and testing it for 100 hours. These two programs will provide a path to efficient in-space propulsion that will allow NASA to transfer the large amounts of cargo that is needed to support human missions - first to the moon and then on to Mars. The Advanced Electric Propulsion System (AEPS) program is completing development, qualification and delivery of five flight 13.3kW EP systems to NASA. The flight AEPS system includes a magnetically shielded long-life Hall thruster, Power Processing Unit (PPU) and a Xenon Flow Controller (XFC). The Hall thruster, developed and demonstrated by NASA, operates at input powers up to 12.5kW while providing a specific impulse over an estimated 2800s at an input voltage of 600V. The power processor is designed to accommodate an input voltage range of 95-140V, consistent with operation beyond the orbit of Mars. The integrated system input power is continuously throttleable between 3 and 13.3kW. Component level testing of the EP String has begun with prototype hardware. The NextSTEP program is developing a 100kW Electric Propulsion (EP) system using a nested Hall thruster designed for powers up to 250kW, a modular power processor and a modular mass flow controller. While the program objective is to operate the integrated EP system continuously at 100kW for 100hrs to demonstrate thermal stability and support the development of system life time models, it builds on decades of experience with long-life Hall thrusters and the design is evolvable to a capability of 250kW. Design upgrades that demonstrate the 100kW EP system have been completed and tested. Aerojet Rocketdyne (AR) is excited to support NASA as it extends human reach into deep space and believes that these programs will provide the propulsion to make such missions affordable and sustainable. These systems provide NASA with a range of options to power its deep space transport vehicles. This paper presents the mission requirements for supporting the NASA exploration vision, as well as the status for the high power Hall thruster systems in development.

Jackson, Jerry↗
NASA NTRS2018

Development of High Power Hall Thruster Systems to Enable the NASA Exploration Vision

The next phase of space exploration missions requires high power Solar Electric Propulsion (SEP) systems for large-scale science missions and cargo transportation. Development is underway at Aerojet Rocketdyne on Hall thruster systems that are intended to bracket the needs of future NASA SEP missions in support of space exploration. The Advanced Electric Propulsion System (AEPS) program is developing and qualifying a 13.3kW Hall thruster system to be demonstrated on the Power and Propulsion Element (PPE), which is intended to be the first element of a Lunar Outpost Platform - Gateway (LOP-G). The NextSTEP program is integrating a nested Hall thruster into a 100 kW system and testing it for 100 hours. These two programs will provide a path to efficient in-space propulsion that will allow NASA to transfer the large amounts of cargo that is needed to support human missions - first to the moon and then on to Mars. The Advanced Electric Propulsion System (AEPS) program is completing development, qualification and delivery of five flight 13.3kW EP systems to NASA. The flight AEPS system includes a magnetically shielded long-life Hall thruster, Power Processing Unit (PPU) and a Xenon Flow Controller (XFC). The Hall thruster, developed and demonstrated by NASA, operates at input powers up to 12.5 kW while providing a specific impulse over an estimated 2800s at an input voltage of 600V. The power processor is designed to accommodate an input voltage range of 95-140V, consistent with operation beyond the orbit of Mars. The integrated system input power is continuously throttleable between 3 and 13.3kW. Component level testing of the EP String has begun with prototype hardware. The NextSTEP program is developing a 100kW Electric Propulsion (EP) system using a nested Hall thruster designed for powers up to 250kW, a modular power processor and a modular mass flow controller. While the program objective is to operate the integrated EP system continuously at 100kW for 100 hours to demonstrate thermal stability and support the development of system life time models, it builds on decades of experience with long-life Hall thrusters and the design is evolvable to a capability of 250kW. Design upgrades that demonstrate the 100kW EP system have been completed and tested. Aerojet Rocketdyne is excited to support NASA as it extends human reach into deep space and believes that these programs will provide the propulsion to make such missions affordable and sustainable. These systems provide NASA with a range of options to power its deep space transport vehicles. This paper presents the mission requirements for supporting the NASA exploration vision, as well as the status for the high power Hall thruster systems in development.

Jackson, Jerry↗
NASA NTRS2010

Ethernet-Enabled Power and Communication Module for Embedded Processors

The power and communications module is a printed circuit board (PCB) that has the capability of providing power to an embedded processor and converting Ethernet packets into serial data to transfer to the processor. The purpose of the new design is to address the shortcomings of previous designs, including limited bandwidth and program memory, lack of control over packet processing, and lack of support for timing synchronization. The new design of the module creates a robust serial-to-Ethernet conversion that is powered using the existing Ethernet cable. This innovation has a small form factor that allows it to power processors and transducers with minimal space requirements.

Perotti, Jose↗
DOE OSTI2016

An efficient and portable SIMD algorithm for charge/current deposition in Particle-In-Cell codes

In current computer architectures, data movement (from die to network) is by far the most energy consuming part of an algorithm (≈20pJ/word on-die to ≈10,000 pJ/word on the network). To increase memory locality at the hardware level and reduce energy consumption related to data movement, future exascale computers tend to use many-core processors on each compute nodes that will have a reduced clock speed to allow for efficient cooling. To compensate for frequency decrease, machine vendors are making use of long SIMD instruction registers that are able to process multiple data with one arithmetic operator in one clock cycle. SIMD register length is expected to double every four years. As a consequence, Particle-In-Cell (PIC) codes will have to achieve good vectorization to fully take advantage of these upcoming architectures. In this paper, we present a new algorithm that allows for efficient and portable SIMD vectorization of current/charge deposition routines that are, along with the field gathering routines, among the most time consuming parts of the PIC algorithm. Our new algorithm uses a particular data structure that takes into account memory alignment constraints and avoids gather/scat;ter instructions that can significantly affect vectorization performances on current CPUs. The new algorithm was successfully implemented in the 3D skeleton PIC code PICSAR and tested on Haswell Xeon processors (AVX2-256 bits wide data registers). Results show a factor of ×2 to ×2.5 speed-up in double precision for particle shape factor of orders 1–3. The new algorithm can be applied as is on future KNL (Knights Landing) architectures that will include AVX-512 instruction sets with 512 bits register lengths (8 doubles/16 singles). Program summary Program Title: vec_deposition Program Files doi:http://dx.doi.org/10.17632/nh77fv9k8c.1 Licensing provisions: BSD 3-Clause Programming language: Fortran 90 External routines/libraries: OpenMP > 4.0 Nature of problem: Exascale architectures will have many-core processors per node with long vector data registers capable of performing one single instruction on multiple data during one clock cycle. Data register lengths are expected to double every four years and this pushes for new portable solutions for efficiently vectorizing Particle-In-Cell codes on these future many-core architectures. One of the main hotspot routines of the PIC algorithm is the current/charge deposition for which there is no efficient and portable vector algorithm. Solution method: Here we provide an efficient and portable vector algorithm of current/charge deposition routines that uses a new data structure, which significantly reduces gather/scatter operations. Vectorization is controlled using OpenMP 4.0 compiler directives for vectorization which ensures portability across different architectures. Restrictions: Here we do not provide the full PIC algorithm with an executable but only vector routines for current/charge deposition. These scalar/vector routines can be used as library routines in your 3D Particle-In-Cell code. However, to get the best performances out of vector routines you have to satisfy the two following requirements: (1) Your code should implement particle tiling (as explained in the manuscript) to allow for maximized cache reuse and reduce memory accesses that can hinder vector performances. The routines can be used directly on each particle tile. (2) You should compile your code with a Fortran 90 compiler (e.g Intel, gnu or cray) and provide proper alignment flags and compiler alignment directives (more details in README file).

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1979

NASF transposition network: A computing network for unscrambling p-ordered vectors

The viewpoints of design, programming, and application of the transportation network (TN) is presented. The TN is a programmable combinational logic network that connects 521 memory modules to 512 processors. The unscrambling of p-ordered vectors to 1-ordered vectors in one cycle is described. The TN design is based upon the concept of cyclic groups from abstract algebra and primitive roots and indices from number theory. The programming of the TN is very simple, requiring only 20 bits: 10 bits for offset control and 10 bits for barrel switch shift control. This simple control is executed by the control unit (CU), not the processors. Any memory access by a processor must be coordinated with the CU and wait for all other processors to come to a synchronization point. These wait and synchronization events can be a degradation in performance to a computation. The TN application is for multidimensional data manipulation, matrix processing, and data sorting, and can also perform a perfect shuffle. Unlike other more complicated and powerful permutation networks, the TN cannot, if possible at all, unscramble non-p-ordered vectors in one cycle.

Lim, R. S.↗
DOE OSTI2019

Visualizing Hierarchical Performance Profiles of Parallel Codes Using CallFlow

Calling context trees (CCTs) couple performance metrics with call paths, helping understand the execution and performance of parallel programs. To identify performance bottlenecks, programmers and performance analysts visually explore CCTs to form and validate hypotheses regarding degraded performance. However, due to the complexity of parallel programs, existing visual representations do not scale to applications running on a large number of processors. In this work, we present CallFlow, an interactive visual analysis tool that provides a high-level overview of CCTs together with semantic refinement operations to progressively explore CCTs. Using a flow-based metaphor, we visualize a CCT by treating execution time as a resource spent during the call chain, and demonstrate the effectiveness of our design with case studies on large-scale, production simulation codes.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1986

FTMP (Fault Tolerant Multiprocessor) programmer's manual

The Fault Tolerant Multiprocessor (FTMP) computer system was constructed using the Rockwell/Collins CAPS-6 processor. It is installed in the Avionics Integration Research Laboratory (AIRLAB) of NASA Langley Research Center. It is hosted by AIRLAB's System 10, a VAX 11/750, for the loading of programs and experimentation. The FTMP support software includes a cross compiler for a high level language called Automated Engineering Design (AED) System, an assembler for the CAPS-6 processor assembly language, and a linker. Access to this support software is through an automated remote access facility on the VAX which relieves the user of the burden of learning how to use the IBM 4381. This manual is a compilation of information about the FTMP support environment. It explains the FTMP software and support environment along many of the finer points of running programs on FTMP. This will be helpful to the researcher trying to run an experiment on FTMP and even to the person probing FTMP with fault injections. Much of the information in this manual can be found in other sources; we are only attempting to bring together the basic points in a single source. If the reader should need points clarified, there is a list of support documentation in the back of this manual.

Feather, F. E.↗
NASA NTRS2010

Systems, methods, and products for graphically illustrating and controlling a droplet actuator

Systems for controlling a droplet microactuator are provided. According to one embodiment, a system is provided and includes a controller, a droplet microactuator electronically coupled to the controller, and a display device displaying a user interface electronically coupled to the controller, wherein the system is programmed and configured to permit a user to effect a droplet manipulation by interacting with the user interface. According to another embodiment, a system is provided and includes a processor, a display device electronically coupled to the processor, and software loaded and/or stored in a storage device electronically coupled to the controller, a memory device electronically coupled to the controller, and/or the controller and programmed to display an interactive map of a droplet microactuator. According to yet another embodiment, a system is provided and includes a controller, a droplet microactuator electronically coupled to the controller, a display device displaying a user interface electronically coupled to the controller, and software for executing a protocol loaded and/or stored in a storage device electronically coupled to the controller, a memory device electronically coupled to the controller, and/or the controller.

Paik, Philip Y.↗
NASA NTRS1975

Dispersion analysis techniques within the space vehicle dynamics simulation program

The Space Vehicle Dynamics Simulation (SVDS) program was evaluated as a dispersion analysis tool. The Linear Error Analysis (LEA) post processor was examined in detail and simulation techniques relative to conducting a dispersion analysis using the SVDS were considered. The LEA processor is a tool for correlating trajectory dispersion data developed by simulating 3 sigma uncertainties as single error source cases. The processor combines trajectory and performance deviations by a root-sum-square (RSS process) and develops a covariance matrix for the deviations. Results are used in dispersion analyses for the baseline reference and orbiter flight test missions. As a part of this study, LEA results were verified as follows: (A) Hand calculating the RSS data and the elements of the covariance matrix for comparison with the LEA processor computed data. (B) Comparing results with previous error analyses. The LEA comparisons and verification are made at main engine cutoff (MECO).

Snow, L. S.↗
NASA NTRS1982

A Loran-C prototype navigation receiver for general aviation

The design, fabrication and evaluation of a prototype Loran-C receiver is described. Hardware, and microcomputer programming for addition of area navigation capability are reported. The receiver is an envelope processor, offering simplicity of RF processor circuitry.

Lilley, R. W.↗
NASA NTRS1985

Automatic Dynamic Aircraft Modeler (ADAM) for the Computer Program NASTRAN

Large general purpose finite element programs require users to develop large quantities of input data. General purpose pre-processors are used to decrease the effort required to develop structural models. Further reduction of effort can be achieved by specific application pre-processors. Automatic Dynamic Aircraft Modeler (ADAM) is one such application specific pre-processor. General purpose pre-processors use points, lines and surfaces to describe geometric shapes. Specifying that ADAM is used only for aircraft structures allows generic structural sections, wing boxes and bodies, to be pre-defined. Hence with only gross dimensions, thicknesses, material properties and pre-defined boundary conditions a complete model of an aircraft can be created.

Griffis, H.↗
NASA NTRS1985

Algorithms and programming tools for image processing on the MPP

Topics addressed include: data mapping and rotational algorithms for the Massively Parallel Processor (MPP); Parallel Pascal language; documentation for the Parallel Pascal Development system; and a description of the Parallel Pascal language used on the MPP.

Reeves, A. P.↗
NASA NTRS1986

Dynamic remapping decisions in multi-phase parallel computations

The effectiveness of any given mapping of workload to processors in a parallel system is dependent on the stochastic behavior of the workload. Program behavior is often characterized by a sequence of phases, with phase changes occurring unpredictably. During a phase, the behavior is fairly stable, but may become quite different during the next phase. Thus a workload assignment generated for one phase may hinder performance during the next phase. We consider the problem of deciding whether to remap a paralled computation in the face of uncertainty in remapping's utility. Fundamentally, it is necessary to balance the expected remapping performance gain against the delay cost of remapping. This paper treats this problem formally by constructing a probabilistic model of a computation with at most two phases. We use stochastic dynamic programming to show that the remapping decision policy which minimizes the expected running time of the computation has an extremely simple structure: the optimal decision at any step is followed by comparing the probability of remapping gain against a threshold. This theoretical result stresses the importance of detecting a phase change, and assessing the possibility of gain from remapping. We also empirically study the sensitivity of optimal performance to imprecise decision threshold. Under a wide range of model parameter values, we find nearly optimal performance if remapping is chosen simply when the gain probability is high. These results strongly suggest that except in extreme cases, the remapping decision problem is essentially that of dynamically determining whether gain can be achieved by remapping after a phase change; precise quantification of the decision model parameters is not necessary.

Nicol, D. M.↗
NASA NTRS1993

Portable computer system architecture for the Space Station Freedom program

This paper outlines various mission requirements and technical approaches that support the potential use of portable computers in several defined activities within the Space Station Freedom (SSF) program. Specifically, the use of portable computers as consoles for both spacecraft control and payload applications is presented. Various issues and proposed solutions regarding the incorporation of portable computers within the program are presented. The primary issues presented regard architecture (standard interface for expansion, advanced processors and displays), integration (methods of high-speed data communication, peripheral interfaces, and interconnectivity within various support networks), and evolution (wireless communications and multimedia data interface methods).

Alena, Richard↗
NASA NTRS1998

Self-Calibrating and Remote Programmable Signal Conditioning Amplifier System and Method

A self-calibrating, remote programmable signal conditioning amplifier system employs information read from a memory attached to a measurement transducer for automatic calibration. The signal conditioning amplifier is self-calibrated on a continuous basis through use of a dual input path arrangement, with each path containing a multiplexer and a programmable amplifier. A digital signal processor controls operation of the system such that a transducer signal is applied to one of the input paths, while one or more calibration signals are applied to the second input path. Once the second path is calibrated, the digital signal processor switches the transducer signal to the second path. and then calibrates the first path. This process is continually repeated so that each path is calibrated on an essentially continuous basis. Dual output paths are also employed which are calibrated in the same manner. The digital signal processor also allows the implementation of a variety of digital filters which are either programmed into the system or downloaded by an operator, and performs up to eighth order linearization.

Medelius, Pedro J.↗
NASA NTRS1995

Navier-Stokes Aerodynamic Simulation of the V-22 Osprey on the Intel Paragon MPP

The paper will describe the Development of a general three-dimensional multiple grid zone Navier-Stokes flowfield simulation program (ENS3D-MPP) designed for efficient execution on the Intel Paragon Massively Parallel Processor (MPP) supercomputer, and the subsequent application of this method to the prediction of the viscous flowfield about the V-22 Osprey tiltrotor vehicle. The flowfield simulation code solves the thin Layer or full Navier-Stoke's equation - for viscous flow modeling, or the Euler equations for inviscid flow modeling on a structured multi-zone mesh. In the present paper only viscous simulations will be shown. The governing difference equations are solved using a time marching implicit approximate factorization method with either TVD upwind or central differencing used for the convective terms and central differencing used for the viscous diffusion terms. Steady state or Lime accurate solutions can be calculated. The present paper will focus on steady state applications, although time accurate solution analysis is the ultimate goal of this effort. Laminar viscosity is calculated using Sutherland's law and the Baldwin-Lomax two layer algebraic turbulence model is used to compute the eddy viscosity. The Simulation method uses an arbitrary block, curvilinear grid topology. An automatic grid adaption scheme is incorporated which concentrates grid points in high density gradient regions. A variety of user-specified boundary conditions are available. This paper will present the application of the scalable and superscalable versions to the steady state viscous flow analysis of the V-22 Osprey using a multiple zone global mesh. The mesh consists of a series of sheared cartesian grid blocks with polar grids embedded within to better simulate the wing tip mounted nacelle. MPP solutions will be shown in comparison to equivalent Cray C-90 results and also in comparison to experimental data. Discussions on meshing considerations, wall clock execution time, load balancing, and scalability will be provided.

Vadyak, Joseph↗
NASA NTRS2002

NASA's Hall Thruster Program 2002

The NASA Hall thruster program currently supports a number of tasks related to high power thruster development for a number of customers including the Energetics Program (formerly called the Space-based Program), the Space Solar Power Program, and the In-space Propulsion Program. In program year 2002, two tasks were central to the NASA Hall thruster program: 1) the development of a laboratory Hall thruster capable of providing high thrust at high power-, and 2) investigations into operation of Hall thrusters at high specific impulse. In addition to these two primary thruster development activities, there are a number of other on-going activities supported by the NASA Hall thruster program. These additional activities are related to issues such as high-power power processor architecture, thruster lifetime, and spacecraft integration.

Jankovsky, Robert S.↗