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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 595 records · Page 33

Qualification of emerging point-of-load regulators for next generation power systems

As demand for high-speed, on-board, digital-processing integrated circuits (ICs) on spacecraft increases (FPGAs and DSPs in particular), the need for the next generation point-of-load (POL) regulator becomes a prominent design issue. Shrinking process nodes have resulted in core rails dropping to values close to 1.0 V, drastically reducing margin to standard switching converters or regulators that power digital ICs. The objectives of this study are to first identify reliability issues or additional space reliability requirements that might not be addressed for commercial application of POL converters; second, to study the performances of existing or emerging POL converters (including linear regulators) within a practical two-stage power distribution architecture; and, finally, to identify points of failure at extreme temperatures (low and high) beyond specifications.

Leon, Rosa↗

Single-event transient testing of low dropout PNP series linear voltage regulators

As demand for high-speed, on-board, digital-processing integrated circuits on spacecraft increases (field-programmable gate arrays and digital signal processors in particular), the need for the next generation point-of-load (POL) regulator becomes a prominent design issue. Shrinking process nodes have resulted in core rails dropping to values close to 1.0 V, drastically reducing margin to standard switching converters or regulators that power digital ICs. The goal of this task is to perform SET characterization of several commercial POL converters, and provide a discussion of the impact of these results to state-of-the-art digital processing IC through laser and heavy ion testing

Allen, Gregory↗

A Low SWaP-C prototype Ka-band Frequency Synthesizer for Atomic Clocks

We present a low size, weight, power and cost (SWaP-C) prototype circuit of a Ka-band frequency synthesizer. It takes advantage of a phase-locked loop single integrated circuit (IC) and harmonic generation with high speed CMOS gates. We use a direct digital synthesizer (DDS) IC to tune the final output with microHertz resolution. An ultra-low-power micro controller that could serve as the clock controller is used to control the PLL and the DDS. All components are commercial off the shelf (COTS) with acceptable industrial support. The total power consumption is about 1.6 Watt with -45 dBm useful output at 40.507347996 GHz. The short-term instability introduced by the prototype is 7.3E-14 at 1s. The prototyped subsystem uses COTS demonstration boards for the sake of agile prototyping. There is still significant margin for improvement of the size and weight.

Tjoelker, Robert L.↗

The Berkeley Sample of Stripped-Envelope Supernovae

We present the complete sample of stripped-envelope supernova (SN) spectra observed by the Lick Observatory Supernova Search (LOSS) collaboration over the last three decades: 888 spectra of 302 SNe, 652 published here for the first time, with 384 spectra (of 92 SNe) having photometrically determined phases. After correcting for redshift and Milky Way dust reddening and reevaluating the spectroscopic classifications for each SN, we construct mean spectra of the three major spectral subtypes (Types IIb, Ib, and Ic) binned by phase. We compare measures of line strengths and widths made from this sample to the results of previous efforts, confirming that OI λ7774 absorption is stronger and found at higher velocity in Type Ic SNe than in Types Ib or IIb SNe in the first ∼30 days after peak brightness, though the widths of nebular emission lines are consistent across subtypes. We also highlight newly available observations for a few rare subpopulations of interest.

spectroscopic↗

DC Modeling of 4H-SiC JFET Gate Length Reduction at 500°C

The development of robust, high-performance integrated circuits (ICs) will enable numerous potential NASA missions of current interest, including long-duration robotic missions exploring the 460 °C surface of Venus. Currently, NASA is looking towards SiC-based devices to provide such a solution. However, the current NASA silicon carbide (SiC) JFET device with a channel length of 6μm (for recently fabricated Gen. 11 ICs) limits on mission relevant circuit capabilities [1]. In this study, we combined experiments with simulations to explore two straightforward fabrication strategies to reduce the SiC JFET channel length while maintaining turn-off behavior (Fig. 1a) needed to realize 500 °C circuit operation. The first fabrication strategy uses a shallow self-align nitrogen implant (Figure 1b) along the device's top surface but not below the gate combined with a high-dose phosphorous implant directly below the source and drain contacts. For the second fabrication strategy (Figure 1c), the high-dose phosphorous implants extended from below the contacts all the way up to the gate edges. Simulations guided gate length reductions without significant degradation in the turn-off performance. In total 12 SiC JFET variants implementing using the different fabrication strategies, gate lengths, and n-channel epilayer thickness were implemented in our simulation framework implemented in COMSOL. Since the COMSOL database does not have the material properties for 4H-SiC, these parameters were taken from the literature and implemented in COMSOL. The empirical models [2] for incomplete ionization, Auger recombination, low field mobility, and Shockley-Read-Hall recombination were implemented to account for material-specific device behavior.

4H-SiC JFET↗

DC Modeling of 4H-SiC nJFET Gate Length Reduction at 500°C

The development of robust, high-performance integrated circuits (ICs) will enable numerous potential NASA missions of current interest, including long-duration robotic missions exploring the 460°C surface of Venus. Currently, NASA is looking towards SiC-based devices to provide such a solution. However, the current NASA silicon carbide (SiC) JFET device with a channel length of 6 μm (recently fabricated Gen. 11 ICs) limits mission-relevant circuit capabilities. In this study, we combined experiments with simulations to explore two straightforward fabrication strategies (shallow n− and deep n+) to reduce the SiC JFET channel length while maintaining turn-off behavior needed to realize 500 °C circuit operation. First, the material properties for 4H-SiC were implemented in COMSOL and the Poisson equation was solved for twelve 2D device designs. Then, based on the insights gained from the distribution of the electron concentration, electrostatic potential, and electric field for twelve designs (with three fabrication strategies), simulation for a 1 μm gate length nJFET with the turn-off performance comparable to the state-of-the-art.

4H-SiC nJFET↗

DC Modeling of 4H-SiC nJFET Gate Length Reduction at 500°C

The development of robust, high-performance integrated circuits (ICs) will enable numerous potential NASA missions of current interest, including long-duration robotic missions exploring the 460°C surface of Venus. Currently, NASA is looking towards SiC-based devices to provide such a solution. However, the current NASA silicon carbide (SiC) JFET device with a channel length of 6 μm (recently fabricated Gen. 11 ICs) limits mission-relevant circuit capabilities. In this study, we combined experiments with simulations to explore two straightforward fabrication strategies (shallow n− and deep n+) to reduce the SiC JFET channel length while maintaining turn-off behavior needed to realize 500 °C circuit operation. First, the material properties for 4H-SiC were implemented in COMSOL and the Poisson equation was solved for twelve 2D device designs. Then, based on the insights gained from the distribution of the electron concentration, electrostatic potential, and electric field for twelve designs (with three fabrication strategies), simulation for a 1 μm gate length nJFET with the turn-off performance comparable to the state-of-the-art.

4H-SiC nJFET↗

xEMU Integrated Communication System

For the past several years, the Exploration Extra-Vehicular Mobility Unit (xEMU) team at NASA’s Johnson Space Center (JSC) has focused on development and testing of the xEMU to support missions to the International Space Station (ISS) and a moon landing in 2024. In that context, this paper examines the development and detailed design of the xEMU Integrated Communication System (ICS). This paper outlines the challenging technical requirements, significant architectural trades, technical solutions required to overcome these challenges, and a status of the detailed design. The preliminary results of Design Verification Testing (DVT) as it relates to the ICS are also provided, along with a forward strategy for final maturation into a flight-ready design.

Ian Meginnis↗

A Brief Overview of Relevant Silicon Carbide Electronics and Sensor Development for Long Duration Venus Surface Exploration

This presentation concentrates on the potential of long duration Venus surface missions, and the role of Silicon Carbide (SiC) electronics and sensor advancements in such exploration. For example, SiC integrated circuit (IC) electronics have matured to a state where a simple long-life scientific probe is feasible for extended Venus surface operations. These electronics have been demonstrated for more than a year at 500˚C, and 60 days in high-fidelity simulated Venus surface conditions [1-2]. Further, high temperature chemical sensing technology, including SiC-based gas sensors, integrated with SiC electronics can enable future exploration of the Venus surface atmosphere [3]. Continued maturation of these high temperature electronics and sensors has been part of the Long-Lived In-Situ Solar System Explorer (LLISSE) project to provide an operational system for in situ exploration of the Venus surface up to 60 days [4]. A key focus of this work includes increasing the complexity and decreasing the power consumption of the ICs which will pave the way to enhanced capabilities, such as long-duration Venus seismic measurements and other mission capabilities currently under development. This is in parallel to work expanding the capabilities of the sensor technology to provide science measurements on the Venus surface. This presentation will give an overview of possible extended duration Venus surface exploration and some of the SiC-based technologies that can enable this exploration.

high temperature Venus surface electronics sensors↗

Machine Learning Framework for Hazard Extraction and Analysis of Trends (HEAT) in Wildfire Response

This research proposes a natural language processing enabled risk analysis framework, named Hazard Extraction andAnalysis of Trends (HEAT), and applies the framework to the ICS-209-PLUS data set of wildfire incident responseforms. The HEAT framework produces safety- and risk- relevant analyses, consisting of: (1) a set of hazards extractedfrom text data, (2) a primary analysis using hazard-relevant metrics, such as rate and severity, to form an FMEA-styletable and risk matrix, (3) a time series analysis of metric trends, and (4) a secondary analysis examining potentialpredictors for hazards. Results from HEAT provide quantitative risk-relevant information for high-level hazards doc-umented in existing-state operations. Because of the generalizability of the steps and limited data requirements, HEATcan be applied to any dataset containing narrative text, thus providing a framework for data-driven machine learning-enabled quantitative risk analysis across a variety of domains. To demonstrate HEAT in a case study, we apply theframework to the ICS-209-PLUS dataset of wildland fire incident response forms. Hazards identified in wildfire re-sponse arise from environmental conditions, the mission, and the wildland urban interface. The resulting risk matrixidentifies evacuations as high-risk hazards, while all other identified hazards are medium or serious risk.

natural language processing↗

Interlaminar R-Curve Effects in Thermoplastic Composites: Experiments and Model Correlations

The interlaminar fracture behavior of thermoplastic composites under Mode-I and Mode-II static loading is investigated in this research. The material system under consideration is a carbon fiber reinforced low melt semi-crystalline resin TC1225 LMPAEK T700G (T700/LMPAEK)†. Characterization experiments were conducted to measure the load-displacement response, peak load, and propagation of delamination from a pre-implanted Kapton® insert. The Mode-I response was characterized using a double cantilever beam (DCB) test according to the ASTM D5528-22 standard. It was observed that the propagation exhibited significant resistance to delamination growth, i.e., an R-Curve effect. The test data indicated that the steady-state fracture toughness, G SS I , was approximately twice the mean initiation fracture toughness, G Ic . The Mode-II response of an end notch flexure (ENF) specimen tested according to the ASTM D7905-19 standard exhibited an unexpected stable behavior upon attaining peak load. Prior to attaining peak load, the Mode-II response exhibited some non-linearity, which may be attributed to nonlinear bulk material response, e.g., hyper-elasticity, viscoelasticity, plasticity, etc., and potentially friction at the load/support rollers and R-Curve effects. Finite element models based on the Cohesive Zone Method (CZM) and the Virtual Crack Closure Technique (VCCT) were used to predict the DCB and ENF specimen responses. DCB analysis results obtained using G SS I predicted propagation consistent with experimental data. However, results obtained with the as characterized G Ic were inaccurate in predicting delamination growth onset and peak load. ENF analysis results obtained with the as-characterized Mode-II fracture toughness, G IIc , were inaccurate in predicting the peak load and propagation. Hence, R-Curve effects were included in both DCB and ENF simulations, which enabled improved predictions. The experimentally determined Mode-I R-Curve was used for the DCB simulations, whereas an R-Curve was derived for Mode-II assuming that the change in compliance of the specimen was associated with crack growth only.

Prabhakar M Rao↗

High Temperature Devices for Aerospace Applications

This presentation will overview important new capabilities and benefits that next-generation higher temperature electronics promise for a variety of aerospace systems and missions. Initial aerospace infusions of higher temperature electronics to be discussed include jet engines and the prolonged robotic exploration of the Venus surface. Complete redesign of systems compared to prior conventional electronics practices would yield the most revolutionary benefits. However, the inherent higher risk and expense associated with new technology adoption will likely drive a more evolutionary technology infusion process, especially since flight qualification demands large safety margins and testing that ensures reliable operation for far longer than actual mission duration. SiC pn-junction based devices are inherently capable of the most durable operation at the highest application temperatures compared other transistor technologies, but such integrated circuits (ICs) will never achieve integration levels near today’s silicon ICs. Extreme temperature high-power devices will also be de-rated compared to room-temperature performance. While the high temperature market will always be small compared to the conventional temperature mass-market, compatibility and leveraging of existing foundry manufacturing is vital to the establishment of a sustainable high temperature electronics ecosystem sufficient to significantly improve aerospace systems.

High Temperature↗

Interlaminar R-Curve Effects in Thermoplastic Composites: Experiments and Model Correlations

The interlaminar fracture behavior of thermoplastic composites under Mode-I and Mode-II static loading is investigated in this research. The material system under consideration is a carbon fiber reinforced low melt semi-crystalline resin TC1225 LMPAEK T700G (T700/LMPAEK)†. Characterization experiments were conducted to measure the load-displacement response, peak load, and propagation of delamination from a pre-implanted Kapton® insert. The Mode-I response was characterized using a double cantilever beam (DCB) test according to the ASTM D5528-22 standard. It was observed that the propagation exhibited significant resistance to delamination growth, i.e., an R-Curve effect. The test data indicated that the steady-state fracture toughness, G SS I , was approximately twice the mean initiation fracture toughness, G Ic . The Mode-II response of an end notch flexure (ENF) specimen tested according to the ASTM D7905-19 standard exhibited an unexpected stable behavior upon attaining peak load. Prior to attaining peak load, the Mode-II response exhibited some non-linearity, which may be attributed to nonlinear bulk material response, e.g., hyper-elasticity, viscoelasticity, plasticity, etc., and potentially friction at the load/support rollers and R-Curve effects. Finite element models based on the Cohesive Zone Method (CZM) and the Virtual Crack Closure Technique (VCCT) were used to predict the DCB and ENF specimen responses. DCB analysis results obtained using G SS I predicted propagation consistent with experimental data. However, results obtained with the as characterized G Ic were inaccurate in predicting delamination growth onset and peak load. ENF analysis results obtained with the as-characterized Mode-II fracture toughness, G IIc , were inaccurate in predicting the peak load and propagation. Hence, R-Curve effects were included in both DCB and ENF simulations, which enabled improved predictions. The experimentally determined Mode-I R-Curve was used for the DCB simulations, whereas an R-Curve was derived for Mode-II assuming that the change in compliance of the specimen was associated with crack growth only.

Prabhakar Rao↗

Venus Surface Environmental Chamber Test of SiC JFET-R Multi-Chip Circuit Board

This poster describes a first attempt to demonstrate a multi-chip prototype lander control and sensor signal digitization electronics circuit board comprised of ten NASA Glenn IC Generation 11 SiC JFET-R IC chips in 460 °C, 9.4 MPa harsh Venus surface conditions. The lander circuit ceased electrical operation prematurely at 107 °C as the Venus chamber heated up. Optical and SEM post-test inspections indicate fatal dielectric cracks occurred on only one of the ten SiC chips.

silicon carbide↗

Interface Consistency: Phase I Results & Phase II Status

Future exploration missions will rely on designing and developing vehicles and complex systems from within NASA and through multiple external commercial partners to meet mission goals. Despite existing consistency-related agency requirements, NASA’s approach to commercial spaceflight development encourages providers’ flexibility and innovation. This strategy is resulting in significant design diversity across Artemis vehicles. Design best practices and guidelines champion interface consistency to promote mental model development and knowledge transfer. However, research investigating the benefits of consistency is mixed, and little is known about its role in complex systems. Determining the level of risk that system diversity presents is difficult, as there is no established method for quantifying the degree of consistency within and across interfaces, nor is there information about the differential impacts of different types of inconsistency. Phase I of this project (Characterization and Measurement) served as a starting point to better understand the construct of consistency, its application, and the range of studies and methods for measuring it. The project team created a taxonomy of consistency to apply to interfaces as a framework to guide the development of tools to assess intersystem consistency. Checklist and cognitive walkthrough methods were developed for use by human factors (HF) and human-computer interaction (HCI) experts. The Intersystem Consistency Scale (ICS) was developed for interface evaluations with crew. A pilot study evaluated the methods’ ability to distinguish differences between Artemis-like prototype pairs exhibiting either high or low design consistency. In addition, click errors and time on task were collected within the ICS (crew-like) group. Results from our exploratory analysis and lessons learned from the pilot study will be discussed. The project team will also present the status of Phase II (Risk Assessment, Standards and Guidelines). This includes incorporating feedback to redesign the assessment tools, and inputs from displays and training Subject Matter Experts to update tasks and prototype designs. The team will present the risk assessment study design to identify the types and levels of inconsistency that pose the greatest risk to performance. Plans to apply these results toward agency standards and guideline recommendations will also be discussed.

Human-Computer Interaction↗

SECURED: Simulator-Enhanced Control and Understanding of Reactor systems for cyber-Event Defense

The study discusses a learning approach for analyzing cyber-events in reactor systems using integrated hardware and personal computer simulator models. Key points include the rise in cyber-attacks and their sophistication in industrial control systems (ICS), the necessity for awareness, understanding, resource allocation, and preparation to combat these threats, and the digital transformation of old and new nuclear plants, increasing their exposure to cyber threats. It highlights the cyber vulnerabilities of advanced reactor systems, which rely on digital instrumentation and control for operations and safety functions, making them susceptible to cyber-attacks. The approach involves demonstrating reactor system plant ICS cyber-attacks under various operational conditions utilizing tools like simulator models and hardware-based kits. A strategic solution approach tailored to critical infrastructure is emphasized, along with community engagement for public and government support, adopting effective learning approaches, and the preparation for anticipated future challenges. The presentation concludes with a call to action to address challenges, leverage opportunities, and advance through lesson learning in cybersecurity for nuclear energy systems.

21 SPECIFIC NUCLEAR REACTORS AND ASSOCIATED PLANTS↗

Adapting Traditional Hazards Analysis Methods to Address Cyber Risks

Traditional hazards analysis (HA) methods, originally developed to address physical and operational risks, often fall short when it comes to identifying and mitigating cyber threats. These cyber threats pose unique and evolving risks to critical infrastructure and industrial control systems (ICS). This report explores the integration of Cyber-Informed Engineering (CIE) principles into existing HA methods to enhance their ability to address cyber-induced risks. CIE provides organizations with a practical, cost-effective approach to closing the gap between traditional HA methods and the need for cyber risk mitigation. By leveraging existing safety processes and controls, CIE allows users to examine and mitigate cyber vulnerabilities without overhauling existing HA methods. This report identifies areas where HA and CIE naturally align and where their approaches diverge. It emphasizes how CIE principles can be used to adapt HA methods, broadening their scope to include cyber risks and enabling the mitigation of cyber- induced impacts alongside traditional hazards and failure scenarios. This report examines how CIE can be applied across various HA methods—such as Hazard and Operability Studies (HAZOP), Probabilistic Risk Assessment (PRA), Failure Modes and Effects Analysis (FMEA), Systems-Theoretic Process Analysis (STPA), Hazard and Consequence Analysis for Digital Systems (HAZCADS), and Layers of Protection Analysis (LOPA). It provides strategies for integrating CIE to strengthen the identification, assessment, and mitigation of cyber-induced risks. The findings offer a structured entry point for organizations to embed CIE concepts into hazards and safety analyses, as well as broader engineering processes, ultimately supporting the design and operation of a more resilient infrastructure.

42 ENGINEERING↗

Adapting Traditional Hazards Analysis Methods to Address Cyber Risks

Traditional hazards analysis (HA) methods, originally developed to address physical and operational risks, often fall short when it comes to identifying and mitigating cyber threats. These cyber threats pose unique and evolving risks to critical infrastructure and industrial control systems (ICS). This report explores the integration of Cyber-Informed Engineering (CIE) principles into existing HA methods to enhance their ability to address cyber-induced risks. CIE provides organizations with a practical, cost-effective approach to closing the gap between traditional HA methods and the need for cyber risk mitigation. By leveraging existing safety processes and controls, CIE allows users to examine and mitigate cyber vulnerabilities without overhauling existing HA methods. This report identifies areas where HA and CIE naturally align and where their approaches diverge. It emphasizes how CIE principles can be used to adapt HA methods, broadening their scope to include cyber risks and enabling the mitigation of cyber- induced impacts alongside traditional hazards and failure scenarios. This report examines how CIE can be applied across various HA methods—such as Hazard and Operability Studies (HAZOP), Probabilistic Risk Assessment (PRA), Failure Modes and Effects Analysis (FMEA), Systems-Theoretic Process Analysis (STPA), Hazard and Consequence Analysis for Digital Systems (HAZCADS), and Layers of Protection Analysis (LOPA). It provides strategies for integrating CIE to strengthen the identification, assessment, and mitigation of cyber-induced risks. The findings offer a structured entry point for organizations to embed CIE concepts into hazards and safety analyses, as well as broader engineering processes, ultimately supporting the design and operation of a more resilient infrastructure.

42 - ENGINEERING↗