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At least 595 records · Page 33

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DOE OSTI2020

Panel Session 70: Nuclear Power Plant Waste Management, LLRW Processing Issues

This panel focused on senior utility managers discussing issues with commercial LLW processors. LLW processors had an opportunity to update utilities/NPPs on new or different services or technologies being offered to assist in their radioactive waste management goals, changes to their facility license, revisions to their acceptance guidelines, and emerging compliance issues. Panelists with presentations: UniTech - 'Expanding to Reduce Costs' LLW Processor Update (Gregg Johnstone); Veolia Nuclear Solutions Federal Services - Alaron Nuclear Services (Dave Garber); EnergySolutions Tennessee Processing Facilities (Fred Schulz); Complex Waste Management Issues Services and Treatment Facilities (George M. Taylor)

12 MANAGEMENT OF RADIOACTIVE AND NON-RADIOACTIVE W↗

DOE OSTI2024

Event detection unit

An event detection unit (EDU) for detecting an explosive event is provided. The EDU includes different types of sensors for measuring characteristics of an explosive event. The EDU includes an event notification component. The EDU also includes a processor that receives a measurement from the sensors and generates a combined non-event probability and a combined event probability based on that measurement that indicates a likelihood that an explosive event has not occurred or has occurred. The processor determines whether an explosive event has occurred based on the non-event probabilities and event probabilities. When an explosive event has been determined to occur, the processor directs the event notification component to output a notification that an explosive event has occurred.

Candy, James Vincent↗

DOE OSTI2024

Ripple-type control of networked physical systems

Techniques for ripple-type control of networked physical systems such as power systems, water systems, and others are provided. As one example, a device includes at least one processor configured to determine, for a first controllable device in a system, based on a measurement of an output parameter and a minimum output parameter value, an output violation value for the first device. The processor is further configured to determine, based on a present input value for the first device, the output violation value, and an assistance requisition value corresponding to a second device, a target input value for the first device. The processor is further configured to cause the first controllable device to modify operation based on the target input value and a maximum input value for the first controllable device.

Cavraro, Guido↗

DOE OSTI2024

Systems and methods for predictive lane change

A system includes a controller comprising at least one processor coupled to a memory storing instructions that, when executed by the at least one processor, cause the at least one processor to perform operations comprising: receiving information indicative of operation of the vehicle and of a driving condition for the vehicle; determining that a speed of the vehicle is less than a target speed for the vehicle based on the received information; determining, in response to the determination that the speed is less than the target speed, that the lane change and takeover event is at least one of feasible or efficient based on the received information; and providing, in response to the determination regarding the lane change and takeover event, a notification.

Borhan, Hoseinali↗

DOE OSTI2016

VTK-m: Accelerating the Visualization Toolkit for Massively Threaded Architectures

Execution on massively threaded processors is one of the most critical challenges for high-performance computing (HPC) scientific visualization. Of the many fundamental changes we are seeing in HPC systems, one of the most profound is a reliance on new processor types optimized for execution bandwidth over latency hiding. Moreover, our current production scientific visualization software is not designed for these new types of architectures. In order to address this issue, the VTK-m framework serves as a container for algorithms, provides flexible data representation, and simplifies the design of visualization algorithms on new and future computer architecture.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2020

Andes Data Analysis System at the Oak Ridge Leadership Computing Facility

Andes is a (704)-node commodity-type Linux® cluster. Each of Andes’s 704 nodes contain two 16-core 3.0 GHz AMD EPYC 7302 processors with AMD’s Simultaneous Multithreading (SMT) Technology and 256GB of main memory. Andes also has nine large memory GPU nodes. These nodes each have 1TB of main memory and two NVIDIA K80 GPUs with two 14-core 2.30 GHz Intel Xeon processors with HT Technology.

AMD EPYC↗

DOE OSTI2014

Preliminary Feasibility Assessment of Integrating CCHP with NW Food Processing Plant #1: Modeling Documentation

The Pacific Northwest National Laboratory (PNNL) has launched a project funded by the Bonneville Power Association (BPA) to identify strategies for increasing industrial energy efficiency and reducing energy costs of Northwest Food Processors Association (NWFPA) plants through deployment of novel combinations and designs of variable-output combined heat and power (CHP) distributed generation (DG), combined cooling, heating and electric power (CCHP) DG and energy storage systems. Detailed evaluations and recommendations of CHP and CCHP DG systems will be performed for several Northwest (NW) food processing sites. The objective is to reduce the overall energy use intensity of NW food processors by 25% by 2020 and by 50% by 2030, as well as reducing emissions and understanding potential congestion reduction impacts on the transmission system in the Pacific Northwest.

Bonneville Power Association↗

DOE OSTI2024

Identification of Defects and the Origins of Surface Noise on Hydrogen–Terminated (100) Diamond

Near-surface nitrogen vacancy centres are critical to many diamond-based quantum technologies such as information processors and nanosensors. Surface defects play an important role in the design and performance of these devices. The targeted creation of defects is central to proposed bottom-up approaches to nanofabrication of quantum diamond processors, and uncontrolled surface defects may generate noise and charge trapping which degrade shallow NV device performance. Surface preparation protocols may be able to control the production of desired defects and eliminate unwanted defects, but only if their atomic structure can first be conclusively identified. This work uses a combination of scanning tunnelling microscopy (STM) imaging and first-principles simulations to identify several surface defects on H:C(100)—2 × 1 surfaces prepared using chemical vapour deposition (CVD). The atomic structure of these defects is elucidated, from which the microscopic origins of magnetic noise and charge trapping are determined based on the modeling of their paramagnetic properties and acceptor states. Rudimentary control of these deleterious properties is demonstrated through STM tip-induced manipulation of the defect structure. Furthermore, the results validate accepted models for CVD diamond growth by identifying key adsorbates responsible for the nucleation of new layers.

36 MATERIALS SCIENCE↗

DOE OSTI2019

Simulation of unsteady blood flows in a patient-specific compliant pulmonary artery with a highly parallel monolithically coupled fluid-structure interaction algorithm

Computational fluid dynamics (CFD) is increasingly used to study blood flows in patient-specific arteries for understanding certain cardiovascular diseases. The techniques work quite well for relatively simple problems, but need improvements when the problems become harder in the case when (1) the geometry becomes complex (from a few branches to a full pulmonary artery), (2) the model becomes more complex (from fluid-only calculation to coupled fluid-structure interaction calculation), (3) both the fluid and wall models become highly nonlinear, and (4) the computer on which we run the simulation is a supercomputer with tens of thousands of processor cores. To push the limit of CFD in all four fronts, in this paper, we develop and study a highly parallel algorithm for solving a monolithically coupled fluid-structure system for the modeling of the interaction of the blood flow and the arterial wall. As a case study, we consider a patient-specific, full size pulmonary artery obtained from CT (Computed Tomography) images, with an artificially added layer of wall with a fixed thickness. The fluid is modeled with a system of incompressible Navier-Stokes equations and the wall is modeled by a geometrically nonlinear elasticity equation. As far as we know this is the first time the unsteady blood flow in a full pulmonary artery is simulated without assuming a rigid wall. We report the proposed numerical algorithm and software scale well beyond 10,000 processor cores on a supercomputer for solving the fluid-structure interaction problem discretized with a stabilized finite element method in space and an implicit scheme in time involving hundreds of millions of unknowns.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2013

Performance modeling of microsecond scale biological molecular dynamics simulations on heterogeneous architectures

Performance improvements in biomolecular simulations based on molecular dynamics (MD) codes are widely desired. Unfortunately, the factors, which allowed past performance improvements, particularly the microprocessor clock frequencies, are no longer increasing. Hence, novel software and hardware solutions are being explored for accelerating performance of widely used MD codes. In this paper, we describe our efforts on porting, optimizing and tuning of Large-scale Atomic/Molecular Massively Parallel Simulator, a popular MD framework, on heterogeneous architectures: multi-core processors with graphical processing unit (GPU) accelerators. Our implementation is based on accelerating the most computationally expensive non-bonded interaction terms on the GPUs and overlapping the computation on the CPU and GPUs. This functionality is built on top of message passing interface that allows multi-level parallelism to be extracted even at the workstation level with the multi-core CPUs and allows extension of the implementation on GPU-enabled clusters. We hypothesize that the optimal benefit of heterogeneous architectures for applications will come by utilizing all possible resources (for example, CPU-cores and GPU devices on GPU-enabled clusters). Benchmarks for a range of biomolecular system sizes are provided, and an analysis is performed on four generations of NVIDIA's GPU devices. On GPU-enabled Linux clusters, by overlapping and pipelining computation and communication, we observe up to 10-folds application acceleration in multi-core and multi-GPU environments illustrating significant performance improvements. Detailed analysis of the implementation is presented that allows identification of bottlenecks in algorithm, indicating that code optimization and improvements on GPUs could allow microsecond scale simulation throughput on workstations and inexpensive GPU clusters, putting widely desired biologically relevant simulation time-scales within reach of a large user community. In order to systematically optimize simulation throughput and to enable performance prediction, we have developed a parameterized performance model that will allow developers and users to explore the performance potential of future heterogeneous systems for biological simulations.

Agarwal, Pratul K.↗

DOE OSTI2016

Global‐view coefficients: a data management solution for parallel quantum Monte Carlo applications

Summary Quantum Monte Carlo (QMC) applications perform simulation with respect to an initial state of the quantum mechanical system, which is often captured by using a cubic B‐spline basis. This representation is stored as a read‐only table of coefficients and accesses to the table are generated at random as part of the Monte Carlo simulation. Current QMC applications, such as QWalk and QMCPACK, replicate this table at every process or node, which limits scalability because increasing the number of processors does not enable larger systems to be run. We present a partitioned global address space approach to transparently managing this data using Global Arrays in a manner that allows the memory of multiple nodes to be aggregated. We develop an automated data management system that significantly reduces communication overheads, enabling new capabilities for QMC codes. Experimental results with QWalk and QMCPACK demonstrate the effectiveness of the data management system. Copyright © 2016 John Wiley & Sons, Ltd.

Niu, Qingpeng↗

DOE OSTI2023

HIPLZ: Enabling performance portability for exascale systems

While heterogeneous computing has emerged as a dominant trend in current and future High-Performance Computing (HPC) systems, it is also widely recognized that this shift has led to increased software complexity due to a proliferation of programming systems for different heterogeneous processors. One such example is the Heterogeneous-Compute Interface for Portability from AMD (HIP ), which is composed of a C Runtime API and C++ Kernel Language. Many HPC applications will likely use HIP on future exascale systems (e.g., Frontier and El Capitan), but HIP currently only targets AMD and NVIDIA processors. This limitation creates challenges for users who would also like to run their applications on exascale systems based on other architectures (e.g., Aurora, which is based on Intel hardware) that are currently not targeted by HIP . In this paper, we introduce the design and implementation of HIPLZ , a compiler and runtime system that uses the Intel Level Zero API to support HIP on Intel GPU architectures. We discuss the design of HIPLZ , derived from HIPCL (an implementation of HIP on top of OpenCL ), and portability issues that occur from using the Level Zero runtime as a backend. We evaluate our implementation by running several performance benchmarks and mini-apps written in HIP on Intel architectures using HIPLZ . Our results show that this approach provides competitive performance relative to Intel's OpenCL implementations on Intel Gen9 and UHD Graphics 770 GPUs, while providing good coverage of features needed by HPC applications. Overall, this approach is a promising demonstration of enabling performance portability for exascale systems.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2016

Parallel FETI‐DP algorithm for efficient simulation of large‐scale EM problems

Summary An efficient parallelization of the dual‐primal finite‐element tearing and interconnecting (FETI‐DP) algorithm is presented for large‐scale electromagnetic simulations. As a nonoverlapping domain decomposition method, the FETI‐DP algorithm formulates a global interface problem, whose iterative solution is accelerated with a solution of a global corner problem. To achieve a good load balance for parallel computation, the original computational domain is decomposed into subdomains with similar sizes and shapes. The subdomains are then distributed to processors based on their close proximity to minimize inter‐processor communication. The parallel generalized minimal residual method, enhanced with the iterative classical Gram‐Schmidt orthogonalization scheme to reduce global communication, is adopted to solve the global interface problem with a fast convergence rate. The global corner‐related coarse problem is solved iteratively with a parallel communication‐avoiding biconjugate gradient stabilized method to minimize global communication, and its convergence is accelerated by a diagonal preconditioner constructed from the coarse system matrix. To alleviate neighboring communication overhead, the non‐blocking communication approach is employed in both generalized minimal residual and communication‐avoiding biconjugate gradient stabilized iterative solutions. Three numerical examples are presented to demonstrate the accuracy, scalability, and capability of the proposed parallel FETI‐DP algorithm for electromagnetic modeling of general objects and antenna arrays. Copyright © 2016 John Wiley & Sons, Ltd.

Zhang, Kedi↗

DOE OSTI2019

Using Compiler Directives for Performance Portability in Scientific Computing: Kernels from Molecular Simulation

Achieving performance portability for high-performance computing (HPC) applications in scientific fields has become an increasingly important initiative due to large differences in emerging supercomputer architectures. Here we test some key kernels from molecular dynamics (MD) to determine whether the use of the OpenACC directive-based programming model when applied to these kernels can result in performance within an acceptable range for these types of programs in the HPC setting. We find that for easily parallelizable kernels, performance on the GPU remains within this range. On the CPU, OpenACC-parallelized pairwise distance kernels would not meet the performance standards required, when using AMD Opteron “Interlagos” processors, but with IBM Power 9 processors, performance remains within an acceptable range for small batch sizes. These kernels provide a test for achieving performance portability with compiler directives for problems with memory-intensive components as are often found in scientific applications.

Sedova, Ada↗

DOE OSTI2018

A non-intrusive parallel-in-time adjoint solver with the XBraid library

In this paper, an adjoint solver for the multigrid-in-time software library XBraid is presented. XBraid provides a non-intrusive approach for simulating unsteady dynamics on multiple processors while parallelizing not only in space but also in the time domain (XBraid: Parallel multigrid in time, http://llnl.gov/casc/xbraid). It applies an iterative multigrid reduction in time algorithm to existing spatially parallel classical time propagators and computes the unsteady solution parallel in time. Techniques from Automatic Differentiation are used to develop a consistent discrete adjoint solver which provides sensitivity information of output quantities with respect to design parameter changes. The adjoint code runs backwards through the primal XBraid actions and accumulates gradient information parallel in time. It is highly non-intrusive as existing adjoint time propagators can easily be integrated through the adjoint interface. The adjoint code is validated on advection-dominated flow with periodic upstream boundary condition. We report it provides similar strong scaling results as the primal XBraid solver and offers great potential for speeding up the overall computational costs for sensitivity analysis using multiple processors.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2021

Multilevel Graph Partitioning for Three-Dimensional Discrete Fracture Network Flow Simulations

We present a topology-based method for mesh-partitioning in three-dimensional discrete fracture network (DFN) simulations that takes advantage of the intrinsic multi-level nature of a DFN. DFN models are used to simulate flow and transport through low-permeability fractured media in the subsurface by explicitly representing fractures as discrete entities. The governing equations for flow and transport are numerically integrated on computational meshes generated on the interconnected fracture networks. Modern high-fidelity DFN simulations require high-performance computing on multiple processors where performance and scalability depends partially on obtaining a high-quality partition of the mesh to balance work-loads and minimize communication across all processors. The discrete structure of a DFN naturally lends itself to various graph representations, which can be thought of as coarse-scale representations of the computational mesh. Using this concept, we develop two applications of the multilevel graph partitioning algorithm to partition the mesh of a DFN. In the first, we project a partition of the graph based on the DFN topology onto the mesh of the DFN and in the second, this DFN-based projection is used as the initial condition for further partitioning refinement of the mesh. We compare the performance of these methods with standard multi-level graph partitioning using graph-based metrics (cut, imbalance, partitioning time), computational-based metrics (FLOPS, iterations, solver time), and total run time. The DFN-based and the mesh-based partitioning methods are comparable in terms of the graph-based metrics, but the time required to obtain the partition is several orders of magnitude faster using the DFN-based partitions. The computation-based metrics show comparable performance between both methods so, in combination, the DFN-based partitions are several orders of magnitude faster than the mesh-based partition. Furthermore, the method which uses the DFN-partition solution as the initial condition of the mesh partition provided cut and imbalance values that were close to the mesh-based partition but in a fraction of the time. In turn, this hybrid method outperformed both of the other methods in terms of the total run time.

58 GEOSCIENCES↗

DOE OSTI2017

A performance study of the time-varying cache behavior: a study on APEX, Mantevo, NAS, and PARSEC

Cache has long been used to minimize the latency of main memory accesses by storing frequently used data near the processor. Processor performance depends on the underlying cache performance. Therefore, significant research has been done to identify the most crucial metrics of cache performance. Although the majority of research focuses on measuring cache hit rates and data movement as the primary cache performance metrics, cache utilization is significantly important. We investigate the application’s locality using cache utilization metrics. In addition, we present cache utilization and traditional cache performance metrics as the program progresses providing detailed insights into the dynamic application behavior on parallel applications from four benchmark suites running on multiple cores. We explore cache utilization for APEX, Mantevo, NAS, and PARSEC, mostly scientific benchmark suites. Our results indicate that 40% of the data bytes in a cache line are accessed at least once before line eviction. Also, on average a byte is accessed two times before the cache line is evicted for these applications. Moreover, we present runtime cache utilization, as well as, conventional performance metrics that illustrate a holistic understanding of cache behavior. To facilitate this research, we build a memory simulator incorporated into the Structural Simulation Toolkit (Rodrigues et al. in SIGMETRICS Perform Eval Rev 38(4):37–42, 2011). Finally, our results suggest that variable cache line size can result in better performance and can also conserve power.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2021

Quantum Divide and Compute: Exploring the Effect of Different Noise Sources

Abstract Our recent work (Ayral et al. in Proceedings of IEEE computer society annual symposium on VLSI, ISVLSI, pp 138–140, 2020. 10.1109/ISVLSI49217.2020.00034 ) showed the first implementation of the Quantum Divide and Compute (QDC) method, which allows to break quantum circuits into smaller fragments with fewer qubits and shallower depth. This accommodates the limited number of qubits and short coherence times of quantum processors. This article investigates the impact of different noise sources—readout error, gate error and decoherence—on the success probability of the QDC procedure. We perform detailed noise modeling on the Atos Quantum Learning Machine, allowing us to understand tradeoffs and formulate recommendations about which hardware noise sources should be preferentially optimized. We also describe in detail the noise models we used to reproduce experimental runs on IBM’s Johannesburg processor. This article also includes a detailed derivation of the equations used in the QDC procedure to compute the output distribution of the original quantum circuit from the output distribution of its fragments. Finally, we analyze the computational complexity of the QDC method for the circuit under study via tensor-network considerations, and elaborate on the relation the QDC method with tensor-network simulation methods.

97 MATHEMATICS AND COMPUTING↗